board/toradex/verdin-imx8mm/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2020 Toradex
   4  */
   5
   6 #include <common.h>
   7 #include <asm/arch/clock.h>
   8 #include <asm/arch/ddr.h>
   9 #include <asm/arch/imx8mm_pins.h>
  10 #include <asm/arch/sys_proto.h>
  11 #include <asm/io.h>
  12 #include <asm/mach-imx/boot_mode.h>
  13 #include <asm/mach-imx/iomux-v3.h>
  14 #include <cpu_func.h>
  15 #include <dm/device.h>
  16 #include <dm/device-internal.h>
  17 #include <dm/uclass.h>
  18 #include <dm/uclass-internal.h>
  19 #include <hang.h>
  20 #include <power/bd71837.h>
  21 #include <power/pmic.h>
  22 #include <spl.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 int spl_board_boot_device(enum boot_device boot_dev_spl)
  27 {
  28         switch (boot_dev_spl) {
  29         case MMC1_BOOT:
  30                 return BOOT_DEVICE_MMC1;
  31         case SD2_BOOT:
  32         case MMC2_BOOT:
  33                 return BOOT_DEVICE_MMC2;
  34         case SD3_BOOT:
  35         case MMC3_BOOT:
  36                 return BOOT_DEVICE_MMC1;
  37         case USB_BOOT:
  38                 return BOOT_DEVICE_BOARD;
  39         default:
  40                 return BOOT_DEVICE_NONE;
  41         }
  42 }
  43
  44 void spl_dram_init(void)
  45 {
  46         ddr_init(&dram_timing);
  47 }
  48
  49 void spl_board_init(void)
  50 {
  51         /* Serial download mode */
  52         if (is_usb_boot()) {
  53                 puts("Back to ROM, SDP\n");
  54                 restore_boot_params();
  55         }
  56         puts("Normal Boot\n");
  57 }
  58
  59 #ifdef CONFIG_SPL_LOAD_FIT
  60 int board_fit_config_name_match(const char *name)
  61 {
  62         /* Just empty function now - can't decide what to choose */
  63         debug("%s: %s\n", __func__, name);
  64
  65         return 0;
  66 }
  67 #endif
  68
  69 #define UART_PAD_CTRL   (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
  70 #define WDOG_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  71
  72 /* Verdin UART_3, Console/Debug UART */
  73 static iomux_v3_cfg_t const uart_pads[] = {
  74         IMX8MM_PAD_SAI2_RXFS_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  75         IMX8MM_PAD_SAI2_RXC_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  76 };
  77
  78 static iomux_v3_cfg_t const wdog_pads[] = {
  79         IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  80 };
  81
  82 int board_early_init_f(void)
  83 {
  84         struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  85
  86         imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  87
  88         set_wdog_reset(wdog);
  89
  90         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  91
  92         return 0;
  93 }
  94
  95 int power_init_board(void)
  96 {
  97         struct udevice *dev;
  98         int ret;
  99
 100         ret = pmic_get("pmic@4b", &dev);
 101         if (ret == -ENODEV) {
 102                 puts("No pmic\n");
 103                 return 0;
 104         }
 105         if (ret != 0)
 106                 return ret;
 107
 108         /* decrease RESET key long push time from the default 10s to 10ms */
 109         pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
 110
 111         /* unlock the PMIC regs */
 112         pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
 113
 114         /* increase VDD_SOC to typical value 0.85v before first DRAM access */
 115         pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
 116
 117         /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
 118         pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
 119
 120 #ifndef CONFIG_IMX8M_LPDDR4
 121         /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
 122         pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
 123 #endif
 124
 125         /* lock the PMIC regs */
 126         pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
 127
 128         return 0;
 129 }
 130
 131 void board_init_f(ulong dummy)
 132 {
 133         struct udevice *dev;
 134         int ret;
 135
 136         arch_cpu_init();
 137
 138         init_uart_clk(0);
 139
 140         board_early_init_f();
 141
 142         timer_init();
 143
 144         preloader_console_init();
 145
 146         /* Clear the BSS. */
 147         memset(__bss_start, 0, __bss_end - __bss_start);
 148
 149         ret = spl_early_init();
 150         if (ret) {
 151                 debug("spl_early_init() failed: %d\n", ret);
 152                 hang();
 153         }
 154
 155         ret = uclass_get_device_by_name(UCLASS_CLK,
 156                                         "clock-controller@30380000",
 157                                         &dev);
 158         if (ret < 0) {
 159                 printf("Failed to find clock node. Check device tree\n");
 160                 hang();
 161         }
 162
 163         enable_tzc380();
 164
 165         power_init_board();
 166
 167         /* DDR initialization */
 168         spl_dram_init();
 169
 170         board_init_r(NULL, 0);
 171 }