board/toradex/verdin-imx8mm/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2020 Toradex
   4  */
   5
   6 #include <common.h>
   7 #include <command.h>
   8 #include <image.h>
   9 #include <init.h>
  10 #include <log.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/ddr.h>
  13 #include <asm/arch/imx8mm_pins.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <asm/io.h>
  16 #include <asm/mach-imx/boot_mode.h>
  17 #include <asm/mach-imx/iomux-v3.h>
  18 #include <cpu_func.h>
  19 #include <dm/device.h>
  20 #include <dm/device-internal.h>
  21 #include <dm/uclass.h>
  22 #include <dm/uclass-internal.h>
  23 #include <hang.h>
  24 #include <power/bd71837.h>
  25 #include <power/pmic.h>
  26 #include <spl.h>
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 int spl_board_boot_device(enum boot_device boot_dev_spl)
  31 {
  32         switch (boot_dev_spl) {
  33         case MMC1_BOOT:
  34                 return BOOT_DEVICE_MMC1;
  35         case SD2_BOOT:
  36         case MMC2_BOOT:
  37                 return BOOT_DEVICE_MMC2;
  38         case SD3_BOOT:
  39         case MMC3_BOOT:
  40                 return BOOT_DEVICE_MMC1;
  41         case USB_BOOT:
  42                 return BOOT_DEVICE_BOARD;
  43         default:
  44                 return BOOT_DEVICE_NONE;
  45         }
  46 }
  47
  48 void spl_dram_init(void)
  49 {
  50         ddr_init(&dram_timing);
  51 }
  52
  53 void spl_board_init(void)
  54 {
  55         /* Serial download mode */
  56         if (is_usb_boot()) {
  57                 puts("Back to ROM, SDP\n");
  58                 restore_boot_params();
  59         }
  60         puts("Normal Boot\n");
  61 }
  62
  63 #ifdef CONFIG_SPL_LOAD_FIT
  64 int board_fit_config_name_match(const char *name)
  65 {
  66         /* Just empty function now - can't decide what to choose */
  67         debug("%s: %s\n", __func__, name);
  68
  69         return 0;
  70 }
  71 #endif
  72
  73 #define UART_PAD_CTRL   (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
  74 #define WDOG_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  75
  76 /* Verdin UART_3, Console/Debug UART */
  77 static iomux_v3_cfg_t const uart_pads[] = {
  78         IMX8MM_PAD_SAI2_RXFS_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  79         IMX8MM_PAD_SAI2_RXC_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  80 };
  81
  82 static iomux_v3_cfg_t const wdog_pads[] = {
  83         IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  84 };
  85
  86 int board_early_init_f(void)
  87 {
  88         struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  89
  90         imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  91
  92         set_wdog_reset(wdog);
  93
  94         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  95
  96         return 0;
  97 }
  98
  99 int power_init_board(void)
 100 {
 101         struct udevice *dev;
 102         int ret;
 103
 104         ret = pmic_get("pmic@4b", &dev);
 105         if (ret == -ENODEV) {
 106                 puts("No pmic\n");
 107                 return 0;
 108         }
 109         if (ret != 0)
 110                 return ret;
 111
 112         /* decrease RESET key long push time from the default 10s to 10ms */
 113         pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
 114
 115         /* unlock the PMIC regs */
 116         pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
 117
 118         /* increase VDD_SOC to typical value 0.85v before first DRAM access */
 119         pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
 120
 121         /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
 122         pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
 123
 124 #ifndef CONFIG_IMX8M_LPDDR4
 125         /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
 126         pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
 127 #endif
 128
 129         /* lock the PMIC regs */
 130         pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
 131
 132         return 0;
 133 }
 134
 135 void board_init_f(ulong dummy)
 136 {
 137         struct udevice *dev;
 138         int ret;
 139
 140         arch_cpu_init();
 141
 142         init_uart_clk(0);
 143
 144         board_early_init_f();
 145
 146         timer_init();
 147
 148         preloader_console_init();
 149
 150         /* Clear the BSS. */
 151         memset(__bss_start, 0, __bss_end - __bss_start);
 152
 153         ret = spl_early_init();
 154         if (ret) {
 155                 debug("spl_early_init() failed: %d\n", ret);
 156                 hang();
 157         }
 158
 159         ret = uclass_get_device_by_name(UCLASS_CLK,
 160                                         "clock-controller@30380000",
 161                                         &dev);
 162         if (ret < 0) {
 163                 printf("Failed to find clock node. Check device tree\n");
 164                 hang();
 165         }
 166
 167         enable_tzc380();
 168
 169         power_init_board();
 170
 171         /* DDR initialization */
 172         spl_dram_init();
 173
 174         board_init_r(NULL, 0);
 175 }