board/toradex/colibri_vf/colibri_vf.c

   1 /*
   2  * Copyright 2015 Toradex, Inc.
   3  *
   4  * Based on vf610twr.c:
   5  * Copyright 2013 Freescale Semiconductor, Inc.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/iomux-vf610.h>
  14 #include <asm/arch/ddrmc-vf610.h>
  15 #include <asm/arch/crm_regs.h>
  16 #include <asm/arch/clock.h>
  17 #include <mmc.h>
  18 #include <fdt_support.h>
  19 #include <fsl_esdhc.h>
  20 #include <fsl_dcu_fb.h>
  21 #include <jffs2/load_kernel.h>
  22 #include <miiphy.h>
  23 #include <mtd_node.h>
  24 #include <netdev.h>
  25 #include <i2c.h>
  26 #include <g_dnl.h>
  27 #include <asm/gpio.h>
  28 #include <usb.h>
  29 #include "../common/tdx-common.h"
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 #define UART_PAD_CTRL   (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  34                         PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
  35
  36 #define ESDHC_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
  37                         PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
  38
  39 #define ENET_PAD_CTRL   (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
  40                         PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
  41
  42 #define USB_PEN_GPIO           83
  43 #define USB_CDET_GPIO           102
  44
  45 static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
  46         /* levelling */
  47         { DDRMC_CR97_WRLVL_EN, 97 },
  48         { DDRMC_CR98_WRLVL_DL_0(0), 98 },
  49         { DDRMC_CR99_WRLVL_DL_1(0), 99 },
  50         { DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 },
  51         { DDRMC_CR105_RDLVL_DL_0(0), 105 },
  52         { DDRMC_CR106_RDLVL_GTDL_0(4), 106 },
  53         { DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 },
  54         /* AXI */
  55         { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
  56         { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
  57         { DDRMC_CR120_AXI0_PRI1_RPRI(2) |
  58                    DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
  59         { DDRMC_CR121_AXI0_PRI3_RPRI(2) |
  60                    DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
  61         { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
  62                    DDRMC_CR122_AXI0_PRIRLX(100), 122 },
  63         { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
  64                    DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
  65         { DDRMC_CR124_AXI1_PRIRLX(100), 124 },
  66         { DDRMC_CR126_PHY_RDLAT(8), 126 },
  67         { DDRMC_CR132_WRLAT_ADJ(5) |
  68                    DDRMC_CR132_RDLAT_ADJ(6), 132 },
  69         { DDRMC_CR137_PHYCTL_DL(2), 137 },
  70         { DDRMC_CR138_PHY_WRLV_MXDL(256) |
  71                    DDRMC_CR138_PHYDRAM_CK_EN(1), 138 },
  72         { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
  73                    DDRMC_CR139_PHY_WRLV_DLL(3) |
  74                    DDRMC_CR139_PHY_WRLV_EN(3), 139 },
  75         { DDRMC_CR140_PHY_WRLV_WW(64), 140 },
  76         { DDRMC_CR143_RDLV_GAT_MXDL(1536) |
  77                    DDRMC_CR143_RDLV_MXDL(128), 143 },
  78         { DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
  79                    DDRMC_CR144_PHY_RDLV_DLL(3) |
  80                    DDRMC_CR144_PHY_RDLV_EN(3), 144 },
  81         { DDRMC_CR145_PHY_RDLV_RR(64), 145 },
  82         { DDRMC_CR146_PHY_RDLVL_RESP(64), 146 },
  83         { DDRMC_CR147_RDLV_RESP_MASK(983040), 147 },
  84         { DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 },
  85         { DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
  86                    DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 },
  87
  88         { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
  89                    DDRMC_CR154_PAD_ZQ_MODE(1) |
  90                    DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
  91                    DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
  92         { DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 },
  93         { DDRMC_CR158_TWR(6), 158 },
  94         { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
  95                    DDRMC_CR161_TODTH_WR(2), 161 },
  96         /* end marker */
  97         { 0, -1 }
  98 };
  99
 100 static const iomux_v3_cfg_t usb_pads[] = {
 101         VF610_PAD_PTD4__GPIO_83,
 102         VF610_PAD_PTC29__GPIO_102,
 103 };
 104
 105 int dram_init(void)
 106 {
 107         static const struct ddr3_jedec_timings timings = {
 108                 .tinit             = 5,
 109                 .trst_pwron        = 80000,
 110                 .cke_inactive      = 200000,
 111                 .wrlat             = 5,
 112                 .caslat_lin        = 12,
 113                 .trc               = 21,
 114                 .trrd              = 4,
 115                 .tccd              = 4,
 116                 .tbst_int_interval = 0,
 117                 .tfaw              = 20,
 118                 .trp               = 6,
 119                 .twtr              = 4,
 120                 .tras_min          = 15,
 121                 .tmrd              = 4,
 122                 .trtp              = 4,
 123                 .tras_max          = 28080,
 124                 .tmod              = 12,
 125                 .tckesr            = 4,
 126                 .tcke              = 3,
 127                 .trcd_int          = 6,
 128                 .tras_lockout      = 0,
 129                 .tdal              = 12,
 130                 .bstlen            = 3,
 131                 .tdll              = 512,
 132                 .trp_ab            = 6,
 133                 .tref              = 3120,
 134                 .trfc              = 64,
 135                 .tref_int          = 0,
 136                 .tpdex             = 3,
 137                 .txpdll            = 10,
 138                 .txsnr             = 48,
 139                 .txsr              = 468,
 140                 .cksrx             = 5,
 141                 .cksre             = 5,
 142                 .freq_chg_en       = 0,
 143                 .zqcl              = 256,
 144                 .zqinit            = 512,
 145                 .zqcs              = 64,
 146                 .ref_per_zq        = 64,
 147                 .zqcs_rotate       = 0,
 148                 .aprebit           = 10,
 149                 .cmd_age_cnt       = 64,
 150                 .age_cnt           = 64,
 151                 .q_fullness        = 7,
 152                 .odt_rd_mapcs0     = 0,
 153                 .odt_wr_mapcs0     = 1,
 154                 .wlmrd             = 40,
 155                 .wldqsen           = 25,
 156         };
 157
 158         ddrmc_setup_iomux(NULL, 0);
 159
 160         ddrmc_ctrl_init_ddr3(&timings, colibri_vf_cr_settings, NULL, 1, 2);
 161         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 162
 163         return 0;
 164 }
 165
 166 static void setup_iomux_uart(void)
 167 {
 168         static const iomux_v3_cfg_t uart_pads[] = {
 169                 NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),
 170                 NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),
 171                 NEW_PAD_CTRL(VF610_PAD_PTB10__UART0_TX, UART_PAD_CTRL),
 172                 NEW_PAD_CTRL(VF610_PAD_PTB11__UART0_RX, UART_PAD_CTRL),
 173         };
 174
 175         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 176 }
 177
 178 static void setup_iomux_enet(void)
 179 {
 180         static const iomux_v3_cfg_t enet0_pads[] = {
 181                 NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKOUT, ENET_PAD_CTRL),
 182                 NEW_PAD_CTRL(VF610_PAD_PTC10__RMII1_MDIO, ENET_PAD_CTRL),
 183                 NEW_PAD_CTRL(VF610_PAD_PTC9__RMII1_MDC, ENET_PAD_CTRL),
 184                 NEW_PAD_CTRL(VF610_PAD_PTC11__RMII1_CRS_DV, ENET_PAD_CTRL),
 185                 NEW_PAD_CTRL(VF610_PAD_PTC12__RMII1_RD1, ENET_PAD_CTRL),
 186                 NEW_PAD_CTRL(VF610_PAD_PTC13__RMII1_RD0, ENET_PAD_CTRL),
 187                 NEW_PAD_CTRL(VF610_PAD_PTC14__RMII1_RXER, ENET_PAD_CTRL),
 188                 NEW_PAD_CTRL(VF610_PAD_PTC15__RMII1_TD1, ENET_PAD_CTRL),
 189                 NEW_PAD_CTRL(VF610_PAD_PTC16__RMII1_TD0, ENET_PAD_CTRL),
 190                 NEW_PAD_CTRL(VF610_PAD_PTC17__RMII1_TXEN, ENET_PAD_CTRL),
 191         };
 192
 193         imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
 194 }
 195
 196 static void setup_iomux_i2c(void)
 197 {
 198         static const iomux_v3_cfg_t i2c0_pads[] = {
 199                 VF610_PAD_PTB14__I2C0_SCL,
 200                 VF610_PAD_PTB15__I2C0_SDA,
 201         };
 202
 203         imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
 204 }
 205
 206 #ifdef CONFIG_NAND_VF610_NFC
 207 static void setup_iomux_nfc(void)
 208 {
 209         static const iomux_v3_cfg_t nfc_pads[] = {
 210                 VF610_PAD_PTD23__NF_IO7,
 211                 VF610_PAD_PTD22__NF_IO6,
 212                 VF610_PAD_PTD21__NF_IO5,
 213                 VF610_PAD_PTD20__NF_IO4,
 214                 VF610_PAD_PTD19__NF_IO3,
 215                 VF610_PAD_PTD18__NF_IO2,
 216                 VF610_PAD_PTD17__NF_IO1,
 217                 VF610_PAD_PTD16__NF_IO0,
 218                 VF610_PAD_PTB24__NF_WE_B,
 219                 VF610_PAD_PTB25__NF_CE0_B,
 220                 VF610_PAD_PTB27__NF_RE_B,
 221                 VF610_PAD_PTC26__NF_RB_B,
 222                 VF610_PAD_PTC27__NF_ALE,
 223                 VF610_PAD_PTC28__NF_CLE
 224         };
 225
 226         imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
 227 }
 228 #endif
 229
 230 #ifdef CONFIG_FSL_DSPI
 231 static void setup_iomux_dspi(void)
 232 {
 233         static const iomux_v3_cfg_t dspi1_pads[] = {
 234                 VF610_PAD_PTD5__DSPI1_CS0,
 235                 VF610_PAD_PTD6__DSPI1_SIN,
 236                 VF610_PAD_PTD7__DSPI1_SOUT,
 237                 VF610_PAD_PTD8__DSPI1_SCK,
 238         };
 239
 240         imx_iomux_v3_setup_multiple_pads(dspi1_pads, ARRAY_SIZE(dspi1_pads));
 241 }
 242 #endif
 243
 244 #ifdef CONFIG_VYBRID_GPIO
 245 static void setup_iomux_gpio(void)
 246 {
 247         static const iomux_v3_cfg_t gpio_pads[] = {
 248                 VF610_PAD_PTA17__GPIO_7,
 249                 VF610_PAD_PTA20__GPIO_10,
 250                 VF610_PAD_PTA21__GPIO_11,
 251                 VF610_PAD_PTA30__GPIO_20,
 252                 VF610_PAD_PTA31__GPIO_21,
 253                 VF610_PAD_PTB0__GPIO_22,
 254                 VF610_PAD_PTB1__GPIO_23,
 255                 VF610_PAD_PTB6__GPIO_28,
 256                 VF610_PAD_PTB7__GPIO_29,
 257                 VF610_PAD_PTB8__GPIO_30,
 258                 VF610_PAD_PTB9__GPIO_31,
 259                 VF610_PAD_PTB12__GPIO_34,
 260                 VF610_PAD_PTB13__GPIO_35,
 261                 VF610_PAD_PTB16__GPIO_38,
 262                 VF610_PAD_PTB17__GPIO_39,
 263                 VF610_PAD_PTB18__GPIO_40,
 264                 VF610_PAD_PTB21__GPIO_43,
 265                 VF610_PAD_PTB22__GPIO_44,
 266                 VF610_PAD_PTC0__GPIO_45,
 267                 VF610_PAD_PTC1__GPIO_46,
 268                 VF610_PAD_PTC2__GPIO_47,
 269                 VF610_PAD_PTC3__GPIO_48,
 270                 VF610_PAD_PTC4__GPIO_49,
 271                 VF610_PAD_PTC5__GPIO_50,
 272                 VF610_PAD_PTC6__GPIO_51,
 273                 VF610_PAD_PTC7__GPIO_52,
 274                 VF610_PAD_PTC8__GPIO_53,
 275                 VF610_PAD_PTD31__GPIO_63,
 276                 VF610_PAD_PTD30__GPIO_64,
 277                 VF610_PAD_PTD29__GPIO_65,
 278                 VF610_PAD_PTD28__GPIO_66,
 279                 VF610_PAD_PTD27__GPIO_67,
 280                 VF610_PAD_PTD26__GPIO_68,
 281                 VF610_PAD_PTD25__GPIO_69,
 282                 VF610_PAD_PTD24__GPIO_70,
 283                 VF610_PAD_PTD9__GPIO_88,
 284                 VF610_PAD_PTD10__GPIO_89,
 285                 VF610_PAD_PTD11__GPIO_90,
 286                 VF610_PAD_PTD12__GPIO_91,
 287                 VF610_PAD_PTD13__GPIO_92,
 288                 VF610_PAD_PTB23__GPIO_93,
 289                 VF610_PAD_PTB26__GPIO_96,
 290                 VF610_PAD_PTB28__GPIO_98,
 291                 VF610_PAD_PTC30__GPIO_103,
 292                 VF610_PAD_PTA7__GPIO_134,
 293         };
 294
 295         imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
 296 }
 297 #endif
 298
 299 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 300 static void setup_iomux_fsl_dcu(void)
 301 {
 302         static const iomux_v3_cfg_t dcu0_pads[] = {
 303                 VF610_PAD_PTE0__DCU0_HSYNC,
 304                 VF610_PAD_PTE1__DCU0_VSYNC,
 305                 VF610_PAD_PTE2__DCU0_PCLK,
 306                 VF610_PAD_PTE4__DCU0_DE,
 307                 VF610_PAD_PTE5__DCU0_R0,
 308                 VF610_PAD_PTE6__DCU0_R1,
 309                 VF610_PAD_PTE7__DCU0_R2,
 310                 VF610_PAD_PTE8__DCU0_R3,
 311                 VF610_PAD_PTE9__DCU0_R4,
 312                 VF610_PAD_PTE10__DCU0_R5,
 313                 VF610_PAD_PTE11__DCU0_R6,
 314                 VF610_PAD_PTE12__DCU0_R7,
 315                 VF610_PAD_PTE13__DCU0_G0,
 316                 VF610_PAD_PTE14__DCU0_G1,
 317                 VF610_PAD_PTE15__DCU0_G2,
 318                 VF610_PAD_PTE16__DCU0_G3,
 319                 VF610_PAD_PTE17__DCU0_G4,
 320                 VF610_PAD_PTE18__DCU0_G5,
 321                 VF610_PAD_PTE19__DCU0_G6,
 322                 VF610_PAD_PTE20__DCU0_G7,
 323                 VF610_PAD_PTE21__DCU0_B0,
 324                 VF610_PAD_PTE22__DCU0_B1,
 325                 VF610_PAD_PTE23__DCU0_B2,
 326                 VF610_PAD_PTE24__DCU0_B3,
 327                 VF610_PAD_PTE25__DCU0_B4,
 328                 VF610_PAD_PTE26__DCU0_B5,
 329                 VF610_PAD_PTE27__DCU0_B6,
 330                 VF610_PAD_PTE28__DCU0_B7,
 331         };
 332
 333         imx_iomux_v3_setup_multiple_pads(dcu0_pads, ARRAY_SIZE(dcu0_pads));
 334 }
 335
 336 static void setup_tcon(void)
 337 {
 338         setbits_le32(TCON0_BASE_ADDR, (1 << 29));
 339 }
 340 #endif
 341
 342 #ifdef CONFIG_FSL_ESDHC
 343 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 344         {ESDHC1_BASE_ADDR},
 345 };
 346
 347 int board_mmc_getcd(struct mmc *mmc)
 348 {
 349         /* eSDHC1 is always present */
 350         return 1;
 351 }
 352
 353 int board_mmc_init(bd_t *bis)
 354 {
 355         static const iomux_v3_cfg_t esdhc1_pads[] = {
 356                 NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
 357                 NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
 358                 NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
 359                 NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
 360                 NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
 361                 NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
 362         };
 363
 364         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 365
 366         imx_iomux_v3_setup_multiple_pads(
 367                 esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
 368
 369         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 370 }
 371 #endif
 372
 373 static inline int is_colibri_vf61(void)
 374 {
 375         struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
 376
 377         /*
 378          * Detect board type by Level 2 Cache: VF50 don't have any
 379          * Level 2 Cache.
 380          */
 381         return !!mscm->cpxcfg1;
 382 }
 383
 384 static void clock_init(void)
 385 {
 386         struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
 387         struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
 388         u32 pfd_clk_sel, ddr_clk_sel;
 389
 390         clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
 391                         CCM_CCGR0_UART0_CTRL_MASK);
 392 #ifdef CONFIG_FSL_DSPI
 393         setbits_le32(&ccm->ccgr0, CCM_CCGR0_DSPI1_CTRL_MASK);
 394 #endif
 395         clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
 396                         CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
 397         clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
 398                         CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
 399                         CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
 400                         CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK);
 401         clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
 402                         CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
 403         clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
 404                         CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
 405                         CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
 406         clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
 407                         CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
 408         clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
 409                         CCM_CCGR7_SDHC1_CTRL_MASK);
 410         clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
 411                         CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
 412         clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
 413                         CCM_CCGR10_NFC_CTRL_MASK);
 414
 415 #ifdef CONFIG_USB_EHCI_VF
 416         setbits_le32(&ccm->ccgr1, CCM_CCGR1_USBC0_CTRL_MASK);
 417         setbits_le32(&ccm->ccgr7, CCM_CCGR7_USBC1_CTRL_MASK);
 418
 419         clrsetbits_le32(&anadig->pll3_ctrl, ANADIG_PLL3_CTRL_BYPASS |
 420                         ANADIG_PLL3_CTRL_POWERDOWN |
 421                         ANADIG_PLL3_CTRL_DIV_SELECT,
 422                         ANADIG_PLL3_CTRL_ENABLE);
 423         clrsetbits_le32(&anadig->pll7_ctrl, ANADIG_PLL7_CTRL_BYPASS |
 424                         ANADIG_PLL7_CTRL_POWERDOWN |
 425                         ANADIG_PLL7_CTRL_DIV_SELECT,
 426                         ANADIG_PLL7_CTRL_ENABLE);
 427 #endif
 428
 429         clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS |
 430                         ANADIG_PLL5_CTRL_POWERDOWN, ANADIG_PLL5_CTRL_ENABLE |
 431                         ANADIG_PLL5_CTRL_DIV_SELECT);
 432
 433         if (is_colibri_vf61()) {
 434                 clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL5_CTRL_BYPASS |
 435                                 ANADIG_PLL2_CTRL_POWERDOWN,
 436                                 ANADIG_PLL2_CTRL_ENABLE |
 437                                 ANADIG_PLL2_CTRL_DIV_SELECT);
 438         }
 439
 440         clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
 441                         ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
 442
 443         clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
 444                         CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
 445
 446         /* See "Typical PLL Configuration" */
 447         if (is_colibri_vf61()) {
 448                 pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(1);
 449                 ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(0);
 450         } else {
 451                 pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(3);
 452                 ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(1);
 453         }
 454
 455         clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, pfd_clk_sel |
 456                         CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN |
 457                         CCM_CCSR_PLL2_PFD2_EN | CCM_CCSR_PLL2_PFD1_EN |
 458                         CCM_CCSR_PLL1_PFD4_EN | CCM_CCSR_PLL1_PFD3_EN |
 459                         CCM_CCSR_PLL1_PFD2_EN | CCM_CCSR_PLL1_PFD1_EN |
 460                         ddr_clk_sel | CCM_CCSR_FAST_CLK_SEL(1) |
 461                         CCM_CCSR_SYS_CLK_SEL(4));
 462
 463         clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
 464                         CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
 465                         CCM_CACRR_ARM_CLK_DIV(0));
 466         clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
 467                         CCM_CSCMR1_ESDHC1_CLK_SEL(3) |
 468                         CCM_CSCMR1_NFC_CLK_SEL(0));
 469         clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
 470                         CCM_CSCDR1_RMII_CLK_EN);
 471         clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
 472                         CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
 473                         CCM_CSCDR2_NFC_EN);
 474         clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
 475                         CCM_CSCDR3_NFC_PRE_DIV(3));
 476         clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
 477                         CCM_CSCMR2_RMII_CLK_SEL(2));
 478
 479 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 480                 setbits_le32(&ccm->ccgr1, CCM_CCGR1_TCON0_CTRL_MASK);
 481                 setbits_le32(&ccm->ccgr3, CCM_CCGR3_DCU0_CTRL_MASK);
 482 #endif
 483 }
 484
 485 static void mscm_init(void)
 486 {
 487         struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
 488         int i;
 489
 490         for (i = 0; i < MSCM_IRSPRC_NUM; i++)
 491                 writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
 492 }
 493
 494 int board_phy_config(struct phy_device *phydev)
 495 {
 496         if (phydev->drv->config)
 497                 phydev->drv->config(phydev);
 498
 499         return 0;
 500 }
 501
 502 int board_early_init_f(void)
 503 {
 504         clock_init();
 505         mscm_init();
 506
 507         setup_iomux_uart();
 508         setup_iomux_enet();
 509         setup_iomux_i2c();
 510 #ifdef CONFIG_NAND_VF610_NFC
 511         setup_iomux_nfc();
 512 #endif
 513
 514 #ifdef CONFIG_VYBRID_GPIO
 515         setup_iomux_gpio();
 516 #endif
 517
 518 #ifdef CONFIG_FSL_DSPI
 519         setup_iomux_dspi();
 520 #endif
 521
 522 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 523         setup_tcon();
 524         setup_iomux_fsl_dcu();
 525 #endif
 526
 527         return 0;
 528 }
 529
 530 #ifdef CONFIG_BOARD_LATE_INIT
 531 int board_late_init(void)
 532 {
 533         struct src *src = (struct src *)SRC_BASE_ADDR;
 534
 535         if (((src->sbmr2 & SRC_SBMR2_BMOD_MASK) >> SRC_SBMR2_BMOD_SHIFT)
 536                         == SRC_SBMR2_BMOD_SERIAL) {
 537                 printf("Serial Downloader recovery mode, disable autoboot\n");
 538                 env_set("bootdelay", "-1");
 539         }
 540
 541         return 0;
 542 }
 543 #endif /* CONFIG_BOARD_LATE_INIT */
 544
 545 int board_init(void)
 546 {
 547         struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
 548
 549         /* address of boot parameters */
 550         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 551
 552         /*
 553          * Enable external 32K Oscillator
 554          *
 555          * The internal clock experiences significant drift
 556          * so we must use the external oscillator in order
 557          * to maintain correct time in the hwclock
 558          */
 559
 560         setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
 561
 562 #ifdef CONFIG_USB_EHCI_VF
 563         gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
 564 #endif
 565
 566         return 0;
 567 }
 568
 569 int checkboard(void)
 570 {
 571         if (is_colibri_vf61())
 572                 puts("Board: Colibri VF61\n");
 573         else
 574                 puts("Board: Colibri VF50\n");
 575
 576         return 0;
 577 }
 578
 579 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 580 int ft_board_setup(void *blob, bd_t *bd)
 581 {
 582         int ret = 0;
 583 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
 584         static struct node_info nodes[] = {
 585                 { "fsl,vf610-nfc", MTD_DEV_TYPE_NAND, }, /* NAND flash */
 586         };
 587
 588         /* Update partition nodes using info from mtdparts env var */
 589         puts("   Updating MTD partitions...\n");
 590         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
 591 #endif
 592 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 593         ret = fsl_dcu_fixedfb_setup(blob);
 594         if (ret)
 595                 return ret;
 596 #endif
 597
 598         return ft_common_board_setup(blob, bd);
 599 }
 600 #endif
 601
 602 #ifdef CONFIG_USB_EHCI_VF
 603 int board_ehci_hcd_init(int port)
 604 {
 605         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 606
 607         switch (port) {
 608         case 0:
 609                 /* USBC does not have PEN, also configured as USB client only */
 610                 break;
 611         case 1:
 612                 gpio_request(USB_PEN_GPIO, "usb-pen-gpio");
 613                 gpio_direction_output(USB_PEN_GPIO, 0);
 614                 break;
 615         }
 616         return 0;
 617 }
 618
 619 int board_usb_phy_mode(int port)
 620 {
 621         switch (port) {
 622         case 0:
 623                 /*
 624                  * Port 0 is used only in client mode on Colibri Vybrid modules
 625                  * Check for state of USB client gpio pin and accordingly return
 626                  * USB_INIT_DEVICE or USB_INIT_HOST.
 627                  */
 628                 if (gpio_get_value(USB_CDET_GPIO))
 629                         return USB_INIT_DEVICE;
 630                 else
 631                         return USB_INIT_HOST;
 632         case 1:
 633                 /* Port 1 is used only in host mode on Colibri Vybrid modules */
 634                 return USB_INIT_HOST;
 635         default:
 636                 /*
 637                  * There are only two USB controllers on Vybrid. Ideally we will
 638                  * not reach here. However return USB_INIT_HOST if we do.
 639                  */
 640                 return USB_INIT_HOST;
 641         }
 642 }
 643 #endif