1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015-2019 Toradex, Inc.
6 * Copyright 2013 Freescale Semiconductor, Inc.
11 #include <asm/arch/clock.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/ddrmc-vf610.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/iomux-vf610.h>
19 #include <fdt_support.h>
20 #include <fsl_dcu_fb.h>
22 #include <jffs2/load_kernel.h>
26 #include "../common/tdx-common.h"
28 DECLARE_GLOBAL_DATA_PTR;
30 #define PTC0_GPIO_45 45
32 static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
33 { DDRMC_CR79_CTLUPD_AREF(1), 79 },
34 /* sets manual values for read lvl. (gate) delay of data slice 0/1 */
35 { DDRMC_CR105_RDLVL_DL_0(28), 105 },
36 { DDRMC_CR106_RDLVL_GTDL_0(24), 106 },
37 { DDRMC_CR110_RDLVL_DL_1(28) | DDRMC_CR110_RDLVL_GTDL_1(24), 110 },
38 { DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN, 102 },
41 { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
42 { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
43 { DDRMC_CR120_AXI0_PRI1_RPRI(2) |
44 DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
45 { DDRMC_CR121_AXI0_PRI3_RPRI(2) |
46 DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
47 { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
48 DDRMC_CR122_AXI0_PRIRLX(100), 122 },
49 { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
50 DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
51 { DDRMC_CR124_AXI1_PRIRLX(100), 124 },
52 { DDRMC_CR126_PHY_RDLAT(8), 126 },
53 { DDRMC_CR132_WRLAT_ADJ(5) |
54 DDRMC_CR132_RDLAT_ADJ(6), 132 },
55 { DDRMC_CR137_PHYCTL_DL(2), 137 },
56 { DDRMC_CR138_PHY_WRLV_MXDL(256) |
57 DDRMC_CR138_PHYDRAM_CK_EN(1), 138 },
58 { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
59 DDRMC_CR139_PHY_WRLV_DLL(3) |
60 DDRMC_CR139_PHY_WRLV_EN(3), 139 },
61 { DDRMC_CR140_PHY_WRLV_WW(64), 140 },
62 { DDRMC_CR143_RDLV_GAT_MXDL(1536) |
63 DDRMC_CR143_RDLV_MXDL(128), 143 },
64 { DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
65 DDRMC_CR144_PHY_RDLV_DLL(3) |
66 DDRMC_CR144_PHY_RDLV_EN(3), 144 },
67 { DDRMC_CR145_PHY_RDLV_RR(64), 145 },
68 { DDRMC_CR146_PHY_RDLVL_RESP(64), 146 },
69 { DDRMC_CR147_RDLV_RESP_MASK(983040), 147 },
70 { DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 },
71 { DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
72 DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 },
74 { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
75 DDRMC_CR154_PAD_ZQ_MODE(1) |
76 DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
77 DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
78 { DDRMC_CR155_PAD_ODT_BYTE1(2) | DDRMC_CR155_PAD_ODT_BYTE0(2), 155 },
79 { DDRMC_CR158_TWR(6), 158 },
80 { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
81 DDRMC_CR161_TODTH_WR(2), 161 },
88 static const struct ddr3_jedec_timings timings = {
91 .cke_inactive = 200000,
97 .tbst_int_interval = 0,
112 .tdll = 512, /* not applicable since freq. scaling
121 .txsnr = 68, /* changed to conform to JEDEC
124 .txsr = 506, /* changed to conform to JEDEC
145 ddrmc_ctrl_init_ddr3(&timings, colibri_vf_cr_settings, NULL, 1, 2);
146 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
151 #ifdef CONFIG_VYBRID_GPIO
152 static void setup_iomux_gpio(void)
154 static const iomux_v3_cfg_t gpio_pads[] = {
155 VF610_PAD_PTA17__GPIO_7,
156 VF610_PAD_PTA20__GPIO_10,
157 VF610_PAD_PTA21__GPIO_11,
158 VF610_PAD_PTA30__GPIO_20,
159 VF610_PAD_PTA31__GPIO_21,
160 VF610_PAD_PTB0__GPIO_22,
161 VF610_PAD_PTB1__GPIO_23,
162 VF610_PAD_PTB6__GPIO_28,
163 VF610_PAD_PTB7__GPIO_29,
164 VF610_PAD_PTB8__GPIO_30,
165 VF610_PAD_PTB9__GPIO_31,
166 VF610_PAD_PTB12__GPIO_34,
167 VF610_PAD_PTB13__GPIO_35,
168 VF610_PAD_PTB16__GPIO_38,
169 VF610_PAD_PTB17__GPIO_39,
170 VF610_PAD_PTB18__GPIO_40,
171 VF610_PAD_PTB21__GPIO_43,
172 VF610_PAD_PTB22__GPIO_44,
173 VF610_PAD_PTC0__GPIO_45,
174 VF610_PAD_PTC1__GPIO_46,
175 VF610_PAD_PTC2__GPIO_47,
176 VF610_PAD_PTC3__GPIO_48,
177 VF610_PAD_PTC4__GPIO_49,
178 VF610_PAD_PTC5__GPIO_50,
179 VF610_PAD_PTC6__GPIO_51,
180 VF610_PAD_PTC7__GPIO_52,
181 VF610_PAD_PTC8__GPIO_53,
182 VF610_PAD_PTD31__GPIO_63,
183 VF610_PAD_PTD30__GPIO_64,
184 VF610_PAD_PTD29__GPIO_65,
185 VF610_PAD_PTD28__GPIO_66,
186 VF610_PAD_PTD27__GPIO_67,
187 VF610_PAD_PTD26__GPIO_68,
188 VF610_PAD_PTD25__GPIO_69,
189 VF610_PAD_PTD24__GPIO_70,
190 VF610_PAD_PTD9__GPIO_88,
191 VF610_PAD_PTD10__GPIO_89,
192 VF610_PAD_PTD11__GPIO_90,
193 VF610_PAD_PTD12__GPIO_91,
194 VF610_PAD_PTD13__GPIO_92,
195 VF610_PAD_PTB23__GPIO_93,
196 VF610_PAD_PTB26__GPIO_96,
197 VF610_PAD_PTB28__GPIO_98,
198 VF610_PAD_PTC30__GPIO_103,
199 VF610_PAD_PTA7__GPIO_134,
202 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
206 #ifdef CONFIG_VIDEO_FSL_DCU_FB
207 static void setup_iomux_fsl_dcu(void)
209 static const iomux_v3_cfg_t dcu0_pads[] = {
210 VF610_PAD_PTE0__DCU0_HSYNC,
211 VF610_PAD_PTE1__DCU0_VSYNC,
212 VF610_PAD_PTE2__DCU0_PCLK,
213 VF610_PAD_PTE4__DCU0_DE,
214 VF610_PAD_PTE5__DCU0_R0,
215 VF610_PAD_PTE6__DCU0_R1,
216 VF610_PAD_PTE7__DCU0_R2,
217 VF610_PAD_PTE8__DCU0_R3,
218 VF610_PAD_PTE9__DCU0_R4,
219 VF610_PAD_PTE10__DCU0_R5,
220 VF610_PAD_PTE11__DCU0_R6,
221 VF610_PAD_PTE12__DCU0_R7,
222 VF610_PAD_PTE13__DCU0_G0,
223 VF610_PAD_PTE14__DCU0_G1,
224 VF610_PAD_PTE15__DCU0_G2,
225 VF610_PAD_PTE16__DCU0_G3,
226 VF610_PAD_PTE17__DCU0_G4,
227 VF610_PAD_PTE18__DCU0_G5,
228 VF610_PAD_PTE19__DCU0_G6,
229 VF610_PAD_PTE20__DCU0_G7,
230 VF610_PAD_PTE21__DCU0_B0,
231 VF610_PAD_PTE22__DCU0_B1,
232 VF610_PAD_PTE23__DCU0_B2,
233 VF610_PAD_PTE24__DCU0_B3,
234 VF610_PAD_PTE25__DCU0_B4,
235 VF610_PAD_PTE26__DCU0_B5,
236 VF610_PAD_PTE27__DCU0_B6,
237 VF610_PAD_PTE28__DCU0_B7,
240 imx_iomux_v3_setup_multiple_pads(dcu0_pads, ARRAY_SIZE(dcu0_pads));
243 static void setup_tcon(void)
245 setbits_le32(TCON0_BASE_ADDR, (1 << 29));
249 static inline int is_colibri_vf61(void)
251 struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
254 * Detect board type by Level 2 Cache: VF50 don't have any
257 return !!mscm->cpxcfg1;
260 static void clock_init(void)
262 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
263 struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
264 u32 pfd_clk_sel, ddr_clk_sel;
266 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
267 CCM_CCGR0_UART0_CTRL_MASK);
268 #ifdef CONFIG_FSL_DSPI
269 setbits_le32(&ccm->ccgr0, CCM_CCGR0_DSPI1_CTRL_MASK);
271 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
272 CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
273 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
274 CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
275 CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
276 CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK);
277 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
278 CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
279 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
280 CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
281 CCM_CCGR4_GPC_CTRL_MASK);
282 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
283 CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
284 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
285 CCM_CCGR7_SDHC1_CTRL_MASK);
286 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
287 CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
288 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
289 CCM_CCGR10_NFC_CTRL_MASK);
291 #ifdef CONFIG_USB_EHCI_VF
292 setbits_le32(&ccm->ccgr1, CCM_CCGR1_USBC0_CTRL_MASK);
293 setbits_le32(&ccm->ccgr7, CCM_CCGR7_USBC1_CTRL_MASK);
295 clrsetbits_le32(&anadig->pll3_ctrl, ANADIG_PLL3_CTRL_BYPASS |
296 ANADIG_PLL3_CTRL_POWERDOWN |
297 ANADIG_PLL3_CTRL_DIV_SELECT,
298 ANADIG_PLL3_CTRL_ENABLE);
299 clrsetbits_le32(&anadig->pll7_ctrl, ANADIG_PLL7_CTRL_BYPASS |
300 ANADIG_PLL7_CTRL_POWERDOWN |
301 ANADIG_PLL7_CTRL_DIV_SELECT,
302 ANADIG_PLL7_CTRL_ENABLE);
305 clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS |
306 ANADIG_PLL5_CTRL_POWERDOWN, ANADIG_PLL5_CTRL_ENABLE |
307 ANADIG_PLL5_CTRL_DIV_SELECT);
309 if (is_colibri_vf61()) {
310 clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL5_CTRL_BYPASS |
311 ANADIG_PLL2_CTRL_POWERDOWN,
312 ANADIG_PLL2_CTRL_ENABLE |
313 ANADIG_PLL2_CTRL_DIV_SELECT);
316 clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
317 ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
319 clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
320 CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
322 /* See "Typical PLL Configuration" */
323 if (is_colibri_vf61()) {
324 pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(1);
325 ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(0);
327 pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(3);
328 ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(1);
331 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, pfd_clk_sel |
332 CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN |
333 CCM_CCSR_PLL2_PFD2_EN | CCM_CCSR_PLL2_PFD1_EN |
334 CCM_CCSR_PLL1_PFD4_EN | CCM_CCSR_PLL1_PFD3_EN |
335 CCM_CCSR_PLL1_PFD2_EN | CCM_CCSR_PLL1_PFD1_EN |
336 ddr_clk_sel | CCM_CCSR_FAST_CLK_SEL(1) |
337 CCM_CCSR_SYS_CLK_SEL(4));
339 clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
340 CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
341 CCM_CACRR_ARM_CLK_DIV(0));
342 clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
343 CCM_CSCMR1_ESDHC1_CLK_SEL(3) |
344 CCM_CSCMR1_NFC_CLK_SEL(0));
345 clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
346 CCM_CSCDR1_RMII_CLK_EN);
347 clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
348 CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
350 clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
351 CCM_CSCDR3_NFC_PRE_DIV(3));
352 clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
353 CCM_CSCMR2_RMII_CLK_SEL(2));
355 #ifdef CONFIG_VIDEO_FSL_DCU_FB
356 setbits_le32(&ccm->ccgr1, CCM_CCGR1_TCON0_CTRL_MASK);
357 setbits_le32(&ccm->ccgr3, CCM_CCGR3_DCU0_CTRL_MASK);
361 static void mscm_init(void)
363 struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
366 for (i = 0; i < MSCM_IRSPRC_NUM; i++)
367 writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
370 int board_early_init_f(void)
375 #ifdef CONFIG_VYBRID_GPIO
379 #ifdef CONFIG_VIDEO_FSL_DCU_FB
381 setup_iomux_fsl_dcu();
387 #ifdef CONFIG_BOARD_LATE_INIT
388 int board_late_init(void)
390 struct src *src = (struct src *)SRC_BASE_ADDR;
392 if (((src->sbmr2 & SRC_SBMR2_BMOD_MASK) >> SRC_SBMR2_BMOD_SHIFT)
393 == SRC_SBMR2_BMOD_SERIAL) {
394 printf("Serial Downloader recovery mode, disable autoboot\n");
395 env_set("bootdelay", "-1");
400 #endif /* CONFIG_BOARD_LATE_INIT */
404 struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
406 /* address of boot parameters */
407 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
410 * Enable external 32K Oscillator
412 * The internal clock experiences significant drift
413 * so we must use the external oscillator in order
414 * to maintain correct time in the hwclock
416 setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
423 if (is_colibri_vf61())
424 puts("Model: Toradex Colibri VF61\n");
426 puts("Model: Toradex Colibri VF50\n");
431 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
432 int ft_board_setup(void *blob, bd_t *bd)
434 #ifndef CONFIG_DM_VIDEO
437 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
438 static const struct node_info nodes[] = {
439 { "fsl,vf610-nfc", MTD_DEV_TYPE_NAND, }, /* NAND flash */
442 /* Update partition nodes using info from mtdparts env var */
443 puts(" Updating MTD partitions...\n");
444 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
446 #if defined(CONFIG_VIDEO_FSL_DCU_FB) && !defined(CONFIG_DM_VIDEO)
447 ret = fsl_dcu_fixedfb_setup(blob);
452 return ft_common_board_setup(blob, bd);
457 * Backlight off before OS handover
459 void board_preboot_os(void)
461 gpio_request(PTC0_GPIO_45, "BL_ON");
462 gpio_direction_output(PTC0_GPIO_45, 0);