1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012 Lucas Stach
9 #include <asm/arch/clock.h>
10 #include <asm/arch/funcmux.h>
11 #include <asm/arch/pinmux.h>
12 #include <asm/arch-tegra/ap.h>
13 #include <asm/arch-tegra/board.h>
14 #include <asm/arch-tegra/tegra.h>
19 #include "../common/tdx-common.h"
21 DECLARE_GLOBAL_DATA_PTR;
23 #define PMU_I2C_ADDRESS 0x34
24 #define MAX_I2C_RETRY 3
25 #define PMU_SUPPLYENE 0x14
26 #define PMU_SUPPLYENE_SYSINEN (1<<5)
27 #define PMU_SUPPLYENE_EXITSLREQ (1<<1)
29 int arch_misc_init(void)
31 /* Disable PMIC sleep mode on low supply voltage */
36 err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev);
38 debug("%s: Cannot find PMIC I2C chip\n", __func__);
44 err = dm_i2c_read(dev, addr, data, 1);
46 debug("failed to get PMU_SUPPLYENE\n");
50 data[0] &= ~PMU_SUPPLYENE_SYSINEN;
51 data[0] |= PMU_SUPPLYENE_EXITSLREQ;
53 err = dm_i2c_write(dev, addr, data, 1);
55 debug("failed to set PMU_SUPPLYENE\n");
59 /* make sure SODIMM pin 87 nRESET_OUT is released properly */
60 pinmux_set_func(PMUX_PINGRP_ATA, PMUX_FUNC_GMI);
62 if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
64 printf("USB recovery mode\n");
71 printf("Model: Toradex Colibri T20 %dMB V%s\n",
72 (gd->ram_size == 0x10000000) ? 256 : 512,
73 (get_nand_dev_by_index(0)->erasesize >> 10 == 512) ?
74 ((gd->ram_size == 0x10000000) ? "1.1B" : "1.1C") : "1.2A");
79 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
80 int ft_board_setup(void *blob, bd_t *bd)
82 return ft_common_board_setup(blob, bd);
86 #ifdef CONFIG_MMC_SDHCI_TEGRA
88 * Routine: pin_mux_mmc
89 * Description: setup the pin muxes/tristate values for the SDMMC(s)
91 void pin_mux_mmc(void)
93 funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
94 pinmux_tristate_disable(PMUX_PINGRP_GMB);
98 #ifdef CONFIG_TEGRA_NAND
99 void pin_mux_nand(void)
101 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT);
104 * configure pingroup ATC to something unrelated to
105 * avoid ATC overriding KBC
107 pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_GMI);
111 #ifdef CONFIG_USB_EHCI_TEGRA
112 void pin_mux_usb(void)
114 /* module internal USB bus to connect ethernet chipset */
115 funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
117 /* ULPI reference clock output */
118 pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
119 pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
122 pinmux_tristate_disable(PMUX_PINGRP_UAC);
125 pinmux_tristate_disable(PMUX_PINGRP_DTE);
127 /* Reset ASIX using LAN_RESET */
128 gpio_request(TEGRA_GPIO(V, 4), "LAN_RESET");
129 gpio_direction_output(TEGRA_GPIO(V, 4), 0);
130 pinmux_tristate_disable(PMUX_PINGRP_GPV);
132 gpio_set_value(TEGRA_GPIO(V, 4), 1);
134 /* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */
135 pinmux_tristate_disable(PMUX_PINGRP_SPIG);
139 #ifdef CONFIG_VIDEO_TEGRA20
141 * Routine: pin_mux_display
142 * Description: setup the pin muxes/tristate values for the LCD interface)
144 void pin_mux_display(void)
147 * Manually untristate BL_ON (PT4 - SODIMM 71) as specified through
150 pinmux_tristate_disable(PMUX_PINGRP_DTA);
152 pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM);
153 pinmux_tristate_disable(PMUX_PINGRP_SDC);
157 * Backlight off before OS handover
159 void board_preboot_os(void)
161 gpio_request(TEGRA_GPIO(T, 4), "BL_ON");
162 gpio_direction_output(TEGRA_GPIO(T, 4), 0);