board/toradex/colibri_imx7/colibri_imx7.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016-2018 Toradex AG
   4  */
   5
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <init.h>
   9 #include <net.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/crm_regs.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/mx7-pins.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <asm/gpio.h>
  16 #include <asm/mach-imx/iomux-v3.h>
  17 #include <asm/io.h>
  18 #include <common.h>
  19 #include <dm.h>
  20 #include <dm/platform_data/serial_mxc.h>
  21 #include <fdt_support.h>
  22 #include <fsl_esdhc_imx.h>
  23 #include <jffs2/load_kernel.h>
  24 #include <linux/sizes.h>
  25 #include <mmc.h>
  26 #include <miiphy.h>
  27 #include <mtd_node.h>
  28 #include <netdev.h>
  29 #include <power/pmic.h>
  30 #include <power/rn5t567_pmic.h>
  31 #include <usb.h>
  32 #include <usb/ehci-ci.h>
  33 #include "../common/tdx-common.h"
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 #define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
  38         PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
  39
  40 #define ENET_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  41 #define ENET_PAD_CTRL_MII  (PAD_CTL_DSE_3P3V_32OHM)
  42
  43 #define ENET_RX_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  44
  45 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
  46         PAD_CTL_DSE_3P3V_49OHM)
  47
  48 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
  49
  50 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
  51
  52 #define USB_CDET_GPIO   IMX_GPIO_NR(7, 14)
  53
  54 int dram_init(void)
  55 {
  56         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, imx_ddr_size());
  57
  58         return 0;
  59 }
  60
  61 static iomux_v3_cfg_t const uart1_pads[] = {
  62         MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  63         MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  64         MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
  65         MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
  66 };
  67
  68 #ifdef CONFIG_USB_EHCI_MX7
  69 static iomux_v3_cfg_t const usb_cdet_pads[] = {
  70         MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
  71 };
  72 #endif
  73
  74 #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
  75 static iomux_v3_cfg_t const gpmi_pads[] = {
  76         MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  77         MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  78         MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  79         MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  80         MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  81         MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  82         MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  83         MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  84         MX7D_PAD_SD3_CLK__NAND_CLE      | MUX_PAD_CTRL(NAND_PAD_CTRL),
  85         MX7D_PAD_SD3_CMD__NAND_ALE      | MUX_PAD_CTRL(NAND_PAD_CTRL),
  86         MX7D_PAD_SD3_STROBE__NAND_RE_B  | MUX_PAD_CTRL(NAND_PAD_CTRL),
  87         MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  88         MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B       | MUX_PAD_CTRL(NAND_PAD_CTRL),
  89         MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B       | MUX_PAD_CTRL(NAND_PAD_CTRL),
  90         MX7D_PAD_SAI1_TX_DATA__NAND_READY_B     | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
  91 };
  92
  93 static void setup_gpmi_nand(void)
  94 {
  95         imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
  96
  97         /* NAND_USDHC_BUS_CLK is set in rom */
  98         set_clk_nand();
  99 }
 100 #endif
 101
 102 #ifdef CONFIG_VIDEO_MXS
 103 static iomux_v3_cfg_t const lcd_pads[] = {
 104         MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
 105         MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
 106         MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
 107         MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
 108         MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 109         MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 110         MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 111         MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 112         MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 113         MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 114         MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 115         MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 116         MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 117         MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 118         MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 119         MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 120         MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 121         MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 122         MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 123         MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 124         MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 125         MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 126 };
 127
 128 static iomux_v3_cfg_t const backlight_pads[] = {
 129         /* Backlight On */
 130         MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
 131         /* Backlight PWM<A> (multiplexed pin) */
 132         MX7D_PAD_GPIO1_IO08__GPIO1_IO8   | MUX_PAD_CTRL(NO_PAD_CTRL),
 133         MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 134 };
 135
 136 #define GPIO_BL_ON IMX_GPIO_NR(5, 1)
 137 #define GPIO_PWM_A IMX_GPIO_NR(1, 8)
 138
 139 static int setup_lcd(void)
 140 {
 141         imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 142
 143         imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
 144
 145         /* Set BL_ON */
 146         gpio_request(GPIO_BL_ON, "BL_ON");
 147         gpio_direction_output(GPIO_BL_ON, 1);
 148
 149         /* Set PWM<A> to full brightness (assuming inversed polarity) */
 150         gpio_request(GPIO_PWM_A, "PWM<A>");
 151         gpio_direction_output(GPIO_PWM_A, 0);
 152
 153         return 0;
 154 }
 155 #endif
 156
 157 /*
 158  * Backlight off before OS handover
 159  */
 160 void board_preboot_os(void)
 161 {
 162         gpio_direction_output(GPIO_PWM_A, 1);
 163         gpio_direction_output(GPIO_BL_ON, 0);
 164 }
 165
 166 static void setup_iomux_uart(void)
 167 {
 168         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 169 }
 170
 171 #ifdef CONFIG_FEC_MXC
 172 static int setup_fec(void)
 173 {
 174         struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
 175                 = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
 176
 177 #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
 178         /*
 179          * Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]
 180          * and output it on the pin
 181          */
 182         clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
 183                         IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK,
 184                         IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK);
 185 #else
 186         /* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */
 187         clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
 188                         IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK,
 189                         IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
 190 #endif
 191
 192         return set_clk_enet(ENET_50MHZ);
 193 }
 194
 195 #endif
 196
 197 int board_early_init_f(void)
 198 {
 199         setup_iomux_uart();
 200
 201         return 0;
 202 }
 203
 204 int board_init(void)
 205 {
 206         /* address of boot parameters */
 207         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 208
 209 #ifdef CONFIG_FEC_MXC
 210         setup_fec();
 211 #endif
 212
 213 #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
 214         setup_gpmi_nand();
 215 #endif
 216
 217 #ifdef CONFIG_VIDEO_MXS
 218         setup_lcd();
 219 #endif
 220
 221 #ifdef CONFIG_USB_EHCI_MX7
 222         imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads));
 223         gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
 224 #endif
 225
 226         return 0;
 227 }
 228
 229 #ifdef CONFIG_DM_PMIC
 230 int power_init_board(void)
 231 {
 232         struct udevice *dev;
 233         int reg, ver;
 234         int ret;
 235
 236
 237         ret = pmic_get("rn5t567@33", &dev);
 238         if (ret)
 239                 return ret;
 240         ver = pmic_reg_read(dev, RN5T567_LSIVER);
 241         reg = pmic_reg_read(dev, RN5T567_OTPVER);
 242
 243         printf("PMIC:  RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg);
 244
 245         /* set judge and press timer of N_OE to minimal values */
 246         pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0);
 247
 248         /* configure sleep slot for 3.3V Ethernet */
 249         reg = pmic_reg_read(dev, RN5T567_LDO1_SLOT);
 250         reg = (reg & 0xf0) | reg >> 4;
 251         pmic_reg_write(dev, RN5T567_LDO1_SLOT, reg);
 252
 253         /* disable DCDC2 discharge to avoid backfeeding through VFB2 */
 254         pmic_clrsetbits(dev, RN5T567_DC2CTL, 0x2, 0);
 255
 256         /* configure sleep slot for ARM rail */
 257         reg = pmic_reg_read(dev, RN5T567_DC2_SLOT);
 258         reg = (reg & 0xf0) | reg >> 4;
 259         pmic_reg_write(dev, RN5T567_DC2_SLOT, reg);
 260
 261         /* disable LDO2 discharge to avoid backfeeding from +V3.3_SD */
 262         pmic_clrsetbits(dev, RN5T567_LDODIS1, 0x2, 0);
 263
 264         return 0;
 265 }
 266
 267 void reset_cpu(ulong addr)
 268 {
 269         struct udevice *dev;
 270
 271         pmic_get("rn5t567@33", &dev);
 272
 273         /* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */
 274         pmic_reg_write(dev, RN5T567_REPCNT, 0x1);
 275         pmic_reg_write(dev, RN5T567_SLPCNT, 0x1);
 276
 277         /*
 278          * Re-power factor detection on PMIC side is not instant. 1ms
 279          * proved to be enough time until reset takes effect.
 280          */
 281         mdelay(1);
 282 }
 283 #endif
 284
 285 int checkboard(void)
 286 {
 287         printf("Model: Toradex Colibri iMX7%c\n",
 288                is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S');
 289
 290         return 0;
 291 }
 292
 293 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 294 int ft_board_setup(void *blob, bd_t *bd)
 295 {
 296 #if defined(CONFIG_IMX_BOOTAUX) && defined(CONFIG_ARCH_FIXUP_FDT_MEMORY)
 297         int up;
 298
 299         up = arch_auxiliary_core_check_up(0);
 300         if (up) {
 301                 int ret;
 302                 int areas = 1;
 303                 u64 start[2], size[2];
 304
 305                 /*
 306                  * Reserve 1MB of memory for M4 (1MiB is also the minimum
 307                  * alignment for Linux due to MMU section size restrictions).
 308                  */
 309                 start[0] = gd->bd->bi_dram[0].start;
 310                 size[0] = SZ_256M - SZ_1M;
 311
 312                 /* If needed, create a second entry for memory beyond 256M */
 313                 if (gd->bd->bi_dram[0].size > SZ_256M) {
 314                         start[1] = gd->bd->bi_dram[0].start + SZ_256M;
 315                         size[1] = gd->bd->bi_dram[0].size - SZ_256M;
 316                         areas = 2;
 317                 }
 318
 319                 ret = fdt_set_usable_memory(blob, start, size, areas);
 320                 if (ret) {
 321                         eprintf("Cannot set usable memory\n");
 322                         return ret;
 323                 }
 324         } else {
 325                 int off;
 326
 327                 off = fdt_node_offset_by_compatible(blob, -1,
 328                                                     "fsl,imx7d-rpmsg");
 329                 if (off > 0)
 330                         fdt_status_disabled(blob, off);
 331         }
 332 #endif
 333 #if defined(CONFIG_FDT_FIXUP_PARTITIONS)
 334         static const struct node_info nodes[] = {
 335                 { "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
 336                 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
 337         };
 338
 339         /* Update partition nodes using info from mtdparts env var */
 340         puts("   Updating MTD partitions...\n");
 341         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
 342 #endif
 343
 344         return ft_common_board_setup(blob, bd);
 345 }
 346 #endif
 347
 348 #ifdef CONFIG_USB_EHCI_MX7
 349 static iomux_v3_cfg_t const usb_otg2_pads[] = {
 350         MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 351 };
 352
 353 int board_ehci_hcd_init(int port)
 354 {
 355         switch (port) {
 356         case 0:
 357                 break;
 358         case 1:
 359                 if (is_cpu_type(MXC_CPU_MX7S))
 360                         return -ENODEV;
 361
 362                 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
 363                                                  ARRAY_SIZE(usb_otg2_pads));
 364                 break;
 365         default:
 366                 return -EINVAL;
 367         }
 368         return 0;
 369 }
 370
 371 int board_usb_phy_mode(int port)
 372 {
 373         switch (port) {
 374         case 0:
 375                 if (gpio_get_value(USB_CDET_GPIO))
 376                         return USB_INIT_DEVICE;
 377                 else
 378                         return USB_INIT_HOST;
 379         case 1:
 380         default:
 381                 return USB_INIT_HOST;
 382         }
 383 }
 384 #endif