board/toradex/colibri_imx7/colibri_imx7.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016-2018 Toradex AG
   4  */
   5
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <init.h>
   9 #include <net.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/crm_regs.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/mx7-pins.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <asm/gpio.h>
  16 #include <asm/mach-imx/iomux-v3.h>
  17 #include <asm/io.h>
  18 #include <common.h>
  19 #include <dm.h>
  20 #include <dm/platform_data/serial_mxc.h>
  21 #include <fdt_support.h>
  22 #include <fsl_esdhc_imx.h>
  23 #include <jffs2/load_kernel.h>
  24 #include <linux/delay.h>
  25 #include <linux/sizes.h>
  26 #include <mmc.h>
  27 #include <miiphy.h>
  28 #include <mtd_node.h>
  29 #include <netdev.h>
  30 #include <power/pmic.h>
  31 #include <power/rn5t567_pmic.h>
  32 #include <usb.h>
  33 #include <usb/ehci-ci.h>
  34 #include "../common/tdx-common.h"
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 #define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
  39         PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
  40
  41 #define ENET_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  42 #define ENET_PAD_CTRL_MII  (PAD_CTL_DSE_3P3V_32OHM)
  43
  44 #define ENET_RX_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  45
  46 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
  47         PAD_CTL_DSE_3P3V_49OHM)
  48
  49 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
  50
  51 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
  52
  53 #define USB_CDET_GPIO   IMX_GPIO_NR(7, 14)
  54
  55 int dram_init(void)
  56 {
  57         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, imx_ddr_size());
  58
  59         return 0;
  60 }
  61
  62 static iomux_v3_cfg_t const uart1_pads[] = {
  63         MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  64         MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  65         MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
  66         MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
  67 };
  68
  69 #ifdef CONFIG_USB_EHCI_MX7
  70 static iomux_v3_cfg_t const usb_cdet_pads[] = {
  71         MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
  72 };
  73 #endif
  74
  75 #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
  76 static iomux_v3_cfg_t const gpmi_pads[] = {
  77         MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  78         MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  79         MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  80         MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  81         MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  82         MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  83         MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  84         MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  85         MX7D_PAD_SD3_CLK__NAND_CLE      | MUX_PAD_CTRL(NAND_PAD_CTRL),
  86         MX7D_PAD_SD3_CMD__NAND_ALE      | MUX_PAD_CTRL(NAND_PAD_CTRL),
  87         MX7D_PAD_SD3_STROBE__NAND_RE_B  | MUX_PAD_CTRL(NAND_PAD_CTRL),
  88         MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  89         MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B       | MUX_PAD_CTRL(NAND_PAD_CTRL),
  90         MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B       | MUX_PAD_CTRL(NAND_PAD_CTRL),
  91         MX7D_PAD_SAI1_TX_DATA__NAND_READY_B     | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
  92 };
  93
  94 static void setup_gpmi_nand(void)
  95 {
  96         imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
  97
  98         /* NAND_USDHC_BUS_CLK is set in rom */
  99         set_clk_nand();
 100 }
 101 #endif
 102
 103 #ifdef CONFIG_VIDEO_MXS
 104 static iomux_v3_cfg_t const lcd_pads[] = {
 105         MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
 106         MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
 107         MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
 108         MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
 109         MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 110         MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 111         MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 112         MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 113         MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 114         MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 115         MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 116         MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 117         MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 118         MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 119         MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 120         MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 121         MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 122         MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 123         MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 124         MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 125         MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 126         MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 127 };
 128
 129 static iomux_v3_cfg_t const backlight_pads[] = {
 130         /* Backlight On */
 131         MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
 132         /* Backlight PWM<A> (multiplexed pin) */
 133         MX7D_PAD_GPIO1_IO08__GPIO1_IO8   | MUX_PAD_CTRL(NO_PAD_CTRL),
 134         MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 135 };
 136
 137 #define GPIO_BL_ON IMX_GPIO_NR(5, 1)
 138 #define GPIO_PWM_A IMX_GPIO_NR(1, 8)
 139
 140 static int setup_lcd(void)
 141 {
 142         imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 143
 144         imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
 145
 146         /* Set BL_ON */
 147         gpio_request(GPIO_BL_ON, "BL_ON");
 148         gpio_direction_output(GPIO_BL_ON, 1);
 149
 150         /* Set PWM<A> to full brightness (assuming inversed polarity) */
 151         gpio_request(GPIO_PWM_A, "PWM<A>");
 152         gpio_direction_output(GPIO_PWM_A, 0);
 153
 154         return 0;
 155 }
 156 #endif
 157
 158 /*
 159  * Backlight off before OS handover
 160  */
 161 void board_preboot_os(void)
 162 {
 163         gpio_direction_output(GPIO_PWM_A, 1);
 164         gpio_direction_output(GPIO_BL_ON, 0);
 165 }
 166
 167 static void setup_iomux_uart(void)
 168 {
 169         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 170 }
 171
 172 #ifdef CONFIG_FEC_MXC
 173 static int setup_fec(void)
 174 {
 175         struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
 176                 = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
 177
 178 #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
 179         /*
 180          * Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]
 181          * and output it on the pin
 182          */
 183         clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
 184                         IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK,
 185                         IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK);
 186 #else
 187         /* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */
 188         clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
 189                         IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK,
 190                         IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
 191 #endif
 192
 193         return set_clk_enet(ENET_50MHZ);
 194 }
 195
 196 #endif
 197
 198 int board_early_init_f(void)
 199 {
 200         setup_iomux_uart();
 201
 202         return 0;
 203 }
 204
 205 int board_init(void)
 206 {
 207         /* address of boot parameters */
 208         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 209
 210 #ifdef CONFIG_FEC_MXC
 211         setup_fec();
 212 #endif
 213
 214 #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
 215         setup_gpmi_nand();
 216 #endif
 217
 218 #ifdef CONFIG_VIDEO_MXS
 219         setup_lcd();
 220 #endif
 221
 222 #ifdef CONFIG_USB_EHCI_MX7
 223         imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads));
 224         gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
 225 #endif
 226
 227         return 0;
 228 }
 229
 230 #ifdef CONFIG_DM_PMIC
 231 int power_init_board(void)
 232 {
 233         struct udevice *dev;
 234         int reg, ver;
 235         int ret;
 236
 237
 238         ret = pmic_get("rn5t567@33", &dev);
 239         if (ret)
 240                 return ret;
 241         ver = pmic_reg_read(dev, RN5T567_LSIVER);
 242         reg = pmic_reg_read(dev, RN5T567_OTPVER);
 243
 244         printf("PMIC:  RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg);
 245
 246         /* set judge and press timer of N_OE to minimal values */
 247         pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0);
 248
 249         /* configure sleep slot for 3.3V Ethernet */
 250         reg = pmic_reg_read(dev, RN5T567_LDO1_SLOT);
 251         reg = (reg & 0xf0) | reg >> 4;
 252         pmic_reg_write(dev, RN5T567_LDO1_SLOT, reg);
 253
 254         /* disable DCDC2 discharge to avoid backfeeding through VFB2 */
 255         pmic_clrsetbits(dev, RN5T567_DC2CTL, 0x2, 0);
 256
 257         /* configure sleep slot for ARM rail */
 258         reg = pmic_reg_read(dev, RN5T567_DC2_SLOT);
 259         reg = (reg & 0xf0) | reg >> 4;
 260         pmic_reg_write(dev, RN5T567_DC2_SLOT, reg);
 261
 262         /* disable LDO2 discharge to avoid backfeeding from +V3.3_SD */
 263         pmic_clrsetbits(dev, RN5T567_LDODIS1, 0x2, 0);
 264
 265         return 0;
 266 }
 267
 268 void reset_cpu(ulong addr)
 269 {
 270         struct udevice *dev;
 271
 272         pmic_get("rn5t567@33", &dev);
 273
 274         /* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */
 275         pmic_reg_write(dev, RN5T567_REPCNT, 0x1);
 276         pmic_reg_write(dev, RN5T567_SLPCNT, 0x1);
 277
 278         /*
 279          * Re-power factor detection on PMIC side is not instant. 1ms
 280          * proved to be enough time until reset takes effect.
 281          */
 282         mdelay(1);
 283 }
 284 #endif
 285
 286 int checkboard(void)
 287 {
 288         printf("Model: Toradex Colibri iMX7%c\n",
 289                is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S');
 290
 291         return 0;
 292 }
 293
 294 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 295 int ft_board_setup(void *blob, bd_t *bd)
 296 {
 297 #if defined(CONFIG_IMX_BOOTAUX) && defined(CONFIG_ARCH_FIXUP_FDT_MEMORY)
 298         int up;
 299
 300         up = arch_auxiliary_core_check_up(0);
 301         if (up) {
 302                 int ret;
 303                 int areas = 1;
 304                 u64 start[2], size[2];
 305
 306                 /*
 307                  * Reserve 1MB of memory for M4 (1MiB is also the minimum
 308                  * alignment for Linux due to MMU section size restrictions).
 309                  */
 310                 start[0] = gd->bd->bi_dram[0].start;
 311                 size[0] = SZ_256M - SZ_1M;
 312
 313                 /* If needed, create a second entry for memory beyond 256M */
 314                 if (gd->bd->bi_dram[0].size > SZ_256M) {
 315                         start[1] = gd->bd->bi_dram[0].start + SZ_256M;
 316                         size[1] = gd->bd->bi_dram[0].size - SZ_256M;
 317                         areas = 2;
 318                 }
 319
 320                 ret = fdt_set_usable_memory(blob, start, size, areas);
 321                 if (ret) {
 322                         eprintf("Cannot set usable memory\n");
 323                         return ret;
 324                 }
 325         } else {
 326                 int off;
 327
 328                 off = fdt_node_offset_by_compatible(blob, -1,
 329                                                     "fsl,imx7d-rpmsg");
 330                 if (off > 0)
 331                         fdt_status_disabled(blob, off);
 332         }
 333 #endif
 334 #if defined(CONFIG_FDT_FIXUP_PARTITIONS)
 335         static const struct node_info nodes[] = {
 336                 { "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
 337                 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
 338         };
 339
 340         /* Update partition nodes using info from mtdparts env var */
 341         puts("   Updating MTD partitions...\n");
 342         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
 343 #endif
 344
 345         return ft_common_board_setup(blob, bd);
 346 }
 347 #endif
 348
 349 #ifdef CONFIG_USB_EHCI_MX7
 350 static iomux_v3_cfg_t const usb_otg2_pads[] = {
 351         MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 352 };
 353
 354 int board_ehci_hcd_init(int port)
 355 {
 356         switch (port) {
 357         case 0:
 358                 break;
 359         case 1:
 360                 if (is_cpu_type(MXC_CPU_MX7S))
 361                         return -ENODEV;
 362
 363                 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
 364                                                  ARRAY_SIZE(usb_otg2_pads));
 365                 break;
 366         default:
 367                 return -EINVAL;
 368         }
 369         return 0;
 370 }
 371
 372 int board_usb_phy_mode(int port)
 373 {
 374         switch (port) {
 375         case 0:
 376                 if (gpio_get_value(USB_CDET_GPIO))
 377                         return USB_INIT_DEVICE;
 378                 else
 379                         return USB_INIT_HOST;
 380         case 1:
 381         default:
 382                 return USB_INIT_HOST;
 383         }
 384 }
 385 #endif