board/toradex/colibri_imx6/colibri_imx6.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   5  * Copyright (C) 2014-2019, Toradex AG
   6  * copied from nitrogen6x
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <env.h>
  12 #include <init.h>
  13
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/crm_regs.h>
  16 #include <asm/arch/imx-regs.h>
  17 #include <asm/arch/mx6-ddr.h>
  18 #include <asm/arch/mx6-pins.h>
  19 #include <asm/arch/mxc_hdmi.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/bootm.h>
  22 #include <asm/gpio.h>
  23 #include <asm/mach-imx/boot_mode.h>
  24 #include <asm/mach-imx/iomux-v3.h>
  25 #include <asm/mach-imx/sata.h>
  26 #include <asm/mach-imx/video.h>
  27 #include <cpu.h>
  28 #include <dm/platform_data/serial_mxc.h>
  29 #include <fsl_esdhc_imx.h>
  30 #include <imx_thermal.h>
  31 #include <micrel.h>
  32 #include <miiphy.h>
  33 #include <netdev.h>
  34 #include <cpu.h>
  35
  36 #include "../common/tdx-cfg-block.h"
  37 #ifdef CONFIG_TDX_CMD_IMX_MFGR
  38 #include "pf0100.h"
  39 #endif
  40
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  44         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  45         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  46
  47 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  48         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |                 \
  49         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  50
  51 #define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP |               \
  52         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  53         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  54
  55 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  56         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  57
  58 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  59         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  60         PAD_CTL_SRE_SLOW)
  61
  62 #define NO_PULLUP       (                                       \
  63         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  64         PAD_CTL_SRE_SLOW)
  65
  66 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  67         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  68         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  69
  70 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
  71
  72 int dram_init(void)
  73 {
  74         /* use the DDR controllers configured size */
  75         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  76                                     (ulong)imx_ddr_size());
  77
  78         return 0;
  79 }
  80
  81 /* Colibri UARTA */
  82 iomux_v3_cfg_t const uart1_pads[] = {
  83         MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  84         MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  85 };
  86
  87 #if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
  88 /* Colibri MMC */
  89 iomux_v3_cfg_t const usdhc1_pads[] = {
  90         MX6_PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  91         MX6_PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  92         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  93         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  94         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  95         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  96         MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  97 #       define GPIO_MMC_CD IMX_GPIO_NR(2, 5)
  98 };
  99
 100 /* eMMC */
 101 iomux_v3_cfg_t const usdhc3_pads[] = {
 102         MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 103         MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 104         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 105         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 106         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 107         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 108         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 109         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 110         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 111         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 112         MX6_PAD_SD3_RST__SD3_RESET  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 113 };
 114 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
 115
 116 iomux_v3_cfg_t const enet_pads[] = {
 117         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 118         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 119         MX6_PAD_ENET_RXD0__ENET_RX_DATA0        | MUX_PAD_CTRL(ENET_PAD_CTRL),
 120         MX6_PAD_ENET_RXD1__ENET_RX_DATA1        | MUX_PAD_CTRL(ENET_PAD_CTRL),
 121         MX6_PAD_ENET_RX_ER__ENET_RX_ER          | MUX_PAD_CTRL(ENET_PAD_CTRL),
 122         MX6_PAD_ENET_TX_EN__ENET_TX_EN          | MUX_PAD_CTRL(ENET_PAD_CTRL),
 123         MX6_PAD_ENET_TXD0__ENET_TX_DATA0        | MUX_PAD_CTRL(ENET_PAD_CTRL),
 124         MX6_PAD_ENET_TXD1__ENET_TX_DATA1        | MUX_PAD_CTRL(ENET_PAD_CTRL),
 125         MX6_PAD_ENET_CRS_DV__ENET_RX_EN         | MUX_PAD_CTRL(ENET_PAD_CTRL),
 126         MX6_PAD_GPIO_16__ENET_REF_CLK           | MUX_PAD_CTRL(ENET_PAD_CTRL),
 127 };
 128
 129 static void setup_iomux_enet(void)
 130 {
 131         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 132 }
 133
 134 /* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
 135 iomux_v3_cfg_t const gpio_pads[] = {
 136         /* ADDRESS[17:18] [25] used as GPIO */
 137         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(WEAK_PULLUP) |
 138                                           MUX_MODE_SION,
 139         MX6_PAD_KEY_COL2__GPIO4_IO10    | MUX_PAD_CTRL(WEAK_PULLUP) |
 140                                           MUX_MODE_SION,
 141         MX6_PAD_NANDF_D1__GPIO2_IO01    | MUX_PAD_CTRL(WEAK_PULLUP) |
 142                                           MUX_MODE_SION,
 143         /* ADDRESS[19:24] used as GPIO */
 144         MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
 145                                           MUX_MODE_SION,
 146         MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
 147                                           MUX_MODE_SION,
 148         MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
 149                                           MUX_MODE_SION,
 150         MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
 151                                           MUX_MODE_SION,
 152         MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
 153                                           MUX_MODE_SION,
 154         MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP) |
 155                                           MUX_MODE_SION,
 156         /* DATA[16:29] [31]      used as GPIO */
 157         MX6_PAD_EIM_LBA__GPIO2_IO27     | MUX_PAD_CTRL(WEAK_PULLUP) |
 158                                           MUX_MODE_SION,
 159         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(WEAK_PULLUP) |
 160                                           MUX_MODE_SION,
 161         MX6_PAD_NANDF_CS3__GPIO6_IO16   | MUX_PAD_CTRL(WEAK_PULLUP) |
 162                                           MUX_MODE_SION,
 163         MX6_PAD_NANDF_CS1__GPIO6_IO14   | MUX_PAD_CTRL(WEAK_PULLUP) |
 164                                           MUX_MODE_SION,
 165         MX6_PAD_NANDF_RB0__GPIO6_IO10   | MUX_PAD_CTRL(WEAK_PULLUP) |
 166                                           MUX_MODE_SION,
 167         MX6_PAD_NANDF_ALE__GPIO6_IO08   | MUX_PAD_CTRL(WEAK_PULLUP) |
 168                                           MUX_MODE_SION,
 169         MX6_PAD_NANDF_WP_B__GPIO6_IO09  | MUX_PAD_CTRL(WEAK_PULLUP) |
 170                                           MUX_MODE_SION,
 171         MX6_PAD_NANDF_CS0__GPIO6_IO11   | MUX_PAD_CTRL(WEAK_PULLUP) |
 172                                           MUX_MODE_SION,
 173         MX6_PAD_NANDF_CLE__GPIO6_IO07   | MUX_PAD_CTRL(WEAK_PULLUP) |
 174                                           MUX_MODE_SION,
 175         MX6_PAD_GPIO_19__GPIO4_IO05     | MUX_PAD_CTRL(WEAK_PULLUP) |
 176                                           MUX_MODE_SION,
 177         MX6_PAD_CSI0_MCLK__GPIO5_IO19   | MUX_PAD_CTRL(WEAK_PULLUP) |
 178                                           MUX_MODE_SION,
 179         MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
 180                                           MUX_MODE_SION,
 181         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(WEAK_PULLUP) |
 182                                           MUX_MODE_SION,
 183         MX6_PAD_GPIO_5__GPIO1_IO05      | MUX_PAD_CTRL(WEAK_PULLUP) |
 184                                           MUX_MODE_SION,
 185         MX6_PAD_GPIO_2__GPIO1_IO02      | MUX_PAD_CTRL(WEAK_PULLUP) |
 186                                           MUX_MODE_SION,
 187         /* DQM[0:3]      used as GPIO */
 188         MX6_PAD_EIM_EB0__GPIO2_IO28     | MUX_PAD_CTRL(WEAK_PULLUP) |
 189                                           MUX_MODE_SION,
 190         MX6_PAD_EIM_EB1__GPIO2_IO29     | MUX_PAD_CTRL(WEAK_PULLUP) |
 191                                           MUX_MODE_SION,
 192         MX6_PAD_SD2_DAT2__GPIO1_IO13    | MUX_PAD_CTRL(WEAK_PULLUP) |
 193                                           MUX_MODE_SION,
 194         MX6_PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(WEAK_PULLUP) |
 195                                           MUX_MODE_SION,
 196         /* RDY  used as GPIO */
 197         MX6_PAD_EIM_WAIT__GPIO5_IO00    | MUX_PAD_CTRL(WEAK_PULLUP) |
 198                                           MUX_MODE_SION,
 199         /* ADDRESS[16] DATA[30]  used as GPIO */
 200         MX6_PAD_KEY_ROW4__GPIO4_IO15    | MUX_PAD_CTRL(WEAK_PULLDOWN) |
 201                                           MUX_MODE_SION,
 202         MX6_PAD_KEY_COL4__GPIO4_IO14    | MUX_PAD_CTRL(WEAK_PULLUP) |
 203                                           MUX_MODE_SION,
 204         /* CSI pins used as GPIO */
 205         MX6_PAD_EIM_A24__GPIO5_IO04     | MUX_PAD_CTRL(WEAK_PULLUP) |
 206                                           MUX_MODE_SION,
 207         MX6_PAD_SD2_CMD__GPIO1_IO11     | MUX_PAD_CTRL(WEAK_PULLUP) |
 208                                           MUX_MODE_SION,
 209         MX6_PAD_NANDF_CS2__GPIO6_IO15   | MUX_PAD_CTRL(WEAK_PULLUP) |
 210                                           MUX_MODE_SION,
 211         MX6_PAD_EIM_D18__GPIO3_IO18     | MUX_PAD_CTRL(WEAK_PULLUP) |
 212                                           MUX_MODE_SION,
 213         MX6_PAD_EIM_A19__GPIO2_IO19     | MUX_PAD_CTRL(WEAK_PULLUP) |
 214                                           MUX_MODE_SION,
 215         MX6_PAD_EIM_D29__GPIO3_IO29     | MUX_PAD_CTRL(WEAK_PULLDOWN) |
 216                                           MUX_MODE_SION,
 217         MX6_PAD_EIM_A23__GPIO6_IO06     | MUX_PAD_CTRL(WEAK_PULLUP) |
 218                                           MUX_MODE_SION,
 219         MX6_PAD_EIM_A20__GPIO2_IO18     | MUX_PAD_CTRL(WEAK_PULLUP) |
 220                                           MUX_MODE_SION,
 221         MX6_PAD_EIM_A17__GPIO2_IO21     | MUX_PAD_CTRL(WEAK_PULLUP) |
 222                                           MUX_MODE_SION,
 223         MX6_PAD_EIM_A18__GPIO2_IO20     | MUX_PAD_CTRL(WEAK_PULLUP) |
 224                                           MUX_MODE_SION,
 225         MX6_PAD_EIM_EB3__GPIO2_IO31     | MUX_PAD_CTRL(WEAK_PULLUP) |
 226                                           MUX_MODE_SION,
 227         MX6_PAD_EIM_D17__GPIO3_IO17     | MUX_PAD_CTRL(WEAK_PULLUP) |
 228                                           MUX_MODE_SION,
 229         MX6_PAD_SD2_DAT0__GPIO1_IO15    | MUX_PAD_CTRL(WEAK_PULLUP) |
 230                                           MUX_MODE_SION,
 231         /* GPIO */
 232         MX6_PAD_EIM_D26__GPIO3_IO26     | MUX_PAD_CTRL(WEAK_PULLUP) |
 233                                           MUX_MODE_SION,
 234         MX6_PAD_EIM_D27__GPIO3_IO27     | MUX_PAD_CTRL(WEAK_PULLUP) |
 235                                           MUX_MODE_SION,
 236         MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(WEAK_PULLUP) |
 237                                           MUX_MODE_SION,
 238         MX6_PAD_NANDF_D3__GPIO2_IO03    | MUX_PAD_CTRL(WEAK_PULLUP) |
 239                                           MUX_MODE_SION,
 240         MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP) |
 241                                           MUX_MODE_SION,
 242         MX6_PAD_DI0_PIN4__GPIO4_IO20    | MUX_PAD_CTRL(WEAK_PULLUP) |
 243                                           MUX_MODE_SION,
 244         MX6_PAD_SD4_DAT3__GPIO2_IO11    | MUX_PAD_CTRL(WEAK_PULLUP) |
 245                                           MUX_MODE_SION,
 246         MX6_PAD_NANDF_D4__GPIO2_IO04    | MUX_PAD_CTRL(WEAK_PULLUP) |
 247                                           MUX_MODE_SION,
 248         MX6_PAD_SD4_DAT0__GPIO2_IO08    | MUX_PAD_CTRL(WEAK_PULLUP) |
 249                                           MUX_MODE_SION,
 250         MX6_PAD_GPIO_7__GPIO1_IO07      | MUX_PAD_CTRL(WEAK_PULLUP) |
 251                                           MUX_MODE_SION,
 252         MX6_PAD_GPIO_8__GPIO1_IO08      | MUX_PAD_CTRL(WEAK_PULLUP) |
 253                                           MUX_MODE_SION,
 254         /* USBH_OC */
 255         MX6_PAD_EIM_D30__GPIO3_IO30     | MUX_PAD_CTRL(WEAK_PULLUP),
 256         /* USBC_ID */
 257         MX6_PAD_NANDF_D2__GPIO2_IO02    | MUX_PAD_CTRL(WEAK_PULLUP),
 258         /* USBC_DET */
 259         MX6_PAD_GPIO_17__GPIO7_IO12     | MUX_PAD_CTRL(WEAK_PULLUP),
 260 };
 261
 262 static void setup_iomux_gpio(void)
 263 {
 264         imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
 265 }
 266
 267 iomux_v3_cfg_t const usb_pads[] = {
 268         /* USBH_PEN */
 269         MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 270 #       define GPIO_USBH_EN IMX_GPIO_NR(3, 31)
 271 };
 272
 273 /*
 274  * UARTs are used in DTE mode, switch the mode on all UARTs before
 275  * any pinmuxing connects a (DCE) output to a transceiver output.
 276  */
 277 #define UCR3            0x88    /* FIFO Control Register */
 278 #define UCR3_RI         BIT(8)  /* RIDELT DTE mode */
 279 #define UCR3_DCD        BIT(9)  /* DCDDELT DTE mode */
 280 #define UFCR            0x90    /* FIFO Control Register */
 281 #define UFCR_DCEDTE     BIT(6)  /* DCE=0 */
 282
 283 static void setup_dtemode_uart(void)
 284 {
 285         setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 286         setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 287         setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE);
 288
 289         clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
 290         clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
 291         clrbits_le32((u32 *)(UART3_BASE + UCR3), UCR3_DCD | UCR3_RI);
 292 }
 293
 294 static void setup_iomux_uart(void)
 295 {
 296         setup_dtemode_uart();
 297         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 298 }
 299
 300 #ifdef CONFIG_USB_EHCI_MX6
 301 int board_ehci_hcd_init(int port)
 302 {
 303         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 304         return 0;
 305 }
 306 #endif
 307
 308 #if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
 309 /* use the following sequence: eMMC, MMC */
 310 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
 311         {USDHC3_BASE_ADDR},
 312         {USDHC1_BASE_ADDR},
 313 };
 314
 315 int board_mmc_getcd(struct mmc *mmc)
 316 {
 317         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 318         int ret = true; /* default: assume inserted */
 319
 320         switch (cfg->esdhc_base) {
 321         case USDHC1_BASE_ADDR:
 322                 gpio_request(GPIO_MMC_CD, "MMC_CD");
 323                 gpio_direction_input(GPIO_MMC_CD);
 324                 ret = !gpio_get_value(GPIO_MMC_CD);
 325                 break;
 326         }
 327
 328         return ret;
 329 }
 330
 331 int board_mmc_init(bd_t *bis)
 332 {
 333         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 334         unsigned reg = readl(&psrc->sbmr1) >> 11;
 335         /*
 336          * Upon reading BOOT_CFG register the following map is done:
 337          * Bit 11 and 12 of BOOT_CFG register can determine the current
 338          * mmc port
 339          * 0x1                  SD1
 340          * 0x2                  SD2
 341          * 0x3                  SD4
 342          */
 343
 344         switch (reg & 0x3) {
 345         case 0x0:
 346                 imx_iomux_v3_setup_multiple_pads(
 347                         usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 348                 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
 349                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 350                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 351                 break;
 352         case 0x2:
 353                 imx_iomux_v3_setup_multiple_pads(
 354                         usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 355                 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 356                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 357                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 358                 break;
 359         default:
 360                 puts("MMC boot device not available");
 361         }
 362
 363         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 364 }
 365 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
 366
 367 int board_phy_config(struct phy_device *phydev)
 368 {
 369         if (phydev->drv->config)
 370                 phydev->drv->config(phydev);
 371
 372         return 0;
 373 }
 374
 375 int board_eth_init(bd_t *bis)
 376 {
 377         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 378         uint32_t base = IMX_FEC_BASE;
 379         struct mii_dev *bus = NULL;
 380         struct phy_device *phydev = NULL;
 381         int ret;
 382
 383         /* provide the PHY clock from the i.MX 6 */
 384         ret = enable_fec_anatop_clock(0, ENET_50MHZ);
 385         if (ret)
 386                 return ret;
 387
 388         /* set gpr1[ENET_CLK_SEL] */
 389         setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
 390
 391         setup_iomux_enet();
 392
 393 #ifdef CONFIG_FEC_MXC
 394         bus = fec_get_miibus(base, -1);
 395         if (!bus)
 396                 return 0;
 397
 398         /* scan PHY 1..7 */
 399         phydev = phy_find_by_mask(bus, 0xff, PHY_INTERFACE_MODE_RMII);
 400         if (!phydev) {
 401                 free(bus);
 402                 puts("no PHY found\n");
 403                 return 0;
 404         }
 405
 406         phy_reset(phydev);
 407         printf("using PHY at %d\n", phydev->addr);
 408         ret = fec_probe(bis, -1, base, bus, phydev);
 409         if (ret) {
 410                 printf("FEC MXC: %s:failed\n", __func__);
 411                 free(phydev);
 412                 free(bus);
 413         }
 414 #endif /* CONFIG_FEC_MXC */
 415
 416         return 0;
 417 }
 418
 419 static iomux_v3_cfg_t const pwr_intb_pads[] = {
 420         /*
 421          * the bootrom sets the iomux to vselect, potentially connecting
 422          * two outputs. Set this back to GPIO
 423          */
 424         MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
 425 };
 426
 427 #if defined(CONFIG_VIDEO_IPUV3)
 428
 429 static iomux_v3_cfg_t const backlight_pads[] = {
 430         /* Backlight On */
 431         MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 432 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26)
 433         /* Backlight PWM, used as GPIO in U-Boot */
 434         MX6_PAD_EIM_A22__GPIO2_IO16  | MUX_PAD_CTRL(NO_PULLUP),
 435         MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 436                                        MUX_MODE_SION,
 437 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9)
 438 };
 439
 440 static iomux_v3_cfg_t const rgb_pads[] = {
 441         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
 442         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
 443         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
 444         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
 445         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
 446         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
 447         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
 448         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
 449         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
 450         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
 451         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
 452         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
 453         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
 454         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
 455         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
 456         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
 457         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
 458         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
 459         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
 460         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
 461         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
 462         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
 463 };
 464
 465 static void do_enable_hdmi(struct display_info_t const *dev)
 466 {
 467         imx_enable_hdmi_phy();
 468 }
 469
 470 static void enable_rgb(struct display_info_t const *dev)
 471 {
 472         imx_iomux_v3_setup_multiple_pads(
 473                 rgb_pads,
 474                 ARRAY_SIZE(rgb_pads));
 475         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 476         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 477 }
 478
 479 static int detect_default(struct display_info_t const *dev)
 480 {
 481         (void) dev;
 482         return 1;
 483 }
 484
 485 struct display_info_t const displays[] = {{
 486         .bus    = -1,
 487         .addr   = 0,
 488         .pixfmt = IPU_PIX_FMT_RGB24,
 489         .detect = detect_hdmi,
 490         .enable = do_enable_hdmi,
 491         .mode   = {
 492                 .name           = "HDMI",
 493                 .refresh        = 60,
 494                 .xres           = 1024,
 495                 .yres           = 768,
 496                 .pixclock       = 15385,
 497                 .left_margin    = 220,
 498                 .right_margin   = 40,
 499                 .upper_margin   = 21,
 500                 .lower_margin   = 7,
 501                 .hsync_len      = 60,
 502                 .vsync_len      = 10,
 503                 .sync           = FB_SYNC_EXT,
 504                 .vmode          = FB_VMODE_NONINTERLACED
 505 } }, {
 506         .bus    = -1,
 507         .addr   = 0,
 508         .pixfmt = IPU_PIX_FMT_RGB666,
 509         .detect = detect_default,
 510         .enable = enable_rgb,
 511         .mode   = {
 512                 .name           = "vga-rgb",
 513                 .refresh        = 60,
 514                 .xres           = 640,
 515                 .yres           = 480,
 516                 .pixclock       = 33000,
 517                 .left_margin    = 48,
 518                 .right_margin   = 16,
 519                 .upper_margin   = 31,
 520                 .lower_margin   = 11,
 521                 .hsync_len      = 96,
 522                 .vsync_len      = 2,
 523                 .sync           = 0,
 524                 .vmode          = FB_VMODE_NONINTERLACED
 525 } }, {
 526         .bus    = -1,
 527         .addr   = 0,
 528         .pixfmt = IPU_PIX_FMT_RGB666,
 529         .enable = enable_rgb,
 530         .mode   = {
 531                 .name           = "wvga-rgb",
 532                 .refresh        = 60,
 533                 .xres           = 800,
 534                 .yres           = 480,
 535                 .pixclock       = 25000,
 536                 .left_margin    = 40,
 537                 .right_margin   = 88,
 538                 .upper_margin   = 33,
 539                 .lower_margin   = 10,
 540                 .hsync_len      = 128,
 541                 .vsync_len      = 2,
 542                 .sync           = 0,
 543                 .vmode          = FB_VMODE_NONINTERLACED
 544 } } };
 545 size_t display_count = ARRAY_SIZE(displays);
 546
 547 static void setup_display(void)
 548 {
 549         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 550         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 551         int reg;
 552
 553         enable_ipu_clock();
 554         imx_setup_hdmi();
 555         /* Turn on LDB0,IPU,IPU DI0 clocks */
 556         reg = __raw_readl(&mxc_ccm->CCGR3);
 557         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 558         writel(reg, &mxc_ccm->CCGR3);
 559
 560         /* set LDB0, LDB1 clk select to 011/011 */
 561         reg = readl(&mxc_ccm->cs2cdr);
 562         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 563                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 564         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 565               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 566         writel(reg, &mxc_ccm->cs2cdr);
 567
 568         reg = readl(&mxc_ccm->cscmr2);
 569         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 570         writel(reg, &mxc_ccm->cscmr2);
 571
 572         reg = readl(&mxc_ccm->chsccdr);
 573         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 574                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 575         writel(reg, &mxc_ccm->chsccdr);
 576
 577         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 578              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 579              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 580              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 581              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 582              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 583              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 584              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 585              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 586         writel(reg, &iomux->gpr[2]);
 587
 588         reg = readl(&iomux->gpr[3]);
 589         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 590                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 591             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 592                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 593         writel(reg, &iomux->gpr[3]);
 594
 595         /* backlight unconditionally on for now */
 596         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 597                                          ARRAY_SIZE(backlight_pads));
 598         /* use 0 for EDT 7", use 1 for LG fullHD panel */
 599         gpio_request(RGB_BACKLIGHTPWM_GP, "PWM<A>");
 600         gpio_request(RGB_BACKLIGHT_GP, "BL_ON");
 601         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 602         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 603 }
 604
 605 /*
 606  * Backlight off before OS handover
 607  */
 608 void board_preboot_os(void)
 609 {
 610         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
 611         gpio_direction_output(RGB_BACKLIGHT_GP, 0);
 612 }
 613 #endif /* defined(CONFIG_VIDEO_IPUV3) */
 614
 615 int board_early_init_f(void)
 616 {
 617         imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
 618                                          ARRAY_SIZE(pwr_intb_pads));
 619         setup_iomux_uart();
 620
 621         return 0;
 622 }
 623
 624 /*
 625  * Do not overwrite the console
 626  * Use always serial for U-Boot console
 627  */
 628 int overwrite_console(void)
 629 {
 630         return 1;
 631 }
 632
 633 int board_init(void)
 634 {
 635         /* address of boot parameters */
 636         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 637
 638 #if defined(CONFIG_VIDEO_IPUV3)
 639         setup_display();
 640 #endif
 641
 642 #ifdef CONFIG_TDX_CMD_IMX_MFGR
 643         (void) pmic_init();
 644 #endif
 645
 646 #ifdef CONFIG_SATA
 647         setup_sata();
 648 #endif
 649
 650         setup_iomux_gpio();
 651
 652         return 0;
 653 }
 654
 655 #ifdef CONFIG_BOARD_LATE_INIT
 656 int board_late_init(void)
 657 {
 658 #if defined(CONFIG_REVISION_TAG) && \
 659     defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
 660         char env_str[256];
 661         u32 rev;
 662
 663         rev = get_board_rev();
 664         snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
 665         env_set("board_rev", env_str);
 666 #endif
 667
 668 #ifdef CONFIG_CMD_USB_SDP
 669         if (is_boot_from_usb()) {
 670                 printf("Serial Downloader recovery mode, using sdp command\n");
 671                 env_set("bootdelay", "0");
 672                 env_set("bootcmd", "sdp 0");
 673         }
 674 #endif /* CONFIG_CMD_USB_SDP */
 675
 676         return 0;
 677 }
 678 #endif /* CONFIG_BOARD_LATE_INIT */
 679
 680 int checkboard(void)
 681 {
 682         char it[] = " IT";
 683         int minc, maxc;
 684
 685         switch (get_cpu_temp_grade(&minc, &maxc)) {
 686         case TEMP_AUTOMOTIVE:
 687         case TEMP_INDUSTRIAL:
 688                 break;
 689         case TEMP_EXTCOMMERCIAL:
 690         default:
 691                 it[0] = 0;
 692         };
 693         printf("Model: Toradex Colibri iMX6 %s %sMB%s\n",
 694                is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo",
 695                (gd->ram_size == 0x20000000) ? "512" : "256", it);
 696         return 0;
 697 }
 698
 699 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 700 int ft_board_setup(void *blob, bd_t *bd)
 701 {
 702         u32 cma_size;
 703
 704         ft_common_board_setup(blob, bd);
 705
 706         cma_size = env_get_ulong("cma-size", 10, 320 * 1024 * 1024);
 707         cma_size = min((u32)(gd->ram_size >> 1), cma_size);
 708
 709         fdt_setprop_u32(blob,
 710                         fdt_path_offset(blob, "/reserved-memory/linux,cma"),
 711                         "size",
 712                         cma_size);
 713         return 0;
 714 }
 715 #endif
 716
 717 #ifdef CONFIG_CMD_BMODE
 718 static const struct boot_mode board_boot_modes[] = {
 719         {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 720         {NULL,  0},
 721 };
 722 #endif
 723
 724 int misc_init_r(void)
 725 {
 726 #ifdef CONFIG_CMD_BMODE
 727         add_board_boot_modes(board_boot_modes);
 728 #endif
 729         return 0;
 730 }
 731
 732 #ifdef CONFIG_LDO_BYPASS_CHECK
 733 /* TODO, use external pmic, for now always ldo_enable */
 734 void ldo_mode_set(int ldo_bypass)
 735 {
 736         return;
 737 }
 738 #endif
 739
 740 #ifdef CONFIG_SPL_BUILD
 741 #include <spl.h>
 742 #include <linux/libfdt.h>
 743 #include "asm/arch/mx6dl-ddr.h"
 744 #include "asm/arch/iomux.h"
 745 #include "asm/arch/crm_regs.h"
 746
 747 static int mx6s_dcd_table[] = {
 748 /* ddr-setup.cfg */
 749
 750 MX6_IOM_DRAM_SDQS0, 0x00000030,
 751 MX6_IOM_DRAM_SDQS1, 0x00000030,
 752 MX6_IOM_DRAM_SDQS2, 0x00000030,
 753 MX6_IOM_DRAM_SDQS3, 0x00000030,
 754 MX6_IOM_DRAM_SDQS4, 0x00000030,
 755 MX6_IOM_DRAM_SDQS5, 0x00000030,
 756 MX6_IOM_DRAM_SDQS6, 0x00000030,
 757 MX6_IOM_DRAM_SDQS7, 0x00000030,
 758
 759 MX6_IOM_GRP_B0DS, 0x00000030,
 760 MX6_IOM_GRP_B1DS, 0x00000030,
 761 MX6_IOM_GRP_B2DS, 0x00000030,
 762 MX6_IOM_GRP_B3DS, 0x00000030,
 763 MX6_IOM_GRP_B4DS, 0x00000030,
 764 MX6_IOM_GRP_B5DS, 0x00000030,
 765 MX6_IOM_GRP_B6DS, 0x00000030,
 766 MX6_IOM_GRP_B7DS, 0x00000030,
 767 MX6_IOM_GRP_ADDDS, 0x00000030,
 768 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 769 MX6_IOM_GRP_CTLDS, 0x00000030,
 770
 771 MX6_IOM_DRAM_DQM0, 0x00020030,
 772 MX6_IOM_DRAM_DQM1, 0x00020030,
 773 MX6_IOM_DRAM_DQM2, 0x00020030,
 774 MX6_IOM_DRAM_DQM3, 0x00020030,
 775 MX6_IOM_DRAM_DQM4, 0x00020030,
 776 MX6_IOM_DRAM_DQM5, 0x00020030,
 777 MX6_IOM_DRAM_DQM6, 0x00020030,
 778 MX6_IOM_DRAM_DQM7, 0x00020030,
 779
 780 MX6_IOM_DRAM_CAS, 0x00020030,
 781 MX6_IOM_DRAM_RAS, 0x00020030,
 782 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 783 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 784
 785 MX6_IOM_DRAM_RESET, 0x00020030,
 786 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 787 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 788
 789 MX6_IOM_DRAM_SDODT0, 0x00003030,
 790 MX6_IOM_DRAM_SDODT1, 0x00003030,
 791
 792 /* (differential input) */
 793 MX6_IOM_DDRMODE_CTL, 0x00020000,
 794 /* (differential input) */
 795 MX6_IOM_GRP_DDRMODE, 0x00020000,
 796 /* disable ddr pullups */
 797 MX6_IOM_GRP_DDRPKE, 0x00000000,
 798 MX6_IOM_DRAM_SDBA2, 0x00000000,
 799 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 800 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 801
 802 /* Read data DQ Byte0-3 delay */
 803 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 804 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 805 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 806 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 807 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 808 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 809 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 810 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 811
 812 /*
 813  * MDMISC       mirroring       interleaved (row/bank/col)
 814  */
 815 /* TODO: check what the RALAT field does */
 816 MX6_MMDC_P0_MDMISC, 0x00081740,
 817
 818 /*
 819  * MDSCR        con_req
 820  */
 821 MX6_MMDC_P0_MDSCR, 0x00008000,
 822
 823
 824 /* 800mhz_2x64mx16.cfg */
 825
 826 MX6_MMDC_P0_MDPDC, 0x0002002D,
 827 MX6_MMDC_P0_MDCFG0, 0x2C305503,
 828 MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
 829 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 830 MX6_MMDC_P0_MDRWD, 0x000026D2,
 831 MX6_MMDC_P0_MDOR, 0x00301023,
 832 MX6_MMDC_P0_MDOTC, 0x00333030,
 833 MX6_MMDC_P0_MDPDC, 0x0002556D,
 834 /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
 835 MX6_MMDC_P0_MDASP, 0x00000017,
 836 /* DDR3 DATA BUS SIZE: 64BIT */
 837 /* MX6_MMDC_P0_MDCTL, 0x821A0000, */
 838 /* DDR3 DATA BUS SIZE: 32BIT */
 839 MX6_MMDC_P0_MDCTL, 0x82190000,
 840
 841 /* Write commands to DDR */
 842 /* Load Mode Registers */
 843 /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
 844 /* MX6_MMDC_P0_MDSCR, 0x04408032, */
 845 MX6_MMDC_P0_MDSCR, 0x04008032,
 846 MX6_MMDC_P0_MDSCR, 0x00008033,
 847 MX6_MMDC_P0_MDSCR, 0x00048031,
 848 MX6_MMDC_P0_MDSCR, 0x13208030,
 849 /* ZQ calibration */
 850 MX6_MMDC_P0_MDSCR, 0x04008040,
 851
 852 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
 853 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
 854 MX6_MMDC_P0_MDREF, 0x00005800,
 855
 856 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
 857 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
 858
 859 MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
 860 MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
 861 MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
 862 MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
 863
 864 MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
 865 MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
 866 MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
 867 MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
 868
 869 MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
 870 MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
 871 MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
 872 MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
 873
 874 MX6_MMDC_P0_MPMUR0, 0x00000800,
 875 MX6_MMDC_P1_MPMUR0, 0x00000800,
 876 MX6_MMDC_P0_MDSCR, 0x00000000,
 877 MX6_MMDC_P0_MAPSR, 0x00011006,
 878 };
 879
 880 static int mx6dl_dcd_table[] = {
 881 /* ddr-setup.cfg */
 882
 883 MX6_IOM_DRAM_SDQS0, 0x00000030,
 884 MX6_IOM_DRAM_SDQS1, 0x00000030,
 885 MX6_IOM_DRAM_SDQS2, 0x00000030,
 886 MX6_IOM_DRAM_SDQS3, 0x00000030,
 887 MX6_IOM_DRAM_SDQS4, 0x00000030,
 888 MX6_IOM_DRAM_SDQS5, 0x00000030,
 889 MX6_IOM_DRAM_SDQS6, 0x00000030,
 890 MX6_IOM_DRAM_SDQS7, 0x00000030,
 891
 892 MX6_IOM_GRP_B0DS, 0x00000030,
 893 MX6_IOM_GRP_B1DS, 0x00000030,
 894 MX6_IOM_GRP_B2DS, 0x00000030,
 895 MX6_IOM_GRP_B3DS, 0x00000030,
 896 MX6_IOM_GRP_B4DS, 0x00000030,
 897 MX6_IOM_GRP_B5DS, 0x00000030,
 898 MX6_IOM_GRP_B6DS, 0x00000030,
 899 MX6_IOM_GRP_B7DS, 0x00000030,
 900 MX6_IOM_GRP_ADDDS, 0x00000030,
 901 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 902 MX6_IOM_GRP_CTLDS, 0x00000030,
 903
 904 MX6_IOM_DRAM_DQM0, 0x00020030,
 905 MX6_IOM_DRAM_DQM1, 0x00020030,
 906 MX6_IOM_DRAM_DQM2, 0x00020030,
 907 MX6_IOM_DRAM_DQM3, 0x00020030,
 908 MX6_IOM_DRAM_DQM4, 0x00020030,
 909 MX6_IOM_DRAM_DQM5, 0x00020030,
 910 MX6_IOM_DRAM_DQM6, 0x00020030,
 911 MX6_IOM_DRAM_DQM7, 0x00020030,
 912
 913 MX6_IOM_DRAM_CAS, 0x00020030,
 914 MX6_IOM_DRAM_RAS, 0x00020030,
 915 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 916 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 917
 918 MX6_IOM_DRAM_RESET, 0x00020030,
 919 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 920 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 921
 922 MX6_IOM_DRAM_SDODT0, 0x00003030,
 923 MX6_IOM_DRAM_SDODT1, 0x00003030,
 924
 925 /* (differential input) */
 926 MX6_IOM_DDRMODE_CTL, 0x00020000,
 927 /* (differential input) */
 928 MX6_IOM_GRP_DDRMODE, 0x00020000,
 929 /* disable ddr pullups */
 930 MX6_IOM_GRP_DDRPKE, 0x00000000,
 931 MX6_IOM_DRAM_SDBA2, 0x00000000,
 932 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 933 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 934
 935 /* Read data DQ Byte0-3 delay */
 936 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 937 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 938 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 939 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 940 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 941 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 942 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 943 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 944
 945 /*
 946  * MDMISC       mirroring       interleaved (row/bank/col)
 947  */
 948 /* TODO: check what the RALAT field does */
 949 MX6_MMDC_P0_MDMISC, 0x00081740,
 950
 951 /*
 952  * MDSCR        con_req
 953  */
 954 MX6_MMDC_P0_MDSCR, 0x00008000,
 955
 956
 957 /* 800mhz_2x64mx16.cfg */
 958
 959 MX6_MMDC_P0_MDPDC, 0x0002002D,
 960 MX6_MMDC_P0_MDCFG0, 0x2C305503,
 961 MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
 962 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 963 MX6_MMDC_P0_MDRWD, 0x000026D2,
 964 MX6_MMDC_P0_MDOR, 0x00301023,
 965 MX6_MMDC_P0_MDOTC, 0x00333030,
 966 MX6_MMDC_P0_MDPDC, 0x0002556D,
 967 /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
 968 MX6_MMDC_P0_MDASP, 0x00000017,
 969 /* DDR3 DATA BUS SIZE: 64BIT */
 970 MX6_MMDC_P0_MDCTL, 0x821A0000,
 971 /* DDR3 DATA BUS SIZE: 32BIT */
 972 /* MX6_MMDC_P0_MDCTL, 0x82190000, */
 973
 974 /* Write commands to DDR */
 975 /* Load Mode Registers */
 976 /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
 977 /* MX6_MMDC_P0_MDSCR, 0x04408032, */
 978 MX6_MMDC_P0_MDSCR, 0x04008032,
 979 MX6_MMDC_P0_MDSCR, 0x00008033,
 980 MX6_MMDC_P0_MDSCR, 0x00048031,
 981 MX6_MMDC_P0_MDSCR, 0x13208030,
 982 /* ZQ calibration */
 983 MX6_MMDC_P0_MDSCR, 0x04008040,
 984
 985 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
 986 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
 987 MX6_MMDC_P0_MDREF, 0x00005800,
 988
 989 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
 990 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
 991
 992 MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
 993 MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
 994 MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
 995 MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
 996
 997 MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
 998 MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
 999 MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
1000 MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
1001
1002 MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
1003 MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
1004 MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
1005 MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
1006
1007 MX6_MMDC_P0_MPMUR0, 0x00000800,
1008 MX6_MMDC_P1_MPMUR0, 0x00000800,
1009 MX6_MMDC_P0_MDSCR, 0x00000000,
1010 MX6_MMDC_P0_MAPSR, 0x00011006,
1011 };
1012
1013 static void ccgr_init(void)
1014 {
1015         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1016
1017         writel(0x00C03F3F, &ccm->CCGR0);
1018         writel(0x0030FC03, &ccm->CCGR1);
1019         writel(0x0FFFFFF3, &ccm->CCGR2);
1020         writel(0x3FF0300F, &ccm->CCGR3);
1021         writel(0x00FFF300, &ccm->CCGR4);
1022         writel(0x0F0000F3, &ccm->CCGR5);
1023         writel(0x000003FF, &ccm->CCGR6);
1024
1025 /*
1026  * Setup CCM_CCOSR register as follows:
1027  *
1028  * cko1_en  = 1    --> CKO1 enabled
1029  * cko1_div = 111  --> divide by 8
1030  * cko1_sel = 1011 --> ahb_clk_root
1031  *
1032  * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
1033  */
1034         writel(0x000000FB, &ccm->ccosr);
1035 }
1036
1037 static void ddr_init(int *table, int size)
1038 {
1039         int i;
1040
1041         for (i = 0; i < size / 2 ; i++)
1042                 writel(table[2 * i + 1], table[2 * i]);
1043 }
1044
1045 static void spl_dram_init(void)
1046 {
1047         int minc, maxc;
1048
1049         switch (get_cpu_temp_grade(&minc, &maxc)) {
1050         case TEMP_COMMERCIAL:
1051         case TEMP_EXTCOMMERCIAL:
1052                 if (is_cpu_type(MXC_CPU_MX6DL)) {
1053                         puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n");
1054                         ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1055                 } else {
1056                         puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
1057                         ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1058                 }
1059                 break;
1060         case TEMP_INDUSTRIAL:
1061         case TEMP_AUTOMOTIVE:
1062         default:
1063                 if (is_cpu_type(MXC_CPU_MX6DL)) {
1064                         puts("Industrial temperature grade DDR3 timings, 64bit bus width.\n");
1065                         ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1066                 } else {
1067                         puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
1068                         ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1069                 }
1070                 break;
1071         };
1072         udelay(100);
1073 }
1074
1075 static iomux_v3_cfg_t const gpio_reset_pad[] = {
1076         MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL) |
1077                                         MUX_MODE_SION
1078 #define GPIO_NRESET IMX_GPIO_NR(6, 27)
1079 };
1080
1081 #define IMX_RESET_CAUSE_POR 0x00011
1082 static void nreset_out(void)
1083 {
1084         int reset_cause = get_imx_reset_cause();
1085
1086         if (reset_cause != IMX_RESET_CAUSE_POR) {
1087                 imx_iomux_v3_setup_multiple_pads(gpio_reset_pad,
1088                                                  ARRAY_SIZE(gpio_reset_pad));
1089                 gpio_direction_output(GPIO_NRESET, 1);
1090                 udelay(100);
1091                 gpio_direction_output(GPIO_NRESET, 0);
1092         }
1093 }
1094
1095 void board_init_f(ulong dummy)
1096 {
1097         /* setup AIPS and disable watchdog */
1098         arch_cpu_init();
1099
1100         ccgr_init();
1101         gpr_init();
1102
1103         /* iomux */
1104         board_early_init_f();
1105
1106         /* setup GP timer */
1107         timer_init();
1108
1109         /* UART clocks enabled and gd valid - init serial console */
1110         preloader_console_init();
1111
1112         /* Make sure we use dte mode */
1113         setup_dtemode_uart();
1114
1115         /* DDR initialization */
1116         spl_dram_init();
1117
1118         /* Clear the BSS. */
1119         memset(__bss_start, 0, __bss_end - __bss_start);
1120
1121         /* Assert nReset_Out */
1122         nreset_out();
1123
1124         /* load/boot image from boot device */
1125         board_init_r(NULL, 0);
1126 }
1127
1128 void reset_cpu(ulong addr)
1129 {
1130 }
1131
1132 #endif /* CONFIG_SPL_BUILD */
1133
1134 static struct mxc_serial_platdata mxc_serial_plat = {
1135         .reg = (struct mxc_uart *)UART1_BASE,
1136         .use_dte = true,
1137 };
1138
1139 U_BOOT_DEVICE(mxc_serial) = {
1140         .name = "serial_mxc",
1141         .platdata = &mxc_serial_plat,
1142 };