1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014-2018
4 * Marcel Ziswiler <marcel@ziswiler.com>
10 #include <asm/arch/gp_padctrl.h>
11 #include <asm/arch/pinmux.h>
12 #include <asm/arch-tegra/ap.h>
13 #include <asm/arch-tegra/tegra.h>
18 #include <pci_tegra.h>
19 #include "../common/tdx-common.h"
21 #include "pinmux-config-apalis_t30.h"
23 DECLARE_GLOBAL_DATA_PTR;
25 #define PMU_I2C_ADDRESS 0x2D
26 #define MAX_I2C_RETRY 3
28 #ifdef CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT
29 #define PEX_PERST_N TEGRA_GPIO(S, 7) /* Apalis GPIO7 */
30 #define RESET_MOCI_CTRL TEGRA_GPIO(I, 4)
32 static int pci_reset_status;
33 #endif /* CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT */
35 int arch_misc_init(void)
37 if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
39 printf("USB recovery mode\n");
46 printf("Model: Toradex Apalis T30 %dGB\n",
47 (gd->ram_size == 0x40000000) ? 1 : 2);
52 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
53 int ft_board_setup(void *blob, bd_t *bd)
55 return ft_common_board_setup(blob, bd);
60 * Routine: pinmux_init
61 * Description: Do individual peripheral pinmux configs
63 void pinmux_init(void)
65 pinmux_config_pingrp_table(tegra3_pinmux_common,
66 ARRAY_SIZE(tegra3_pinmux_common));
68 pinmux_config_pingrp_table(unused_pins_lowpower,
69 ARRAY_SIZE(unused_pins_lowpower));
71 /* Initialize any non-default pad configs (APB_MISC_GP regs) */
72 pinmux_config_drvgrp_table(apalis_t30_padctrl,
73 ARRAY_SIZE(apalis_t30_padctrl));
76 #ifdef CONFIG_PCI_TEGRA
77 int tegra_pcie_board_init(void)
83 err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev);
85 debug("%s: Cannot find PMIC I2C chip\n", __func__);
89 /* TPS659110: VDD2_OP_REG = 1.05V */
93 err = dm_i2c_write(dev, addr, data, 1);
95 debug("failed to set VDD supply\n");
99 /* TPS659110: VDD2_REG 7.5 mV/us, ACTIVE */
103 err = dm_i2c_write(dev, addr, data, 1);
105 debug("failed to enable VDD supply\n");
109 /* TPS659110: LDO6_REG = 1.1V, ACTIVE */
113 err = dm_i2c_write(dev, addr, data, 1);
115 debug("failed to set AVDD supply\n");
119 #ifdef CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT
120 gpio_request(PEX_PERST_N, "PEX_PERST_N");
121 gpio_request(RESET_MOCI_CTRL, "RESET_MOCI_CTRL");
122 #endif /* CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT */
127 void tegra_pcie_board_port_reset(struct tegra_pcie_port *port)
129 int index = tegra_pcie_port_index_of_port(port);
131 if (index == 2) { /* I210 Gigabit Ethernet Controller (On-module) */
132 tegra_pcie_port_reset(port);
134 #ifdef CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT
136 * Apalis PCIe aka port 1 and Apalis Type Specific 4 Lane PCIe aka port
137 * 0 share the same RESET_MOCI therefore only assert it once for both
138 * ports to avoid losing the previously brought up port again.
140 else if ((index == 1) || (index == 0)) {
141 /* only do it once per init cycle */
142 if (pci_reset_status % 2 == 0) {
144 * Reset PLX PEX 8605 PCIe Switch plus PCIe devices on
145 * Apalis Evaluation Board
147 gpio_direction_output(PEX_PERST_N, 0);
148 gpio_direction_output(RESET_MOCI_CTRL, 0);
151 * Must be asserted for 100 ms after power and clocks
156 gpio_set_value(PEX_PERST_N, 1);
158 * Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not
159 * Guaranteed Until 900 us After PEX_PERST# De-assertion
162 gpio_set_value(RESET_MOCI_CTRL, 1);
166 #endif /* CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT */
168 #endif /* CONFIG_PCI_TEGRA */
171 * Backlight off before OS handover
173 void board_preboot_os(void)
175 gpio_request(TEGRA_GPIO(V, 2), "BKL1_ON");
176 gpio_direction_output(TEGRA_GPIO(V, 2), 0);