board/toradex/apalis_imx6/apalis_imx6.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   5  * Copyright (C) 2014-2019, Toradex AG
   6  * copied from nitrogen6x
   7  */
   8
   9 #include <common.h>
  10 #include <cpu_func.h>
  11 #include <dm.h>
  12 #include <image.h>
  13 #include <init.h>
  14 #include <net.h>
  15 #include <linux/delay.h>
  16
  17 #include <ahci.h>
  18 #include <asm/arch/clock.h>
  19 #include <asm/arch/crm_regs.h>
  20 #include <asm/arch/imx-regs.h>
  21 #include <asm/arch/mx6-ddr.h>
  22 #include <asm/arch/mx6-pins.h>
  23 #include <asm/arch/mxc_hdmi.h>
  24 #include <asm/arch/sys_proto.h>
  25 #include <asm/bootm.h>
  26 #include <asm/gpio.h>
  27 #include <asm/mach-imx/boot_mode.h>
  28 #include <asm/mach-imx/iomux-v3.h>
  29 #include <asm/mach-imx/sata.h>
  30 #include <asm/mach-imx/video.h>
  31 #include <dm/device-internal.h>
  32 #include <dm/platform_data/serial_mxc.h>
  33 #include <dwc_ahsata.h>
  34 #include <env.h>
  35 #include <fsl_esdhc_imx.h>
  36 #include <imx_thermal.h>
  37 #include <micrel.h>
  38 #include <miiphy.h>
  39 #include <netdev.h>
  40
  41 #include "../common/tdx-cfg-block.h"
  42 #ifdef CONFIG_TDX_CMD_IMX_MFGR
  43 #include "pf0100.h"
  44 #endif
  45
  46 DECLARE_GLOBAL_DATA_PTR;
  47
  48 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  49         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  50         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  51
  52 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  53         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |                 \
  54         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  55
  56 #define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP |               \
  57         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  58         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  59
  60 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  61         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  62
  63 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  64         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  65         PAD_CTL_SRE_SLOW)
  66
  67 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  68         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  69         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  70
  71 #define TRISTATE        (PAD_CTL_HYS | PAD_CTL_SPEED_MED)
  72
  73 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
  74
  75 #define APALIS_IMX6_SATA_INIT_RETRIES   10
  76
  77 int dram_init(void)
  78 {
  79         /* use the DDR controllers configured size */
  80         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  81                                     (ulong)imx_ddr_size());
  82
  83         return 0;
  84 }
  85
  86 /* Apalis UART1 */
  87 iomux_v3_cfg_t const uart1_pads_dce[] = {
  88         MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  89         MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  90 };
  91 iomux_v3_cfg_t const uart1_pads_dte[] = {
  92         MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  93         MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  94 };
  95
  96 #if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
  97 /* Apalis MMC1 */
  98 iomux_v3_cfg_t const usdhc1_pads[] = {
  99         MX6_PAD_SD1_CLK__SD1_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 100         MX6_PAD_SD1_CMD__SD1_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 101         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 102         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 103         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 104         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 105         MX6_PAD_NANDF_D0__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 106         MX6_PAD_NANDF_D1__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 107         MX6_PAD_NANDF_D2__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 108         MX6_PAD_NANDF_D3__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 109         MX6_PAD_DI0_PIN4__GPIO4_IO20   | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 110 #       define GPIO_MMC_CD IMX_GPIO_NR(4, 20)
 111 };
 112
 113 /* Apalis SD1 */
 114 iomux_v3_cfg_t const usdhc2_pads[] = {
 115         MX6_PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 116         MX6_PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 117         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 118         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 119         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 120         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 121         MX6_PAD_NANDF_CS1__GPIO6_IO14  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 122 #       define GPIO_SD_CD IMX_GPIO_NR(6, 14)
 123 };
 124
 125 /* eMMC */
 126 iomux_v3_cfg_t const usdhc3_pads[] = {
 127         MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 128         MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 129         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 130         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 131         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 132         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 133         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 134         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 135         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 136         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 137         MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
 138 };
 139 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
 140
 141 int mx6_rgmii_rework(struct phy_device *phydev)
 142 {
 143         int tmp;
 144
 145         switch (ksz9xx1_phy_get_id(phydev) & MII_KSZ9x31_SILICON_REV_MASK) {
 146         case PHY_ID_KSZ9131:
 147                 /* read rxc dll control - devaddr = 0x02, register = 0x4c */
 148                 tmp = ksz9031_phy_extended_read(phydev, 0x02,
 149                                            MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
 150                                            MII_KSZ9031_MOD_DATA_NO_POST_INC);
 151                 /* disable rxdll bypass (enable 2ns skew delay on RXC) */
 152                 tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
 153                 /* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4c */
 154                 ksz9031_phy_extended_write(phydev, 0x02,
 155                                            MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
 156                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 157                                            tmp);
 158                 /* read txc dll control - devaddr = 0x02, register = 0x4d */
 159                 tmp = ksz9031_phy_extended_read(phydev, 0x02,
 160                                            MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
 161                                            MII_KSZ9031_MOD_DATA_NO_POST_INC);
 162                 /* disable rxdll bypass (enable 2ns skew delay on TXC) */
 163                 tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
 164                 /* txc data pad skew 2ns - devaddr = 0x02, register = 0x4d */
 165                 ksz9031_phy_extended_write(phydev, 0x02,
 166                                            MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
 167                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 168                                            tmp);
 169
 170                 /* control data pad skew - devaddr = 0x02, register = 0x04 */
 171                 ksz9031_phy_extended_write(phydev, 0x02,
 172                                            MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
 173                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 174                                            0x007d);
 175                 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
 176                 ksz9031_phy_extended_write(phydev, 0x02,
 177                                            MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
 178                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 179                                            0x7777);
 180                 /* tx data pad skew - devaddr = 0x02, register = 0x05 */
 181                 ksz9031_phy_extended_write(phydev, 0x02,
 182                                            MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
 183                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 184                                            0xdddd);
 185                 /* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
 186                 ksz9031_phy_extended_write(phydev, 0x02,
 187                                            MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
 188                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 189                                            0x0007);
 190                 break;
 191         case PHY_ID_KSZ9031:
 192         default:
 193                 /* control data pad skew - devaddr = 0x02, register = 0x04 */
 194                 ksz9031_phy_extended_write(phydev, 0x02,
 195                                            MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
 196                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 197                                            0x0000);
 198                 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
 199                 ksz9031_phy_extended_write(phydev, 0x02,
 200                                            MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
 201                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 202                                            0x0000);
 203                 /* tx data pad skew - devaddr = 0x02, register = 0x05 */
 204                 ksz9031_phy_extended_write(phydev, 0x02,
 205                                            MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
 206                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 207                                            0x0000);
 208                 /* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
 209                 ksz9031_phy_extended_write(phydev, 0x02,
 210                                            MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
 211                                            MII_KSZ9031_MOD_DATA_NO_POST_INC,
 212                                            0x03FF);
 213                 break;
 214         }
 215
 216         return 0;
 217 }
 218
 219 iomux_v3_cfg_t const enet_pads[] = {
 220         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 221         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 222         MX6_PAD_RGMII_TXC__RGMII_TXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 223         MX6_PAD_RGMII_TD0__RGMII_TD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 224         MX6_PAD_RGMII_TD1__RGMII_TD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 225         MX6_PAD_RGMII_TD2__RGMII_TD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 226         MX6_PAD_RGMII_TD3__RGMII_TD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 227         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 228         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 229         MX6_PAD_RGMII_RXC__RGMII_RXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 230         MX6_PAD_RGMII_RD0__RGMII_RD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 231         MX6_PAD_RGMII_RD1__RGMII_RD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 232         MX6_PAD_RGMII_RD2__RGMII_RD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 233         MX6_PAD_RGMII_RD3__RGMII_RD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 234         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 235         /* KSZ9031 PHY Reset */
 236         MX6_PAD_ENET_CRS_DV__GPIO1_IO25         | MUX_PAD_CTRL(NO_PAD_CTRL) |
 237                                                   MUX_MODE_SION,
 238 #       define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25)
 239 };
 240
 241 /* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */
 242 iomux_v3_cfg_t const gpio_pads[] = {
 243         /* Apalis GPIO1 - GPIO8 */
 244         MX6_PAD_NANDF_D4__GPIO2_IO04    | MUX_PAD_CTRL(WEAK_PULLUP) |
 245                                           MUX_MODE_SION,
 246         MX6_PAD_NANDF_D5__GPIO2_IO05    | MUX_PAD_CTRL(WEAK_PULLUP) |
 247                                           MUX_MODE_SION,
 248         MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(WEAK_PULLUP) |
 249                                           MUX_MODE_SION,
 250         MX6_PAD_NANDF_D7__GPIO2_IO07    | MUX_PAD_CTRL(WEAK_PULLUP) |
 251                                           MUX_MODE_SION,
 252         MX6_PAD_NANDF_RB0__GPIO6_IO10   | MUX_PAD_CTRL(WEAK_PULLUP) |
 253                                           MUX_MODE_SION,
 254         MX6_PAD_NANDF_WP_B__GPIO6_IO09  | MUX_PAD_CTRL(WEAK_PULLUP) |
 255                                           MUX_MODE_SION,
 256         MX6_PAD_GPIO_2__GPIO1_IO02      | MUX_PAD_CTRL(WEAK_PULLDOWN) |
 257                                           MUX_MODE_SION,
 258         MX6_PAD_GPIO_6__GPIO1_IO06      | MUX_PAD_CTRL(WEAK_PULLUP) |
 259                                           MUX_MODE_SION,
 260         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(WEAK_PULLUP) |
 261                                           MUX_MODE_SION,
 262 };
 263
 264 static void setup_iomux_gpio(void)
 265 {
 266         imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
 267 }
 268
 269 iomux_v3_cfg_t const usb_pads[] = {
 270         /* USBH_EN */
 271         MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 272 #       define GPIO_USBH_EN IMX_GPIO_NR(1, 0)
 273         /* USB_VBUS_DET */
 274         MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
 275 #       define GPIO_USB_VBUS_DET IMX_GPIO_NR(3, 28)
 276         /* USBO1_ID */
 277         MX6_PAD_ENET_RX_ER__USB_OTG_ID  | MUX_PAD_CTRL(WEAK_PULLUP),
 278         /* USBO1_EN */
 279         MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 280 #       define GPIO_USBO_EN IMX_GPIO_NR(3, 22)
 281 };
 282
 283 /*
 284  * UARTs are used in DTE mode, switch the mode on all UARTs before
 285  * any pinmuxing connects a (DCE) output to a transceiver output.
 286  */
 287 #define UCR3            0x88    /* FIFO Control Register */
 288 #define UCR3_RI         BIT(8)  /* RIDELT DTE mode */
 289 #define UCR3_DCD        BIT(9)  /* DCDDELT DTE mode */
 290 #define UFCR            0x90    /* FIFO Control Register */
 291 #define UFCR_DCEDTE     BIT(6)  /* DCE=0 */
 292
 293 static void setup_dtemode_uart(void)
 294 {
 295         setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 296         setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 297         setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
 298         setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
 299
 300         clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
 301         clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
 302         clrbits_le32((u32 *)(UART4_BASE + UCR3), UCR3_DCD | UCR3_RI);
 303         clrbits_le32((u32 *)(UART5_BASE + UCR3), UCR3_DCD | UCR3_RI);
 304 }
 305 static void setup_dcemode_uart(void)
 306 {
 307         clrbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 308         clrbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 309         clrbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
 310         clrbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
 311 }
 312
 313 static void setup_iomux_dte_uart(void)
 314 {
 315         setup_dtemode_uart();
 316         imx_iomux_v3_setup_multiple_pads(uart1_pads_dte,
 317                                          ARRAY_SIZE(uart1_pads_dte));
 318 }
 319 static void setup_iomux_dce_uart(void)
 320 {
 321         setup_dcemode_uart();
 322         imx_iomux_v3_setup_multiple_pads(uart1_pads_dce,
 323                                          ARRAY_SIZE(uart1_pads_dce));
 324 }
 325
 326 #ifdef CONFIG_USB_EHCI_MX6
 327 int board_ehci_hcd_init(int port)
 328 {
 329         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 330         return 0;
 331 }
 332 #endif
 333
 334 #if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
 335 /* use the following sequence: eMMC, MMC1, SD1 */
 336 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
 337         {USDHC3_BASE_ADDR},
 338         {USDHC1_BASE_ADDR},
 339         {USDHC2_BASE_ADDR},
 340 };
 341
 342 int board_mmc_getcd(struct mmc *mmc)
 343 {
 344         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 345         int ret = true; /* default: assume inserted */
 346
 347         switch (cfg->esdhc_base) {
 348         case USDHC1_BASE_ADDR:
 349                 gpio_request(GPIO_MMC_CD, "MMC_CD");
 350                 gpio_direction_input(GPIO_MMC_CD);
 351                 ret = !gpio_get_value(GPIO_MMC_CD);
 352                 break;
 353         case USDHC2_BASE_ADDR:
 354                 gpio_request(GPIO_MMC_CD, "SD_CD");
 355                 gpio_direction_input(GPIO_SD_CD);
 356                 ret = !gpio_get_value(GPIO_SD_CD);
 357                 break;
 358         }
 359
 360         return ret;
 361 }
 362
 363 int board_mmc_init(bd_t *bis)
 364 {
 365         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 366         unsigned reg = readl(&psrc->sbmr1) >> 11;
 367         /*
 368          * Upon reading BOOT_CFG register the following map is done:
 369          * Bit 11 and 12 of BOOT_CFG register can determine the current
 370          * mmc port
 371          * 0x1                  SD1
 372          * 0x2                  SD2
 373          * 0x3                  SD4
 374          */
 375
 376         switch (reg & 0x3) {
 377         case 0x0:
 378                 imx_iomux_v3_setup_multiple_pads(
 379                         usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 380                 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
 381                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 382                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 383                 break;
 384         case 0x1:
 385                 imx_iomux_v3_setup_multiple_pads(
 386                         usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 387                 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
 388                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 389                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 390                 break;
 391         case 0x2:
 392                 imx_iomux_v3_setup_multiple_pads(
 393                         usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 394                 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 395                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 396                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 397                 break;
 398         default:
 399                 puts("MMC boot device not available");
 400         }
 401
 402         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 403 }
 404 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
 405
 406 int board_phy_config(struct phy_device *phydev)
 407 {
 408         mx6_rgmii_rework(phydev);
 409         if (phydev->drv->config)
 410                 phydev->drv->config(phydev);
 411
 412         return 0;
 413 }
 414
 415 static iomux_v3_cfg_t const pwr_intb_pads[] = {
 416         /*
 417          * the bootrom sets the iomux to vselect, potentially connecting
 418          * two outputs. Set this back to GPIO
 419          */
 420         MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
 421 };
 422
 423 #if defined(CONFIG_VIDEO_IPUV3)
 424
 425 static iomux_v3_cfg_t const backlight_pads[] = {
 426         /* Backlight on RGB connector: J15 */
 427         MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 428                                        MUX_MODE_SION,
 429 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13)
 430         /* additional CPU pin on BKL_PWM, keep in tristate */
 431         MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE),
 432         /* Backlight PWM, used as GPIO in U-Boot */
 433         MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 434                                        MUX_MODE_SION,
 435 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10)
 436         /* buffer output enable 0: buffer enabled */
 437         MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
 438 #define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2)
 439         /* PSAVE# integrated VDAC */
 440         MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 441                                        MUX_MODE_SION,
 442 #define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31)
 443 };
 444
 445 static iomux_v3_cfg_t const rgb_pads[] = {
 446         MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
 447         MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
 448         MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
 449         MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
 450         MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
 451         MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
 452         MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
 453         MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
 454         MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
 455         MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
 456         MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
 457         MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
 458         MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
 459         MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
 460         MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
 461         MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
 462         MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
 463         MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
 464         MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
 465         MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
 466         MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
 467         MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
 468         MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 | MUX_PAD_CTRL(OUTPUT_RGB),
 469         MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 | MUX_PAD_CTRL(OUTPUT_RGB),
 470         MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 | MUX_PAD_CTRL(OUTPUT_RGB),
 471         MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 | MUX_PAD_CTRL(OUTPUT_RGB),
 472         MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 | MUX_PAD_CTRL(OUTPUT_RGB),
 473         MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 | MUX_PAD_CTRL(OUTPUT_RGB),
 474 };
 475
 476 static void do_enable_hdmi(struct display_info_t const *dev)
 477 {
 478         imx_enable_hdmi_phy();
 479 }
 480
 481 static void enable_lvds(struct display_info_t const *dev)
 482 {
 483         struct iomuxc *iomux = (struct iomuxc *)
 484                                 IOMUXC_BASE_ADDR;
 485         u32 reg = readl(&iomux->gpr[2]);
 486         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 487         writel(reg, &iomux->gpr[2]);
 488         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 489         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 490         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 491 }
 492
 493 static void enable_rgb(struct display_info_t const *dev)
 494 {
 495         imx_iomux_v3_setup_multiple_pads(
 496                 rgb_pads,
 497                 ARRAY_SIZE(rgb_pads));
 498         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 499         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 500         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 501 }
 502
 503 static int detect_default(struct display_info_t const *dev)
 504 {
 505         (void) dev;
 506         return 1;
 507 }
 508
 509 struct display_info_t const displays[] = {{
 510         .bus    = -1,
 511         .addr   = 0,
 512         .pixfmt = IPU_PIX_FMT_RGB24,
 513         .detect = detect_hdmi,
 514         .enable = do_enable_hdmi,
 515         .mode   = {
 516                 .name           = "HDMI",
 517                 .refresh        = 60,
 518                 .xres           = 1024,
 519                 .yres           = 768,
 520                 .pixclock       = 15385,
 521                 .left_margin    = 220,
 522                 .right_margin   = 40,
 523                 .upper_margin   = 21,
 524                 .lower_margin   = 7,
 525                 .hsync_len      = 60,
 526                 .vsync_len      = 10,
 527                 .sync           = FB_SYNC_EXT,
 528                 .vmode          = FB_VMODE_NONINTERLACED
 529 } }, {
 530         .bus    = -1,
 531         .addr   = 0,
 532         .di     = 1,
 533         .pixfmt = IPU_PIX_FMT_RGB24,
 534         .detect = detect_default,
 535         .enable = enable_rgb,
 536         .mode   = {
 537                 .name           = "vga-rgb",
 538                 .refresh        = 60,
 539                 .xres           = 640,
 540                 .yres           = 480,
 541                 .pixclock       = 33000,
 542                 .left_margin    = 48,
 543                 .right_margin   = 16,
 544                 .upper_margin   = 31,
 545                 .lower_margin   = 11,
 546                 .hsync_len      = 96,
 547                 .vsync_len      = 2,
 548                 .sync           = 0,
 549                 .vmode          = FB_VMODE_NONINTERLACED
 550 } }, {
 551         .bus    = -1,
 552         .addr   = 0,
 553         .di     = 1,
 554         .pixfmt = IPU_PIX_FMT_RGB24,
 555         .enable = enable_rgb,
 556         .mode   = {
 557                 .name           = "wvga-rgb",
 558                 .refresh        = 60,
 559                 .xres           = 800,
 560                 .yres           = 480,
 561                 .pixclock       = 25000,
 562                 .left_margin    = 40,
 563                 .right_margin   = 88,
 564                 .upper_margin   = 33,
 565                 .lower_margin   = 10,
 566                 .hsync_len      = 128,
 567                 .vsync_len      = 2,
 568                 .sync           = 0,
 569                 .vmode          = FB_VMODE_NONINTERLACED
 570 } }, {
 571         .bus    = -1,
 572         .addr   = 0,
 573         .pixfmt = IPU_PIX_FMT_LVDS666,
 574         .enable = enable_lvds,
 575         .mode   = {
 576                 .name           = "wsvga-lvds",
 577                 .refresh        = 60,
 578                 .xres           = 1024,
 579                 .yres           = 600,
 580                 .pixclock       = 15385,
 581                 .left_margin    = 220,
 582                 .right_margin   = 40,
 583                 .upper_margin   = 21,
 584                 .lower_margin   = 7,
 585                 .hsync_len      = 60,
 586                 .vsync_len      = 10,
 587                 .sync           = FB_SYNC_EXT,
 588                 .vmode          = FB_VMODE_NONINTERLACED
 589 } } };
 590 size_t display_count = ARRAY_SIZE(displays);
 591
 592 static void setup_display(void)
 593 {
 594         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 595         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 596         int reg;
 597
 598         enable_ipu_clock();
 599         imx_setup_hdmi();
 600         /* Turn on LDB0,IPU,IPU DI0 clocks */
 601         reg = __raw_readl(&mxc_ccm->CCGR3);
 602         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 603         writel(reg, &mxc_ccm->CCGR3);
 604
 605         /* set LDB0, LDB1 clk select to 011/011 */
 606         reg = readl(&mxc_ccm->cs2cdr);
 607         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 608                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 609         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 610               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 611         writel(reg, &mxc_ccm->cs2cdr);
 612
 613         reg = readl(&mxc_ccm->cscmr2);
 614         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 615         writel(reg, &mxc_ccm->cscmr2);
 616
 617         reg = readl(&mxc_ccm->chsccdr);
 618         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 619                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 620         writel(reg, &mxc_ccm->chsccdr);
 621
 622         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 623              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 624              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 625              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 626              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 627              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 628              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 629              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 630              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 631         writel(reg, &iomux->gpr[2]);
 632
 633         reg = readl(&iomux->gpr[3]);
 634         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 635                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 636             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 637                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 638         writel(reg, &iomux->gpr[3]);
 639
 640         /* backlight unconditionally on for now */
 641         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 642                                          ARRAY_SIZE(backlight_pads));
 643         /* use 0 for EDT 7", use 1 for LG fullHD panel */
 644         gpio_request(RGB_BACKLIGHTPWM_GP, "BKL1_PWM");
 645         gpio_request(RGB_BACKLIGHTPWM_OE, "BKL1_PWM_EN");
 646         gpio_request(RGB_BACKLIGHT_GP, "BKL1_ON");
 647         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 648         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 649         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 650 }
 651
 652 /*
 653  * Backlight off before OS handover
 654  */
 655 void board_preboot_os(void)
 656 {
 657         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
 658         gpio_direction_output(RGB_BACKLIGHT_GP, 0);
 659 }
 660 #endif /* defined(CONFIG_VIDEO_IPUV3) */
 661
 662 int board_early_init_f(void)
 663 {
 664         imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
 665                                          ARRAY_SIZE(pwr_intb_pads));
 666 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
 667         setup_iomux_dte_uart();
 668 #else
 669         setup_iomux_dce_uart();
 670 #endif
 671         return 0;
 672 }
 673
 674 /*
 675  * Do not overwrite the console
 676  * Use always serial for U-Boot console
 677  */
 678 int overwrite_console(void)
 679 {
 680         return 1;
 681 }
 682
 683 int board_init(void)
 684 {
 685         /* address of boot parameters */
 686         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 687
 688 #if defined(CONFIG_VIDEO_IPUV3)
 689         setup_display();
 690 #endif
 691
 692 #ifdef CONFIG_TDX_CMD_IMX_MFGR
 693         (void) pmic_init();
 694 #endif
 695
 696 #ifdef CONFIG_SATA
 697         setup_sata();
 698 #endif
 699
 700         setup_iomux_gpio();
 701
 702         return 0;
 703 }
 704
 705 #ifdef CONFIG_BOARD_LATE_INIT
 706 int board_late_init(void)
 707 {
 708 #if defined(CONFIG_REVISION_TAG) && \
 709     defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
 710         char env_str[256];
 711         u32 rev;
 712
 713         rev = get_board_rev();
 714         snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
 715         env_set("board_rev", env_str);
 716
 717 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
 718         if ((rev & 0xfff0) == 0x0100) {
 719                 char *fdt_env;
 720
 721                 /* reconfigure the UART to DCE mode dynamically if on V1.0 HW */
 722                 setup_iomux_dce_uart();
 723
 724                 /* if using the default device tree, use version for V1.0 HW */
 725                 fdt_env = env_get("fdt_file");
 726                 if ((fdt_env != NULL) && (strcmp(FDT_FILE, fdt_env) == 0)) {
 727                         env_set("fdt_file", FDT_FILE_V1_0);
 728                         printf("patching fdt_file to " FDT_FILE_V1_0 "\n");
 729 #ifndef CONFIG_ENV_IS_NOWHERE
 730                         env_save();
 731 #endif
 732                 }
 733         }
 734 #endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */
 735 #endif /* CONFIG_REVISION_TAG */
 736
 737 #ifdef CONFIG_CMD_USB_SDP
 738         if (is_boot_from_usb()) {
 739                 printf("Serial Downloader recovery mode, using sdp command\n");
 740                 env_set("bootdelay", "0");
 741                 env_set("bootcmd", "sdp 0");
 742         }
 743 #endif /* CONFIG_CMD_USB_SDP */
 744
 745         return 0;
 746 }
 747 #endif /* CONFIG_BOARD_LATE_INIT */
 748
 749 int checkboard(void)
 750 {
 751         char it[] = " IT";
 752         int minc, maxc;
 753
 754         switch (get_cpu_temp_grade(&minc, &maxc)) {
 755         case TEMP_AUTOMOTIVE:
 756         case TEMP_INDUSTRIAL:
 757                 break;
 758         case TEMP_EXTCOMMERCIAL:
 759         default:
 760                 it[0] = 0;
 761         };
 762         printf("Model: Toradex Apalis iMX6 %s %s%s\n",
 763                is_cpu_type(MXC_CPU_MX6D) ? "Dual" : "Quad",
 764                (gd->ram_size == 0x80000000) ? "2GB" :
 765                (gd->ram_size == 0x40000000) ? "1GB" : "512MB", it);
 766         return 0;
 767 }
 768
 769 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 770 int ft_board_setup(void *blob, bd_t *bd)
 771 {
 772         return ft_common_board_setup(blob, bd);
 773 }
 774 #endif
 775
 776 #ifdef CONFIG_CMD_BMODE
 777 static const struct boot_mode board_boot_modes[] = {
 778         /* 4-bit bus width */
 779         {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 780         {"sd",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 781         {NULL,  0},
 782 };
 783 #endif
 784
 785 int misc_init_r(void)
 786 {
 787 #ifdef CONFIG_CMD_BMODE
 788         add_board_boot_modes(board_boot_modes);
 789 #endif
 790         return 0;
 791 }
 792
 793 #ifdef CONFIG_LDO_BYPASS_CHECK
 794 /* TODO, use external pmic, for now always ldo_enable */
 795 void ldo_mode_set(int ldo_bypass)
 796 {
 797         return;
 798 }
 799 #endif
 800
 801 #ifdef CONFIG_SPL_BUILD
 802 #include <spl.h>
 803 #include <linux/libfdt.h>
 804 #include "asm/arch/mx6q-ddr.h"
 805 #include "asm/arch/iomux.h"
 806 #include "asm/arch/crm_regs.h"
 807
 808 static int mx6_com_dcd_table[] = {
 809 /* ddr-setup.cfg */
 810 MX6_IOM_DRAM_SDQS0, 0x00000030,
 811 MX6_IOM_DRAM_SDQS1, 0x00000030,
 812 MX6_IOM_DRAM_SDQS2, 0x00000030,
 813 MX6_IOM_DRAM_SDQS3, 0x00000030,
 814 MX6_IOM_DRAM_SDQS4, 0x00000030,
 815 MX6_IOM_DRAM_SDQS5, 0x00000030,
 816 MX6_IOM_DRAM_SDQS6, 0x00000030,
 817 MX6_IOM_DRAM_SDQS7, 0x00000030,
 818
 819 MX6_IOM_GRP_B0DS, 0x00000030,
 820 MX6_IOM_GRP_B1DS, 0x00000030,
 821 MX6_IOM_GRP_B2DS, 0x00000030,
 822 MX6_IOM_GRP_B3DS, 0x00000030,
 823 MX6_IOM_GRP_B4DS, 0x00000030,
 824 MX6_IOM_GRP_B5DS, 0x00000030,
 825 MX6_IOM_GRP_B6DS, 0x00000030,
 826 MX6_IOM_GRP_B7DS, 0x00000030,
 827 MX6_IOM_GRP_ADDDS, 0x00000030,
 828 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 829 MX6_IOM_GRP_CTLDS, 0x00000030,
 830
 831 MX6_IOM_DRAM_DQM0, 0x00020030,
 832 MX6_IOM_DRAM_DQM1, 0x00020030,
 833 MX6_IOM_DRAM_DQM2, 0x00020030,
 834 MX6_IOM_DRAM_DQM3, 0x00020030,
 835 MX6_IOM_DRAM_DQM4, 0x00020030,
 836 MX6_IOM_DRAM_DQM5, 0x00020030,
 837 MX6_IOM_DRAM_DQM6, 0x00020030,
 838 MX6_IOM_DRAM_DQM7, 0x00020030,
 839
 840 MX6_IOM_DRAM_CAS, 0x00020030,
 841 MX6_IOM_DRAM_RAS, 0x00020030,
 842 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 843 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 844
 845 MX6_IOM_DRAM_RESET, 0x00020030,
 846 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 847 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 848
 849 MX6_IOM_DRAM_SDODT0, 0x00003030,
 850 MX6_IOM_DRAM_SDODT1, 0x00003030,
 851
 852 /* (differential input) */
 853 MX6_IOM_DDRMODE_CTL, 0x00020000,
 854 /* (differential input) */
 855 MX6_IOM_GRP_DDRMODE, 0x00020000,
 856 /* disable ddr pullups */
 857 MX6_IOM_GRP_DDRPKE, 0x00000000,
 858 MX6_IOM_DRAM_SDBA2, 0x00000000,
 859 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 860 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 861
 862 /* Read data DQ Byte0-3 delay */
 863 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 864 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 865 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 866 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 867 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 868 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 869 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 870 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 871
 872 /*
 873  * MDMISC       mirroring       interleaved (row/bank/col)
 874  */
 875 MX6_MMDC_P0_MDMISC, 0x00081740,
 876
 877 /*
 878  * MDSCR        con_req
 879  */
 880 MX6_MMDC_P0_MDSCR, 0x00008000,
 881
 882 /* 1066mhz_4x128mx16.cfg */
 883
 884 MX6_MMDC_P0_MDPDC, 0x00020036,
 885 MX6_MMDC_P0_MDCFG0, 0x555A7954,
 886 MX6_MMDC_P0_MDCFG1, 0xDB328F64,
 887 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 888 MX6_MMDC_P0_MDRWD, 0x000026D2,
 889 MX6_MMDC_P0_MDOR, 0x005A1023,
 890 MX6_MMDC_P0_MDOTC, 0x09555050,
 891 MX6_MMDC_P0_MDPDC, 0x00025576,
 892 MX6_MMDC_P0_MDASP, 0x00000027,
 893 MX6_MMDC_P0_MDCTL, 0x831A0000,
 894 MX6_MMDC_P0_MDSCR, 0x04088032,
 895 MX6_MMDC_P0_MDSCR, 0x00008033,
 896 MX6_MMDC_P0_MDSCR, 0x00428031,
 897 MX6_MMDC_P0_MDSCR, 0x19308030,
 898 MX6_MMDC_P0_MDSCR, 0x04008040,
 899 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
 900 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
 901 MX6_MMDC_P0_MDREF, 0x00005800,
 902 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
 903 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
 904
 905 MX6_MMDC_P0_MPDGCTRL0, 0x432A0338,
 906 MX6_MMDC_P0_MPDGCTRL1, 0x03260324,
 907 MX6_MMDC_P1_MPDGCTRL0, 0x43340344,
 908 MX6_MMDC_P1_MPDGCTRL1, 0x031E027C,
 909
 910 MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E,
 911 MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37,
 912
 913 MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C,
 914 MX6_MMDC_P1_MPWRDLCTL, 0x4336453F,
 915
 916 MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
 917 MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
 918 MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
 919 MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
 920
 921 MX6_MMDC_P0_MPMUR0, 0x00000800,
 922 MX6_MMDC_P1_MPMUR0, 0x00000800,
 923 MX6_MMDC_P0_MDSCR, 0x00000000,
 924 MX6_MMDC_P0_MAPSR, 0x00011006,
 925 };
 926
 927 static int mx6_it_dcd_table[] = {
 928 /* ddr-setup.cfg */
 929 MX6_IOM_DRAM_SDQS0, 0x00000030,
 930 MX6_IOM_DRAM_SDQS1, 0x00000030,
 931 MX6_IOM_DRAM_SDQS2, 0x00000030,
 932 MX6_IOM_DRAM_SDQS3, 0x00000030,
 933 MX6_IOM_DRAM_SDQS4, 0x00000030,
 934 MX6_IOM_DRAM_SDQS5, 0x00000030,
 935 MX6_IOM_DRAM_SDQS6, 0x00000030,
 936 MX6_IOM_DRAM_SDQS7, 0x00000030,
 937
 938 MX6_IOM_GRP_B0DS, 0x00000030,
 939 MX6_IOM_GRP_B1DS, 0x00000030,
 940 MX6_IOM_GRP_B2DS, 0x00000030,
 941 MX6_IOM_GRP_B3DS, 0x00000030,
 942 MX6_IOM_GRP_B4DS, 0x00000030,
 943 MX6_IOM_GRP_B5DS, 0x00000030,
 944 MX6_IOM_GRP_B6DS, 0x00000030,
 945 MX6_IOM_GRP_B7DS, 0x00000030,
 946 MX6_IOM_GRP_ADDDS, 0x00000030,
 947 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 948 MX6_IOM_GRP_CTLDS, 0x00000030,
 949
 950 MX6_IOM_DRAM_DQM0, 0x00020030,
 951 MX6_IOM_DRAM_DQM1, 0x00020030,
 952 MX6_IOM_DRAM_DQM2, 0x00020030,
 953 MX6_IOM_DRAM_DQM3, 0x00020030,
 954 MX6_IOM_DRAM_DQM4, 0x00020030,
 955 MX6_IOM_DRAM_DQM5, 0x00020030,
 956 MX6_IOM_DRAM_DQM6, 0x00020030,
 957 MX6_IOM_DRAM_DQM7, 0x00020030,
 958
 959 MX6_IOM_DRAM_CAS, 0x00020030,
 960 MX6_IOM_DRAM_RAS, 0x00020030,
 961 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 962 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 963
 964 MX6_IOM_DRAM_RESET, 0x00020030,
 965 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 966 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 967
 968 MX6_IOM_DRAM_SDODT0, 0x00003030,
 969 MX6_IOM_DRAM_SDODT1, 0x00003030,
 970
 971 /* (differential input) */
 972 MX6_IOM_DDRMODE_CTL, 0x00020000,
 973 /* (differential input) */
 974 MX6_IOM_GRP_DDRMODE, 0x00020000,
 975 /* disable ddr pullups */
 976 MX6_IOM_GRP_DDRPKE, 0x00000000,
 977 MX6_IOM_DRAM_SDBA2, 0x00000000,
 978 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 979 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 980
 981 /* Read data DQ Byte0-3 delay */
 982 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 983 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 984 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 985 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 986 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 987 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 988 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 989 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 990
 991 /*
 992  * MDMISC       mirroring       interleaved (row/bank/col)
 993  */
 994 MX6_MMDC_P0_MDMISC, 0x00081740,
 995
 996 /*
 997  * MDSCR        con_req
 998  */
 999 MX6_MMDC_P0_MDSCR, 0x00008000,
1000
1001 /* 1066mhz_4x256mx16.cfg */
1002
1003 MX6_MMDC_P0_MDPDC, 0x00020036,
1004 MX6_MMDC_P0_MDCFG0, 0x898E78f5,
1005 MX6_MMDC_P0_MDCFG1, 0xff328f64,
1006 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
1007 MX6_MMDC_P0_MDRWD, 0x000026D2,
1008 MX6_MMDC_P0_MDOR, 0x008E1023,
1009 MX6_MMDC_P0_MDOTC, 0x09444040,
1010 MX6_MMDC_P0_MDPDC, 0x00025576,
1011 MX6_MMDC_P0_MDASP, 0x00000047,
1012 MX6_MMDC_P0_MDCTL, 0x841A0000,
1013 MX6_MMDC_P0_MDSCR, 0x02888032,
1014 MX6_MMDC_P0_MDSCR, 0x00008033,
1015 MX6_MMDC_P0_MDSCR, 0x00048031,
1016 MX6_MMDC_P0_MDSCR, 0x19408030,
1017 MX6_MMDC_P0_MDSCR, 0x04008040,
1018 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
1019 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
1020 MX6_MMDC_P0_MDREF, 0x00007800,
1021 MX6_MMDC_P0_MPODTCTRL, 0x00022227,
1022 MX6_MMDC_P1_MPODTCTRL, 0x00022227,
1023
1024 MX6_MMDC_P0_MPDGCTRL0, 0x03300338,
1025 MX6_MMDC_P0_MPDGCTRL1, 0x03240324,
1026 MX6_MMDC_P1_MPDGCTRL0, 0x03440350,
1027 MX6_MMDC_P1_MPDGCTRL1, 0x032C0308,
1028
1029 MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E,
1030 MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46,
1031
1032 MX6_MMDC_P0_MPWRDLCTL, 0x403E463E,
1033 MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46,
1034
1035 MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
1036 MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
1037 MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
1038 MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
1039
1040 MX6_MMDC_P0_MPMUR0, 0x00000800,
1041 MX6_MMDC_P1_MPMUR0, 0x00000800,
1042 MX6_MMDC_P0_MDSCR, 0x00000000,
1043 MX6_MMDC_P0_MAPSR, 0x00011006,
1044 };
1045
1046 static void ccgr_init(void)
1047 {
1048         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1049
1050         writel(0x00C03F3F, &ccm->CCGR0);
1051         writel(0x0030FC03, &ccm->CCGR1);
1052         writel(0x0FFFFFF3, &ccm->CCGR2);
1053         writel(0x3FF0300F, &ccm->CCGR3);
1054         writel(0x00FFF300, &ccm->CCGR4);
1055         writel(0x0F0000F3, &ccm->CCGR5);
1056         writel(0x000003FF, &ccm->CCGR6);
1057
1058 /*
1059  * Setup CCM_CCOSR register as follows:
1060  *
1061  * cko1_en  = 1    --> CKO1 enabled
1062  * cko1_div = 111  --> divide by 8
1063  * cko1_sel = 1011 --> ahb_clk_root
1064  *
1065  * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
1066  */
1067         writel(0x000000FB, &ccm->ccosr);
1068 }
1069
1070 static void ddr_init(int *table, int size)
1071 {
1072         int i;
1073
1074         for (i = 0; i < size / 2 ; i++)
1075                 writel(table[2 * i + 1], table[2 * i]);
1076 }
1077
1078 static void spl_dram_init(void)
1079 {
1080         int minc, maxc;
1081
1082         switch (get_cpu_temp_grade(&minc, &maxc)) {
1083         case TEMP_COMMERCIAL:
1084         case TEMP_EXTCOMMERCIAL:
1085                 puts("Commercial temperature grade DDR3 timings.\n");
1086                 ddr_init(mx6_com_dcd_table, ARRAY_SIZE(mx6_com_dcd_table));
1087                 break;
1088         case TEMP_INDUSTRIAL:
1089         case TEMP_AUTOMOTIVE:
1090         default:
1091                 puts("Industrial temperature grade DDR3 timings.\n");
1092                 ddr_init(mx6_it_dcd_table, ARRAY_SIZE(mx6_it_dcd_table));
1093                 break;
1094         };
1095         udelay(100);
1096 }
1097
1098 void board_init_f(ulong dummy)
1099 {
1100         /* setup AIPS and disable watchdog */
1101         arch_cpu_init();
1102
1103         ccgr_init();
1104         gpr_init();
1105
1106         /* iomux */
1107         board_early_init_f();
1108
1109         /* setup GP timer */
1110         timer_init();
1111
1112         /* UART clocks enabled and gd valid - init serial console */
1113         preloader_console_init();
1114
1115 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
1116         /* Make sure we use dte mode */
1117         setup_dtemode_uart();
1118 #endif
1119
1120         /* DDR initialization */
1121         spl_dram_init();
1122
1123         /* Clear the BSS. */
1124         memset(__bss_start, 0, __bss_end - __bss_start);
1125
1126         /* load/boot image from boot device */
1127         board_init_r(NULL, 0);
1128 }
1129
1130 #ifdef CONFIG_SPL_LOAD_FIT
1131 int board_fit_config_name_match(const char *name)
1132 {
1133         if (!strcmp(name, "imx6-apalis"))
1134                 return 0;
1135
1136         return -1;
1137 }
1138 #endif
1139
1140 void reset_cpu(ulong addr)
1141 {
1142 }
1143
1144 #endif /* CONFIG_SPL_BUILD */
1145
1146 static struct mxc_serial_platdata mxc_serial_plat = {
1147         .reg = (struct mxc_uart *)UART1_BASE,
1148         .use_dte = true,
1149 };
1150
1151 U_BOOT_DEVICE(mxc_serial) = {
1152         .name = "serial_mxc",
1153         .platdata = &mxc_serial_plat,
1154 };