board/toradex/apalis_imx6/apalis_imx6.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   5  * Copyright (C) 2014-2019, Toradex AG
   6  * copied from nitrogen6x
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/crm_regs.h>
  14 #include <asm/arch/imx-regs.h>
  15 #include <asm/arch/mx6-ddr.h>
  16 #include <asm/arch/mx6-pins.h>
  17 #include <asm/arch/mxc_hdmi.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/bootm.h>
  20 #include <asm/gpio.h>
  21 #include <asm/mach-imx/boot_mode.h>
  22 #include <asm/mach-imx/iomux-v3.h>
  23 #include <asm/mach-imx/mxc_i2c.h>
  24 #include <asm/mach-imx/sata.h>
  25 #include <asm/mach-imx/video.h>
  26 #include <dm/platform_data/serial_mxc.h>
  27 #include <environment.h>
  28 #include <fsl_esdhc.h>
  29 #include <i2c.h>
  30 #include <imx_thermal.h>
  31 #include <micrel.h>
  32 #include <miiphy.h>
  33 #include <netdev.h>
  34
  35 #include "../common/tdx-cfg-block.h"
  36 #ifdef CONFIG_TDX_CMD_IMX_MFGR
  37 #include "pf0100.h"
  38 #endif
  39
  40 DECLARE_GLOBAL_DATA_PTR;
  41
  42 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  43         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  44         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  45
  46 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  47         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  48         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  49
  50 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  51         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  52
  53 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |         \
  54         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  55
  56 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |                  \
  57         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  58
  59 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  60         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  61         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  62
  63 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  64         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  65         PAD_CTL_SRE_SLOW)
  66
  67 #define NO_PULLUP       (                                       \
  68         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  69         PAD_CTL_SRE_SLOW)
  70
  71 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  72         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  73         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  74
  75 #define TRISTATE        (PAD_CTL_HYS | PAD_CTL_SPEED_MED)
  76
  77 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
  78
  79 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
  80
  81 int dram_init(void)
  82 {
  83         /* use the DDR controllers configured size */
  84         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  85                                     (ulong)imx_ddr_size());
  86
  87         return 0;
  88 }
  89
  90 /* Apalis UART1 */
  91 iomux_v3_cfg_t const uart1_pads_dce[] = {
  92         MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  93         MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  94 };
  95 iomux_v3_cfg_t const uart1_pads_dte[] = {
  96         MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  97         MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  98 };
  99
 100 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 101 /* Apalis I2C1 */
 102 struct i2c_pads_info i2c_pad_info1 = {
 103         .scl = {
 104                 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
 105                 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
 106                 .gp = IMX_GPIO_NR(5, 27)
 107         },
 108         .sda = {
 109                 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
 110                 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
 111                 .gp = IMX_GPIO_NR(5, 26)
 112         }
 113 };
 114
 115 /* Apalis local, PMIC, SGTL5000, STMPE811 */
 116 struct i2c_pads_info i2c_pad_info_loc = {
 117         .scl = {
 118                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
 119                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
 120                 .gp = IMX_GPIO_NR(4, 12)
 121         },
 122         .sda = {
 123                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
 124                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 125                 .gp = IMX_GPIO_NR(4, 13)
 126         }
 127 };
 128
 129 /* Apalis I2C3 / CAM */
 130 struct i2c_pads_info i2c_pad_info3 = {
 131         .scl = {
 132                 .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
 133                 .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
 134                 .gp = IMX_GPIO_NR(3, 17)
 135         },
 136         .sda = {
 137                 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
 138                 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
 139                 .gp = IMX_GPIO_NR(3, 18)
 140         }
 141 };
 142
 143 /* Apalis I2C2 / DDC */
 144 struct i2c_pads_info i2c_pad_info_ddc = {
 145         .scl = {
 146                 .i2c_mode = MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL | PC,
 147                 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
 148                 .gp = IMX_GPIO_NR(2, 30)
 149         },
 150         .sda = {
 151                 .i2c_mode = MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA | PC,
 152                 .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
 153                 .gp = IMX_GPIO_NR(3, 16)
 154         }
 155 };
 156
 157 /* Apalis MMC1 */
 158 iomux_v3_cfg_t const usdhc1_pads[] = {
 159         MX6_PAD_SD1_CLK__SD1_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 160         MX6_PAD_SD1_CMD__SD1_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 161         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 162         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 163         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 164         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 165         MX6_PAD_NANDF_D0__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 166         MX6_PAD_NANDF_D1__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 167         MX6_PAD_NANDF_D2__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 168         MX6_PAD_NANDF_D3__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 169         MX6_PAD_DI0_PIN4__GPIO4_IO20   | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 170 #       define GPIO_MMC_CD IMX_GPIO_NR(4, 20)
 171 };
 172
 173 /* Apalis SD1 */
 174 iomux_v3_cfg_t const usdhc2_pads[] = {
 175         MX6_PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 176         MX6_PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 177         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 178         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 179         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 180         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 181         MX6_PAD_NANDF_CS1__GPIO6_IO14  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 182 #       define GPIO_SD_CD IMX_GPIO_NR(6, 14)
 183 };
 184
 185 /* eMMC */
 186 iomux_v3_cfg_t const usdhc3_pads[] = {
 187         MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 188         MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 189         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 190         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 191         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 192         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 193         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 194         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 195         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 196         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 197         MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
 198 };
 199
 200 int mx6_rgmii_rework(struct phy_device *phydev)
 201 {
 202         /* control data pad skew - devaddr = 0x02, register = 0x04 */
 203         ksz9031_phy_extended_write(phydev, 0x02,
 204                                    MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
 205                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 206         /* rx data pad skew - devaddr = 0x02, register = 0x05 */
 207         ksz9031_phy_extended_write(phydev, 0x02,
 208                                    MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
 209                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 210         /* tx data pad skew - devaddr = 0x02, register = 0x05 */
 211         ksz9031_phy_extended_write(phydev, 0x02,
 212                                    MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
 213                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 214         /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
 215         ksz9031_phy_extended_write(phydev, 0x02,
 216                                    MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
 217                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
 218         return 0;
 219 }
 220
 221 iomux_v3_cfg_t const enet_pads[] = {
 222         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 223         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 224         MX6_PAD_RGMII_TXC__RGMII_TXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 225         MX6_PAD_RGMII_TD0__RGMII_TD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 226         MX6_PAD_RGMII_TD1__RGMII_TD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 227         MX6_PAD_RGMII_TD2__RGMII_TD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 228         MX6_PAD_RGMII_TD3__RGMII_TD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 229         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 230         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 231         MX6_PAD_RGMII_RXC__RGMII_RXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 232         MX6_PAD_RGMII_RD0__RGMII_RD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 233         MX6_PAD_RGMII_RD1__RGMII_RD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 234         MX6_PAD_RGMII_RD2__RGMII_RD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 235         MX6_PAD_RGMII_RD3__RGMII_RD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 236         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 237         /* KSZ9031 PHY Reset */
 238         MX6_PAD_ENET_CRS_DV__GPIO1_IO25         | MUX_PAD_CTRL(NO_PAD_CTRL) |
 239                                                   MUX_MODE_SION,
 240 #       define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25)
 241 };
 242
 243 static void setup_iomux_enet(void)
 244 {
 245         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 246 }
 247
 248 static int reset_enet_phy(struct mii_dev *bus)
 249 {
 250         /* Reset KSZ9031 PHY */
 251         gpio_request(GPIO_ENET_PHY_RESET, "ETH_RESET#");
 252         gpio_direction_output(GPIO_ENET_PHY_RESET, 0);
 253         mdelay(10);
 254         gpio_set_value(GPIO_ENET_PHY_RESET, 1);
 255
 256         return 0;
 257 }
 258
 259 /* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */
 260 iomux_v3_cfg_t const gpio_pads[] = {
 261         /* Apalis GPIO1 - GPIO8 */
 262         MX6_PAD_NANDF_D4__GPIO2_IO04    | MUX_PAD_CTRL(WEAK_PULLUP) |
 263                                           MUX_MODE_SION,
 264         MX6_PAD_NANDF_D5__GPIO2_IO05    | MUX_PAD_CTRL(WEAK_PULLUP) |
 265                                           MUX_MODE_SION,
 266         MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(WEAK_PULLUP) |
 267                                           MUX_MODE_SION,
 268         MX6_PAD_NANDF_D7__GPIO2_IO07    | MUX_PAD_CTRL(WEAK_PULLUP) |
 269                                           MUX_MODE_SION,
 270         MX6_PAD_NANDF_RB0__GPIO6_IO10   | MUX_PAD_CTRL(WEAK_PULLUP) |
 271                                           MUX_MODE_SION,
 272         MX6_PAD_NANDF_WP_B__GPIO6_IO09  | MUX_PAD_CTRL(WEAK_PULLUP) |
 273                                           MUX_MODE_SION,
 274         MX6_PAD_GPIO_2__GPIO1_IO02      | MUX_PAD_CTRL(WEAK_PULLDOWN) |
 275                                           MUX_MODE_SION,
 276         MX6_PAD_GPIO_6__GPIO1_IO06      | MUX_PAD_CTRL(WEAK_PULLUP) |
 277                                           MUX_MODE_SION,
 278         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(WEAK_PULLUP) |
 279                                           MUX_MODE_SION,
 280 };
 281
 282 static void setup_iomux_gpio(void)
 283 {
 284         imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
 285 }
 286
 287 iomux_v3_cfg_t const usb_pads[] = {
 288         /* USBH_EN */
 289         MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 290 #       define GPIO_USBH_EN IMX_GPIO_NR(1, 0)
 291         /* USB_VBUS_DET */
 292         MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
 293 #       define GPIO_USB_VBUS_DET IMX_GPIO_NR(3, 28)
 294         /* USBO1_ID */
 295         MX6_PAD_ENET_RX_ER__USB_OTG_ID  | MUX_PAD_CTRL(WEAK_PULLUP),
 296         /* USBO1_EN */
 297         MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 298 #       define GPIO_USBO_EN IMX_GPIO_NR(3, 22)
 299 };
 300
 301 /*
 302  * UARTs are used in DTE mode, switch the mode on all UARTs before
 303  * any pinmuxing connects a (DCE) output to a transceiver output.
 304  */
 305 #define UFCR            0x90    /* FIFO Control Register */
 306 #define UFCR_DCEDTE     (1<<6)  /* DCE=0 */
 307
 308 static void setup_dtemode_uart(void)
 309 {
 310         setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 311         setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 312         setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
 313         setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
 314 }
 315 static void setup_dcemode_uart(void)
 316 {
 317         clrbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 318         clrbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 319         clrbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
 320         clrbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
 321 }
 322
 323 static void setup_iomux_dte_uart(void)
 324 {
 325         setup_dtemode_uart();
 326         imx_iomux_v3_setup_multiple_pads(uart1_pads_dte,
 327                                          ARRAY_SIZE(uart1_pads_dte));
 328 }
 329 static void setup_iomux_dce_uart(void)
 330 {
 331         setup_dcemode_uart();
 332         imx_iomux_v3_setup_multiple_pads(uart1_pads_dce,
 333                                          ARRAY_SIZE(uart1_pads_dce));
 334 }
 335
 336 #ifdef CONFIG_USB_EHCI_MX6
 337 int board_ehci_hcd_init(int port)
 338 {
 339         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 340         return 0;
 341 }
 342
 343 int board_ehci_power(int port, int on)
 344 {
 345         switch (port) {
 346         case 0:
 347                 /* control OTG power */
 348                 gpio_direction_output(GPIO_USBO_EN, on);
 349                 mdelay(100);
 350                 break;
 351         case 1:
 352                 /* Control MXM USBH */
 353                 gpio_direction_output(GPIO_USBH_EN, on);
 354                 mdelay(2);
 355                 /* Control onboard USB Hub VBUS */
 356                 gpio_direction_output(GPIO_USB_VBUS_DET, on);
 357                 mdelay(100);
 358                 break;
 359         default:
 360                 break;
 361         }
 362         return 0;
 363 }
 364 #endif
 365
 366 #ifdef CONFIG_FSL_ESDHC
 367 /* use the following sequence: eMMC, MMC1, SD1 */
 368 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
 369         {USDHC3_BASE_ADDR},
 370         {USDHC1_BASE_ADDR},
 371         {USDHC2_BASE_ADDR},
 372 };
 373
 374 int board_mmc_getcd(struct mmc *mmc)
 375 {
 376         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 377         int ret = true; /* default: assume inserted */
 378
 379         switch (cfg->esdhc_base) {
 380         case USDHC1_BASE_ADDR:
 381                 gpio_request(GPIO_MMC_CD, "MMC_CD");
 382                 gpio_direction_input(GPIO_MMC_CD);
 383                 ret = !gpio_get_value(GPIO_MMC_CD);
 384                 break;
 385         case USDHC2_BASE_ADDR:
 386                 gpio_request(GPIO_MMC_CD, "SD_CD");
 387                 gpio_direction_input(GPIO_SD_CD);
 388                 ret = !gpio_get_value(GPIO_SD_CD);
 389                 break;
 390         }
 391
 392         return ret;
 393 }
 394
 395 int board_mmc_init(bd_t *bis)
 396 {
 397 #ifndef CONFIG_SPL_BUILD
 398         s32 status = 0;
 399         u32 index = 0;
 400
 401         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 402         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 403         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 404
 405         usdhc_cfg[0].max_bus_width = 8;
 406         usdhc_cfg[1].max_bus_width = 8;
 407         usdhc_cfg[2].max_bus_width = 4;
 408
 409         for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 410                 switch (index) {
 411                 case 0:
 412                         imx_iomux_v3_setup_multiple_pads(
 413                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 414                         break;
 415                 case 1:
 416                         imx_iomux_v3_setup_multiple_pads(
 417                                 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 418                         break;
 419                 case 2:
 420                         imx_iomux_v3_setup_multiple_pads(
 421                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 422                         break;
 423                 default:
 424                         printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n",
 425                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 426                         return status;
 427                 }
 428
 429                 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 430         }
 431
 432         return status;
 433 #else /* CONFIG_SPL_BUILD */
 434         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 435         unsigned reg = readl(&psrc->sbmr1) >> 11;
 436         /*
 437          * Upon reading BOOT_CFG register the following map is done:
 438          * Bit 11 and 12 of BOOT_CFG register can determine the current
 439          * mmc port
 440          * 0x1                  SD1
 441          * 0x2                  SD2
 442          * 0x3                  SD4
 443          */
 444
 445         switch (reg & 0x3) {
 446         case 0x0:
 447                 imx_iomux_v3_setup_multiple_pads(
 448                         usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 449                 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
 450                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 451                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 452                 break;
 453         case 0x1:
 454                 imx_iomux_v3_setup_multiple_pads(
 455                         usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 456                 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
 457                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 458                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 459                 break;
 460         case 0x2:
 461                 imx_iomux_v3_setup_multiple_pads(
 462                         usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 463                 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 464                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 465                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 466                 break;
 467         default:
 468                 puts("MMC boot device not available");
 469         }
 470
 471         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 472 #endif /* CONFIG_SPL_BUILD */
 473 }
 474 #endif /* CONFIG_FSL_ESDHC */
 475
 476 int board_phy_config(struct phy_device *phydev)
 477 {
 478         mx6_rgmii_rework(phydev);
 479         if (phydev->drv->config)
 480                 phydev->drv->config(phydev);
 481
 482         return 0;
 483 }
 484
 485 int board_eth_init(bd_t *bis)
 486 {
 487         uint32_t base = IMX_FEC_BASE;
 488         struct mii_dev *bus = NULL;
 489         struct phy_device *phydev = NULL;
 490         int ret;
 491
 492         setup_iomux_enet();
 493
 494 #ifdef CONFIG_FEC_MXC
 495         bus = fec_get_miibus(base, -1);
 496         if (!bus)
 497                 return 0;
 498
 499         bus->reset = reset_enet_phy;
 500         /* scan PHY 4,5,6,7 */
 501         phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
 502         if (!phydev) {
 503                 free(bus);
 504                 puts("no PHY found\n");
 505                 return 0;
 506         }
 507
 508         printf("using PHY at %d\n", phydev->addr);
 509         ret = fec_probe(bis, -1, base, bus, phydev);
 510         if (ret) {
 511                 printf("FEC MXC: %s:failed\n", __func__);
 512                 free(phydev);
 513                 free(bus);
 514         }
 515 #endif /* CONFIG_FEC_MXC */
 516
 517         return 0;
 518 }
 519
 520 static iomux_v3_cfg_t const pwr_intb_pads[] = {
 521         /*
 522          * the bootrom sets the iomux to vselect, potentially connecting
 523          * two outputs. Set this back to GPIO
 524          */
 525         MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
 526 };
 527
 528 #if defined(CONFIG_VIDEO_IPUV3)
 529
 530 static iomux_v3_cfg_t const backlight_pads[] = {
 531         /* Backlight on RGB connector: J15 */
 532         MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 533                                        MUX_MODE_SION,
 534 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13)
 535         /* additional CPU pin on BKL_PWM, keep in tristate */
 536         MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE),
 537         /* Backlight PWM, used as GPIO in U-Boot */
 538         MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 539                                        MUX_MODE_SION,
 540 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10)
 541         /* buffer output enable 0: buffer enabled */
 542         MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
 543 #define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2)
 544         /* PSAVE# integrated VDAC */
 545         MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 546                                        MUX_MODE_SION,
 547 #define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31)
 548 };
 549
 550 static iomux_v3_cfg_t const rgb_pads[] = {
 551         MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
 552         MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
 553         MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
 554         MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
 555         MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
 556         MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
 557         MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
 558         MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
 559         MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
 560         MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
 561         MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
 562         MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
 563         MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
 564         MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
 565         MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
 566         MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
 567         MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
 568         MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
 569         MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
 570         MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
 571         MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
 572         MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
 573         MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 | MUX_PAD_CTRL(OUTPUT_RGB),
 574         MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 | MUX_PAD_CTRL(OUTPUT_RGB),
 575         MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 | MUX_PAD_CTRL(OUTPUT_RGB),
 576         MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 | MUX_PAD_CTRL(OUTPUT_RGB),
 577         MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 | MUX_PAD_CTRL(OUTPUT_RGB),
 578         MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 | MUX_PAD_CTRL(OUTPUT_RGB),
 579 };
 580
 581 static void do_enable_hdmi(struct display_info_t const *dev)
 582 {
 583         imx_enable_hdmi_phy();
 584 }
 585
 586 static int detect_i2c(struct display_info_t const *dev)
 587 {
 588         return (0 == i2c_set_bus_num(dev->bus)) &&
 589                (0 == i2c_probe(dev->addr));
 590 }
 591
 592 static void enable_lvds(struct display_info_t const *dev)
 593 {
 594         struct iomuxc *iomux = (struct iomuxc *)
 595                                 IOMUXC_BASE_ADDR;
 596         u32 reg = readl(&iomux->gpr[2]);
 597         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 598         writel(reg, &iomux->gpr[2]);
 599         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 600         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 601         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 602 }
 603
 604 static void enable_rgb(struct display_info_t const *dev)
 605 {
 606         imx_iomux_v3_setup_multiple_pads(
 607                 rgb_pads,
 608                 ARRAY_SIZE(rgb_pads));
 609         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 610         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 611         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 612 }
 613
 614 static int detect_default(struct display_info_t const *dev)
 615 {
 616         (void) dev;
 617         return 1;
 618 }
 619
 620 struct display_info_t const displays[] = {{
 621         .bus    = -1,
 622         .addr   = 0,
 623         .pixfmt = IPU_PIX_FMT_RGB24,
 624         .detect = detect_hdmi,
 625         .enable = do_enable_hdmi,
 626         .mode   = {
 627                 .name           = "HDMI",
 628                 .refresh        = 60,
 629                 .xres           = 1024,
 630                 .yres           = 768,
 631                 .pixclock       = 15385,
 632                 .left_margin    = 220,
 633                 .right_margin   = 40,
 634                 .upper_margin   = 21,
 635                 .lower_margin   = 7,
 636                 .hsync_len      = 60,
 637                 .vsync_len      = 10,
 638                 .sync           = FB_SYNC_EXT,
 639                 .vmode          = FB_VMODE_NONINTERLACED
 640 } }, {
 641         .bus    = -1,
 642         .addr   = 0,
 643         .di     = 1,
 644         .pixfmt = IPU_PIX_FMT_RGB24,
 645         .detect = detect_default,
 646         .enable = enable_rgb,
 647         .mode   = {
 648                 .name           = "vga-rgb",
 649                 .refresh        = 60,
 650                 .xres           = 640,
 651                 .yres           = 480,
 652                 .pixclock       = 33000,
 653                 .left_margin    = 48,
 654                 .right_margin   = 16,
 655                 .upper_margin   = 31,
 656                 .lower_margin   = 11,
 657                 .hsync_len      = 96,
 658                 .vsync_len      = 2,
 659                 .sync           = 0,
 660                 .vmode          = FB_VMODE_NONINTERLACED
 661 } }, {
 662         .bus    = -1,
 663         .addr   = 0,
 664         .di     = 1,
 665         .pixfmt = IPU_PIX_FMT_RGB24,
 666         .enable = enable_rgb,
 667         .mode   = {
 668                 .name           = "wvga-rgb",
 669                 .refresh        = 60,
 670                 .xres           = 800,
 671                 .yres           = 480,
 672                 .pixclock       = 25000,
 673                 .left_margin    = 40,
 674                 .right_margin   = 88,
 675                 .upper_margin   = 33,
 676                 .lower_margin   = 10,
 677                 .hsync_len      = 128,
 678                 .vsync_len      = 2,
 679                 .sync           = 0,
 680                 .vmode          = FB_VMODE_NONINTERLACED
 681 } }, {
 682         .bus    = -1,
 683         .addr   = 0,
 684         .pixfmt = IPU_PIX_FMT_LVDS666,
 685         .detect = detect_i2c,
 686         .enable = enable_lvds,
 687         .mode   = {
 688                 .name           = "wsvga-lvds",
 689                 .refresh        = 60,
 690                 .xres           = 1024,
 691                 .yres           = 600,
 692                 .pixclock       = 15385,
 693                 .left_margin    = 220,
 694                 .right_margin   = 40,
 695                 .upper_margin   = 21,
 696                 .lower_margin   = 7,
 697                 .hsync_len      = 60,
 698                 .vsync_len      = 10,
 699                 .sync           = FB_SYNC_EXT,
 700                 .vmode          = FB_VMODE_NONINTERLACED
 701 } } };
 702 size_t display_count = ARRAY_SIZE(displays);
 703
 704 static void setup_display(void)
 705 {
 706         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 707         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 708         int reg;
 709
 710         enable_ipu_clock();
 711         imx_setup_hdmi();
 712         /* Turn on LDB0,IPU,IPU DI0 clocks */
 713         reg = __raw_readl(&mxc_ccm->CCGR3);
 714         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 715         writel(reg, &mxc_ccm->CCGR3);
 716
 717         /* set LDB0, LDB1 clk select to 011/011 */
 718         reg = readl(&mxc_ccm->cs2cdr);
 719         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 720                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 721         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 722               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 723         writel(reg, &mxc_ccm->cs2cdr);
 724
 725         reg = readl(&mxc_ccm->cscmr2);
 726         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 727         writel(reg, &mxc_ccm->cscmr2);
 728
 729         reg = readl(&mxc_ccm->chsccdr);
 730         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 731                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 732         writel(reg, &mxc_ccm->chsccdr);
 733
 734         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 735              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 736              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 737              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 738              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 739              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 740              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 741              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 742              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 743         writel(reg, &iomux->gpr[2]);
 744
 745         reg = readl(&iomux->gpr[3]);
 746         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 747                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 748             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 749                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 750         writel(reg, &iomux->gpr[3]);
 751
 752         /* backlight unconditionally on for now */
 753         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 754                                          ARRAY_SIZE(backlight_pads));
 755         /* use 0 for EDT 7", use 1 for LG fullHD panel */
 756         gpio_request(RGB_BACKLIGHTPWM_GP, "BKL1_PWM");
 757         gpio_request(RGB_BACKLIGHTPWM_OE, "BKL1_PWM_EN");
 758         gpio_request(RGB_BACKLIGHT_GP, "BKL1_ON");
 759         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 760         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 761         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 762 }
 763
 764 /*
 765  * Backlight off before OS handover
 766  */
 767 void board_preboot_os(void)
 768 {
 769         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
 770         gpio_direction_output(RGB_BACKLIGHT_GP, 0);
 771 }
 772 #endif /* defined(CONFIG_VIDEO_IPUV3) */
 773
 774 int board_early_init_f(void)
 775 {
 776         imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
 777                                          ARRAY_SIZE(pwr_intb_pads));
 778 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
 779         setup_iomux_dte_uart();
 780 #else
 781         setup_iomux_dce_uart();
 782 #endif
 783         return 0;
 784 }
 785
 786 /*
 787  * Do not overwrite the console
 788  * Use always serial for U-Boot console
 789  */
 790 int overwrite_console(void)
 791 {
 792         return 1;
 793 }
 794
 795 int board_init(void)
 796 {
 797         /* address of boot parameters */
 798         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 799
 800         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 801         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc);
 802         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
 803
 804 #if defined(CONFIG_VIDEO_IPUV3)
 805         setup_display();
 806 #endif
 807
 808 #ifdef CONFIG_TDX_CMD_IMX_MFGR
 809         (void) pmic_init();
 810 #endif
 811
 812 #ifdef CONFIG_SATA
 813         setup_sata();
 814 #endif
 815
 816         setup_iomux_gpio();
 817
 818         return 0;
 819 }
 820
 821 #ifdef CONFIG_BOARD_LATE_INIT
 822 int board_late_init(void)
 823 {
 824 #if defined(CONFIG_REVISION_TAG) && \
 825     defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
 826         char env_str[256];
 827         u32 rev;
 828
 829         rev = get_board_rev();
 830         snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
 831         env_set("board_rev", env_str);
 832
 833 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
 834         if ((rev & 0xfff0) == 0x0100) {
 835                 char *fdt_env;
 836
 837                 /* reconfigure the UART to DCE mode dynamically if on V1.0 HW */
 838                 setup_iomux_dce_uart();
 839
 840                 /* if using the default device tree, use version for V1.0 HW */
 841                 fdt_env = env_get("fdt_file");
 842                 if ((fdt_env != NULL) && (strcmp(FDT_FILE, fdt_env) == 0)) {
 843                         env_set("fdt_file", FDT_FILE_V1_0);
 844                         printf("patching fdt_file to " FDT_FILE_V1_0 "\n");
 845 #ifndef CONFIG_ENV_IS_NOWHERE
 846                         env_save();
 847 #endif
 848                 }
 849         }
 850 #endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */
 851 #endif /* CONFIG_REVISION_TAG */
 852
 853         return 0;
 854 }
 855 #endif /* CONFIG_BOARD_LATE_INIT */
 856
 857 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP)
 858 int ft_system_setup(void *blob, bd_t *bd)
 859 {
 860         return 0;
 861 }
 862 #endif
 863
 864 int checkboard(void)
 865 {
 866         char it[] = " IT";
 867         int minc, maxc;
 868
 869         switch (get_cpu_temp_grade(&minc, &maxc)) {
 870         case TEMP_AUTOMOTIVE:
 871         case TEMP_INDUSTRIAL:
 872                 break;
 873         case TEMP_EXTCOMMERCIAL:
 874         default:
 875                 it[0] = 0;
 876         };
 877         printf("Model: Toradex Apalis iMX6 %s %s%s\n",
 878                is_cpu_type(MXC_CPU_MX6D) ? "Dual" : "Quad",
 879                (gd->ram_size == 0x80000000) ? "2GB" :
 880                (gd->ram_size == 0x40000000) ? "1GB" : "512MB", it);
 881         return 0;
 882 }
 883
 884 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 885 int ft_board_setup(void *blob, bd_t *bd)
 886 {
 887         return ft_common_board_setup(blob, bd);
 888 }
 889 #endif
 890
 891 #ifdef CONFIG_CMD_BMODE
 892 static const struct boot_mode board_boot_modes[] = {
 893         /* 4-bit bus width */
 894         {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 895         {"sd",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 896         {NULL,  0},
 897 };
 898 #endif
 899
 900 int misc_init_r(void)
 901 {
 902 #ifdef CONFIG_CMD_BMODE
 903         add_board_boot_modes(board_boot_modes);
 904 #endif
 905         return 0;
 906 }
 907
 908 #ifdef CONFIG_LDO_BYPASS_CHECK
 909 /* TODO, use external pmic, for now always ldo_enable */
 910 void ldo_mode_set(int ldo_bypass)
 911 {
 912         return;
 913 }
 914 #endif
 915
 916 #ifdef CONFIG_SPL_BUILD
 917 #include <spl.h>
 918 #include <linux/libfdt.h>
 919 #include "asm/arch/mx6q-ddr.h"
 920 #include "asm/arch/iomux.h"
 921 #include "asm/arch/crm_regs.h"
 922
 923 static int mx6_com_dcd_table[] = {
 924 /* ddr-setup.cfg */
 925 MX6_IOM_DRAM_SDQS0, 0x00000030,
 926 MX6_IOM_DRAM_SDQS1, 0x00000030,
 927 MX6_IOM_DRAM_SDQS2, 0x00000030,
 928 MX6_IOM_DRAM_SDQS3, 0x00000030,
 929 MX6_IOM_DRAM_SDQS4, 0x00000030,
 930 MX6_IOM_DRAM_SDQS5, 0x00000030,
 931 MX6_IOM_DRAM_SDQS6, 0x00000030,
 932 MX6_IOM_DRAM_SDQS7, 0x00000030,
 933
 934 MX6_IOM_GRP_B0DS, 0x00000030,
 935 MX6_IOM_GRP_B1DS, 0x00000030,
 936 MX6_IOM_GRP_B2DS, 0x00000030,
 937 MX6_IOM_GRP_B3DS, 0x00000030,
 938 MX6_IOM_GRP_B4DS, 0x00000030,
 939 MX6_IOM_GRP_B5DS, 0x00000030,
 940 MX6_IOM_GRP_B6DS, 0x00000030,
 941 MX6_IOM_GRP_B7DS, 0x00000030,
 942 MX6_IOM_GRP_ADDDS, 0x00000030,
 943 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 944 MX6_IOM_GRP_CTLDS, 0x00000030,
 945
 946 MX6_IOM_DRAM_DQM0, 0x00020030,
 947 MX6_IOM_DRAM_DQM1, 0x00020030,
 948 MX6_IOM_DRAM_DQM2, 0x00020030,
 949 MX6_IOM_DRAM_DQM3, 0x00020030,
 950 MX6_IOM_DRAM_DQM4, 0x00020030,
 951 MX6_IOM_DRAM_DQM5, 0x00020030,
 952 MX6_IOM_DRAM_DQM6, 0x00020030,
 953 MX6_IOM_DRAM_DQM7, 0x00020030,
 954
 955 MX6_IOM_DRAM_CAS, 0x00020030,
 956 MX6_IOM_DRAM_RAS, 0x00020030,
 957 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 958 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 959
 960 MX6_IOM_DRAM_RESET, 0x00020030,
 961 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 962 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 963
 964 MX6_IOM_DRAM_SDODT0, 0x00003030,
 965 MX6_IOM_DRAM_SDODT1, 0x00003030,
 966
 967 /* (differential input) */
 968 MX6_IOM_DDRMODE_CTL, 0x00020000,
 969 /* (differential input) */
 970 MX6_IOM_GRP_DDRMODE, 0x00020000,
 971 /* disable ddr pullups */
 972 MX6_IOM_GRP_DDRPKE, 0x00000000,
 973 MX6_IOM_DRAM_SDBA2, 0x00000000,
 974 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 975 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 976
 977 /* Read data DQ Byte0-3 delay */
 978 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 979 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 980 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 981 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 982 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 983 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 984 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 985 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 986
 987 /*
 988  * MDMISC       mirroring       interleaved (row/bank/col)
 989  */
 990 MX6_MMDC_P0_MDMISC, 0x00081740,
 991
 992 /*
 993  * MDSCR        con_req
 994  */
 995 MX6_MMDC_P0_MDSCR, 0x00008000,
 996
 997 /* 1066mhz_4x128mx16.cfg */
 998
 999 MX6_MMDC_P0_MDPDC, 0x00020036,
1000 MX6_MMDC_P0_MDCFG0, 0x555A7954,
1001 MX6_MMDC_P0_MDCFG1, 0xDB328F64,
1002 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
1003 MX6_MMDC_P0_MDRWD, 0x000026D2,
1004 MX6_MMDC_P0_MDOR, 0x005A1023,
1005 MX6_MMDC_P0_MDOTC, 0x09555050,
1006 MX6_MMDC_P0_MDPDC, 0x00025576,
1007 MX6_MMDC_P0_MDASP, 0x00000027,
1008 MX6_MMDC_P0_MDCTL, 0x831A0000,
1009 MX6_MMDC_P0_MDSCR, 0x04088032,
1010 MX6_MMDC_P0_MDSCR, 0x00008033,
1011 MX6_MMDC_P0_MDSCR, 0x00428031,
1012 MX6_MMDC_P0_MDSCR, 0x19308030,
1013 MX6_MMDC_P0_MDSCR, 0x04008040,
1014 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
1015 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
1016 MX6_MMDC_P0_MDREF, 0x00005800,
1017 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
1018 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
1019
1020 MX6_MMDC_P0_MPDGCTRL0, 0x432A0338,
1021 MX6_MMDC_P0_MPDGCTRL1, 0x03260324,
1022 MX6_MMDC_P1_MPDGCTRL0, 0x43340344,
1023 MX6_MMDC_P1_MPDGCTRL1, 0x031E027C,
1024
1025 MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E,
1026 MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37,
1027
1028 MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C,
1029 MX6_MMDC_P1_MPWRDLCTL, 0x4336453F,
1030
1031 MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
1032 MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
1033 MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
1034 MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
1035
1036 MX6_MMDC_P0_MPMUR0, 0x00000800,
1037 MX6_MMDC_P1_MPMUR0, 0x00000800,
1038 MX6_MMDC_P0_MDSCR, 0x00000000,
1039 MX6_MMDC_P0_MAPSR, 0x00011006,
1040 };
1041
1042 static int mx6_it_dcd_table[] = {
1043 /* ddr-setup.cfg */
1044 MX6_IOM_DRAM_SDQS0, 0x00000030,
1045 MX6_IOM_DRAM_SDQS1, 0x00000030,
1046 MX6_IOM_DRAM_SDQS2, 0x00000030,
1047 MX6_IOM_DRAM_SDQS3, 0x00000030,
1048 MX6_IOM_DRAM_SDQS4, 0x00000030,
1049 MX6_IOM_DRAM_SDQS5, 0x00000030,
1050 MX6_IOM_DRAM_SDQS6, 0x00000030,
1051 MX6_IOM_DRAM_SDQS7, 0x00000030,
1052
1053 MX6_IOM_GRP_B0DS, 0x00000030,
1054 MX6_IOM_GRP_B1DS, 0x00000030,
1055 MX6_IOM_GRP_B2DS, 0x00000030,
1056 MX6_IOM_GRP_B3DS, 0x00000030,
1057 MX6_IOM_GRP_B4DS, 0x00000030,
1058 MX6_IOM_GRP_B5DS, 0x00000030,
1059 MX6_IOM_GRP_B6DS, 0x00000030,
1060 MX6_IOM_GRP_B7DS, 0x00000030,
1061 MX6_IOM_GRP_ADDDS, 0x00000030,
1062 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
1063 MX6_IOM_GRP_CTLDS, 0x00000030,
1064
1065 MX6_IOM_DRAM_DQM0, 0x00020030,
1066 MX6_IOM_DRAM_DQM1, 0x00020030,
1067 MX6_IOM_DRAM_DQM2, 0x00020030,
1068 MX6_IOM_DRAM_DQM3, 0x00020030,
1069 MX6_IOM_DRAM_DQM4, 0x00020030,
1070 MX6_IOM_DRAM_DQM5, 0x00020030,
1071 MX6_IOM_DRAM_DQM6, 0x00020030,
1072 MX6_IOM_DRAM_DQM7, 0x00020030,
1073
1074 MX6_IOM_DRAM_CAS, 0x00020030,
1075 MX6_IOM_DRAM_RAS, 0x00020030,
1076 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
1077 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
1078
1079 MX6_IOM_DRAM_RESET, 0x00020030,
1080 MX6_IOM_DRAM_SDCKE0, 0x00003000,
1081 MX6_IOM_DRAM_SDCKE1, 0x00003000,
1082
1083 MX6_IOM_DRAM_SDODT0, 0x00003030,
1084 MX6_IOM_DRAM_SDODT1, 0x00003030,
1085
1086 /* (differential input) */
1087 MX6_IOM_DDRMODE_CTL, 0x00020000,
1088 /* (differential input) */
1089 MX6_IOM_GRP_DDRMODE, 0x00020000,
1090 /* disable ddr pullups */
1091 MX6_IOM_GRP_DDRPKE, 0x00000000,
1092 MX6_IOM_DRAM_SDBA2, 0x00000000,
1093 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
1094 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
1095
1096 /* Read data DQ Byte0-3 delay */
1097 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
1098 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
1099 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
1100 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
1101 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
1102 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
1103 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
1104 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
1105
1106 /*
1107  * MDMISC       mirroring       interleaved (row/bank/col)
1108  */
1109 MX6_MMDC_P0_MDMISC, 0x00081740,
1110
1111 /*
1112  * MDSCR        con_req
1113  */
1114 MX6_MMDC_P0_MDSCR, 0x00008000,
1115
1116 /* 1066mhz_4x256mx16.cfg */
1117
1118 MX6_MMDC_P0_MDPDC, 0x00020036,
1119 MX6_MMDC_P0_MDCFG0, 0x898E78f5,
1120 MX6_MMDC_P0_MDCFG1, 0xff328f64,
1121 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
1122 MX6_MMDC_P0_MDRWD, 0x000026D2,
1123 MX6_MMDC_P0_MDOR, 0x008E1023,
1124 MX6_MMDC_P0_MDOTC, 0x09444040,
1125 MX6_MMDC_P0_MDPDC, 0x00025576,
1126 MX6_MMDC_P0_MDASP, 0x00000047,
1127 MX6_MMDC_P0_MDCTL, 0x841A0000,
1128 MX6_MMDC_P0_MDSCR, 0x02888032,
1129 MX6_MMDC_P0_MDSCR, 0x00008033,
1130 MX6_MMDC_P0_MDSCR, 0x00048031,
1131 MX6_MMDC_P0_MDSCR, 0x19408030,
1132 MX6_MMDC_P0_MDSCR, 0x04008040,
1133 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
1134 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
1135 MX6_MMDC_P0_MDREF, 0x00007800,
1136 MX6_MMDC_P0_MPODTCTRL, 0x00022227,
1137 MX6_MMDC_P1_MPODTCTRL, 0x00022227,
1138
1139 MX6_MMDC_P0_MPDGCTRL0, 0x03300338,
1140 MX6_MMDC_P0_MPDGCTRL1, 0x03240324,
1141 MX6_MMDC_P1_MPDGCTRL0, 0x03440350,
1142 MX6_MMDC_P1_MPDGCTRL1, 0x032C0308,
1143
1144 MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E,
1145 MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46,
1146
1147 MX6_MMDC_P0_MPWRDLCTL, 0x403E463E,
1148 MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46,
1149
1150 MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
1151 MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
1152 MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
1153 MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
1154
1155 MX6_MMDC_P0_MPMUR0, 0x00000800,
1156 MX6_MMDC_P1_MPMUR0, 0x00000800,
1157 MX6_MMDC_P0_MDSCR, 0x00000000,
1158 MX6_MMDC_P0_MAPSR, 0x00011006,
1159 };
1160
1161 static void ccgr_init(void)
1162 {
1163         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1164
1165         writel(0x00C03F3F, &ccm->CCGR0);
1166         writel(0x0030FC03, &ccm->CCGR1);
1167         writel(0x0FFFFFF3, &ccm->CCGR2);
1168         writel(0x3FF0300F, &ccm->CCGR3);
1169         writel(0x00FFF300, &ccm->CCGR4);
1170         writel(0x0F0000F3, &ccm->CCGR5);
1171         writel(0x000003FF, &ccm->CCGR6);
1172
1173 /*
1174  * Setup CCM_CCOSR register as follows:
1175  *
1176  * cko1_en  = 1    --> CKO1 enabled
1177  * cko1_div = 111  --> divide by 8
1178  * cko1_sel = 1011 --> ahb_clk_root
1179  *
1180  * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
1181  */
1182         writel(0x000000FB, &ccm->ccosr);
1183 }
1184
1185 static void ddr_init(int *table, int size)
1186 {
1187         int i;
1188
1189         for (i = 0; i < size / 2 ; i++)
1190                 writel(table[2 * i + 1], table[2 * i]);
1191 }
1192
1193 static void spl_dram_init(void)
1194 {
1195         int minc, maxc;
1196
1197         switch (get_cpu_temp_grade(&minc, &maxc)) {
1198         case TEMP_COMMERCIAL:
1199         case TEMP_EXTCOMMERCIAL:
1200                 puts("Commercial temperature grade DDR3 timings.\n");
1201                 ddr_init(mx6_com_dcd_table, ARRAY_SIZE(mx6_com_dcd_table));
1202                 break;
1203         case TEMP_INDUSTRIAL:
1204         case TEMP_AUTOMOTIVE:
1205         default:
1206                 puts("Industrial temperature grade DDR3 timings.\n");
1207                 ddr_init(mx6_it_dcd_table, ARRAY_SIZE(mx6_it_dcd_table));
1208                 break;
1209         };
1210         udelay(100);
1211 }
1212
1213 void board_init_f(ulong dummy)
1214 {
1215         /* setup AIPS and disable watchdog */
1216         arch_cpu_init();
1217
1218         ccgr_init();
1219         gpr_init();
1220
1221         /* iomux and setup of i2c */
1222         board_early_init_f();
1223
1224         /* setup GP timer */
1225         timer_init();
1226
1227         /* UART clocks enabled and gd valid - init serial console */
1228         preloader_console_init();
1229
1230 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
1231         /* Make sure we use dte mode */
1232         setup_dtemode_uart();
1233 #endif
1234
1235         /* DDR initialization */
1236         spl_dram_init();
1237
1238         /* Clear the BSS. */
1239         memset(__bss_start, 0, __bss_end - __bss_start);
1240
1241         /* load/boot image from boot device */
1242         board_init_r(NULL, 0);
1243 }
1244
1245 void reset_cpu(ulong addr)
1246 {
1247 }
1248
1249 #endif /* CONFIG_SPL_BUILD */
1250
1251 static struct mxc_serial_platdata mxc_serial_plat = {
1252         .reg = (struct mxc_uart *)UART1_BASE,
1253         .use_dte = true,
1254 };
1255
1256 U_BOOT_DEVICE(mxc_serial) = {
1257         .name = "serial_mxc",
1258         .platdata = &mxc_serial_plat,
1259 };