board/toradex/apalis_imx6/apalis_imx6.c

   1 /*
   2  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   3  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   4  * Copyright (C) 2014-2016, Toradex AG
   5  * copied from nitrogen6x
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <environment.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/crm_regs.h>
  15 #include <asm/arch/mxc_hdmi.h>
  16 #include <asm/arch/imx-regs.h>
  17 #include <asm/arch/iomux.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/arch/mx6-pins.h>
  20 #include <asm/arch/mx6-ddr.h>
  21 #include <asm/bootm.h>
  22 #include <asm/gpio.h>
  23 #include <asm/io.h>
  24 #include <asm/mach-imx/iomux-v3.h>
  25 #include <asm/mach-imx/mxc_i2c.h>
  26 #include <asm/mach-imx/sata.h>
  27 #include <asm/mach-imx/boot_mode.h>
  28 #include <asm/mach-imx/video.h>
  29 #include <dm/platform_data/serial_mxc.h>
  30 #include <dm/platdata.h>
  31 #include <fsl_esdhc.h>
  32 #include <i2c.h>
  33 #include <input.h>
  34 #include <imx_thermal.h>
  35 #include <linux/errno.h>
  36 #include <malloc.h>
  37 #include <mmc.h>
  38 #include <micrel.h>
  39 #include <miiphy.h>
  40 #include <netdev.h>
  41
  42 #include "../common/tdx-cfg-block.h"
  43 #ifdef CONFIG_TDX_CMD_IMX_MFGR
  44 #include "pf0100.h"
  45 #endif
  46
  47 DECLARE_GLOBAL_DATA_PTR;
  48
  49 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  50         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  51         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  52
  53 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  54         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  55         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  56
  57 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  58         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  59
  60 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |         \
  61         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  62
  63 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |                  \
  64         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  65
  66 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  67         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  68         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  69
  70 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  71         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  72         PAD_CTL_SRE_SLOW)
  73
  74 #define NO_PULLUP       (                                       \
  75         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  76         PAD_CTL_SRE_SLOW)
  77
  78 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  79         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  80         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  81
  82 #define TRISTATE        (PAD_CTL_HYS | PAD_CTL_SPEED_MED)
  83
  84 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
  85
  86 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
  87
  88 int dram_init(void)
  89 {
  90         /* use the DDR controllers configured size */
  91         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  92                                     (ulong)imx_ddr_size());
  93
  94         return 0;
  95 }
  96
  97 /* Apalis UART1 */
  98 iomux_v3_cfg_t const uart1_pads_dce[] = {
  99         MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 100         MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 101 };
 102 iomux_v3_cfg_t const uart1_pads_dte[] = {
 103         MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 104         MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 105 };
 106
 107 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 108 /* Apalis I2C1 */
 109 struct i2c_pads_info i2c_pad_info1 = {
 110         .scl = {
 111                 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
 112                 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
 113                 .gp = IMX_GPIO_NR(5, 27)
 114         },
 115         .sda = {
 116                 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
 117                 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
 118                 .gp = IMX_GPIO_NR(5, 26)
 119         }
 120 };
 121
 122 /* Apalis local, PMIC, SGTL5000, STMPE811 */
 123 struct i2c_pads_info i2c_pad_info_loc = {
 124         .scl = {
 125                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
 126                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
 127                 .gp = IMX_GPIO_NR(4, 12)
 128         },
 129         .sda = {
 130                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
 131                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 132                 .gp = IMX_GPIO_NR(4, 13)
 133         }
 134 };
 135
 136 /* Apalis I2C3 / CAM */
 137 struct i2c_pads_info i2c_pad_info3 = {
 138         .scl = {
 139                 .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
 140                 .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
 141                 .gp = IMX_GPIO_NR(3, 17)
 142         },
 143         .sda = {
 144                 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
 145                 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
 146                 .gp = IMX_GPIO_NR(3, 18)
 147         }
 148 };
 149
 150 /* Apalis I2C2 / DDC */
 151 struct i2c_pads_info i2c_pad_info_ddc = {
 152         .scl = {
 153                 .i2c_mode = MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL | PC,
 154                 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
 155                 .gp = IMX_GPIO_NR(2, 30)
 156         },
 157         .sda = {
 158                 .i2c_mode = MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA | PC,
 159                 .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
 160                 .gp = IMX_GPIO_NR(3, 16)
 161         }
 162 };
 163
 164 /* Apalis MMC1 */
 165 iomux_v3_cfg_t const usdhc1_pads[] = {
 166         MX6_PAD_SD1_CLK__SD1_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 167         MX6_PAD_SD1_CMD__SD1_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 168         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 169         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 170         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 171         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 172         MX6_PAD_NANDF_D0__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 173         MX6_PAD_NANDF_D1__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 174         MX6_PAD_NANDF_D2__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 175         MX6_PAD_NANDF_D3__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 176         MX6_PAD_DI0_PIN4__GPIO4_IO20   | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 177 #       define GPIO_MMC_CD IMX_GPIO_NR(4, 20)
 178 };
 179
 180 /* Apalis SD1 */
 181 iomux_v3_cfg_t const usdhc2_pads[] = {
 182         MX6_PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 183         MX6_PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 184         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 185         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 186         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 187         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 188         MX6_PAD_NANDF_CS1__GPIO6_IO14  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 189 #       define GPIO_SD_CD IMX_GPIO_NR(6, 14)
 190 };
 191
 192 /* eMMC */
 193 iomux_v3_cfg_t const usdhc3_pads[] = {
 194         MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 195         MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 196         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 197         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 198         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 199         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 200         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 201         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 202         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 203         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 204         MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP),
 205 };
 206
 207 int mx6_rgmii_rework(struct phy_device *phydev)
 208 {
 209         /* control data pad skew - devaddr = 0x02, register = 0x04 */
 210         ksz9031_phy_extended_write(phydev, 0x02,
 211                                    MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
 212                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 213         /* rx data pad skew - devaddr = 0x02, register = 0x05 */
 214         ksz9031_phy_extended_write(phydev, 0x02,
 215                                    MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
 216                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 217         /* tx data pad skew - devaddr = 0x02, register = 0x05 */
 218         ksz9031_phy_extended_write(phydev, 0x02,
 219                                    MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
 220                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 221         /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
 222         ksz9031_phy_extended_write(phydev, 0x02,
 223                                    MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
 224                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
 225         return 0;
 226 }
 227
 228 iomux_v3_cfg_t const enet_pads[] = {
 229         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 230         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 231         MX6_PAD_RGMII_TXC__RGMII_TXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 232         MX6_PAD_RGMII_TD0__RGMII_TD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 233         MX6_PAD_RGMII_TD1__RGMII_TD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 234         MX6_PAD_RGMII_TD2__RGMII_TD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 235         MX6_PAD_RGMII_TD3__RGMII_TD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 236         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 237         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 238         MX6_PAD_RGMII_RXC__RGMII_RXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 239         MX6_PAD_RGMII_RD0__RGMII_RD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 240         MX6_PAD_RGMII_RD1__RGMII_RD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 241         MX6_PAD_RGMII_RD2__RGMII_RD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 242         MX6_PAD_RGMII_RD3__RGMII_RD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 243         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 244         /* KSZ9031 PHY Reset */
 245         MX6_PAD_ENET_CRS_DV__GPIO1_IO25         | MUX_PAD_CTRL(NO_PAD_CTRL),
 246 #       define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25)
 247 };
 248
 249 static void setup_iomux_enet(void)
 250 {
 251         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 252 }
 253
 254 static int reset_enet_phy(struct mii_dev *bus)
 255 {
 256         /* Reset KSZ9031 PHY */
 257         gpio_direction_output(GPIO_ENET_PHY_RESET, 0);
 258         mdelay(10);
 259         gpio_set_value(GPIO_ENET_PHY_RESET, 1);
 260
 261         return 0;
 262 }
 263
 264 /* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */
 265 iomux_v3_cfg_t const gpio_pads[] = {
 266         /* Apalis GPIO1 - GPIO8 */
 267         MX6_PAD_NANDF_D4__GPIO2_IO04    | MUX_PAD_CTRL(WEAK_PULLUP),
 268         MX6_PAD_NANDF_D5__GPIO2_IO05    | MUX_PAD_CTRL(WEAK_PULLUP),
 269         MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(WEAK_PULLUP),
 270         MX6_PAD_NANDF_D7__GPIO2_IO07    | MUX_PAD_CTRL(WEAK_PULLUP),
 271         MX6_PAD_NANDF_RB0__GPIO6_IO10   | MUX_PAD_CTRL(WEAK_PULLUP),
 272         MX6_PAD_NANDF_WP_B__GPIO6_IO09  | MUX_PAD_CTRL(WEAK_PULLUP),
 273         MX6_PAD_GPIO_2__GPIO1_IO02      | MUX_PAD_CTRL(WEAK_PULLDOWN),
 274         MX6_PAD_GPIO_6__GPIO1_IO06      | MUX_PAD_CTRL(WEAK_PULLUP),
 275         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(WEAK_PULLUP),
 276 };
 277
 278 static void setup_iomux_gpio(void)
 279 {
 280         imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
 281 }
 282
 283 iomux_v3_cfg_t const usb_pads[] = {
 284         /* USBH_EN */
 285         MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
 286 #       define GPIO_USBH_EN IMX_GPIO_NR(1, 0)
 287         /* USB_VBUS_DET */
 288         MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
 289 #       define GPIO_USB_VBUS_DET IMX_GPIO_NR(3, 28)
 290         /* USBO1_ID */
 291         MX6_PAD_ENET_RX_ER__USB_OTG_ID  | MUX_PAD_CTRL(WEAK_PULLUP),
 292         /* USBO1_EN */
 293         MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 294 #       define GPIO_USBO_EN IMX_GPIO_NR(3, 22)
 295 };
 296
 297 /*
 298  * UARTs are used in DTE mode, switch the mode on all UARTs before
 299  * any pinmuxing connects a (DCE) output to a transceiver output.
 300  */
 301 #define UFCR            0x90    /* FIFO Control Register */
 302 #define UFCR_DCEDTE     (1<<6)  /* DCE=0 */
 303
 304 static void setup_dtemode_uart(void)
 305 {
 306         setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 307         setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 308         setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
 309         setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
 310 }
 311 static void setup_dcemode_uart(void)
 312 {
 313         clrbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 314         clrbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 315         clrbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
 316         clrbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
 317 }
 318
 319 static void setup_iomux_dte_uart(void)
 320 {
 321         setup_dtemode_uart();
 322         imx_iomux_v3_setup_multiple_pads(uart1_pads_dte,
 323                                          ARRAY_SIZE(uart1_pads_dte));
 324 }
 325
 326 static void setup_iomux_dce_uart(void)
 327 {
 328         setup_dcemode_uart();
 329         imx_iomux_v3_setup_multiple_pads(uart1_pads_dce,
 330                                          ARRAY_SIZE(uart1_pads_dce));
 331 }
 332
 333 #ifdef CONFIG_USB_EHCI_MX6
 334 int board_ehci_hcd_init(int port)
 335 {
 336         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 337         return 0;
 338 }
 339
 340 int board_ehci_power(int port, int on)
 341 {
 342         switch (port) {
 343         case 0:
 344                 /* control OTG power */
 345                 gpio_direction_output(GPIO_USBO_EN, on);
 346                 mdelay(100);
 347                 break;
 348         case 1:
 349                 /* Control MXM USBH */
 350                 gpio_direction_output(GPIO_USBH_EN, on);
 351                 mdelay(2);
 352                 /* Control onboard USB Hub VBUS */
 353                 gpio_direction_output(GPIO_USB_VBUS_DET, on);
 354                 mdelay(100);
 355                 break;
 356         default:
 357                 break;
 358         }
 359         return 0;
 360 }
 361 #endif
 362
 363 #ifdef CONFIG_FSL_ESDHC
 364 /* use the following sequence: eMMC, MMC, SD */
 365 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
 366         {USDHC3_BASE_ADDR},
 367         {USDHC1_BASE_ADDR},
 368         {USDHC2_BASE_ADDR},
 369 };
 370
 371 int board_mmc_getcd(struct mmc *mmc)
 372 {
 373         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 374         int ret = true; /* default: assume inserted */
 375
 376         switch (cfg->esdhc_base) {
 377         case USDHC1_BASE_ADDR:
 378                 gpio_direction_input(GPIO_MMC_CD);
 379                 ret = !gpio_get_value(GPIO_MMC_CD);
 380                 break;
 381         case USDHC2_BASE_ADDR:
 382                 gpio_direction_input(GPIO_SD_CD);
 383                 ret = !gpio_get_value(GPIO_SD_CD);
 384                 break;
 385         }
 386
 387         return ret;
 388 }
 389
 390 int board_mmc_init(bd_t *bis)
 391 {
 392 #ifndef CONFIG_SPL_BUILD
 393         s32 status = 0;
 394         u32 index = 0;
 395
 396         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 397         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 398         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 399
 400         usdhc_cfg[0].max_bus_width = 8;
 401         usdhc_cfg[1].max_bus_width = 8;
 402         usdhc_cfg[2].max_bus_width = 4;
 403
 404         for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 405                 switch (index) {
 406                 case 0:
 407                         imx_iomux_v3_setup_multiple_pads(
 408                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 409                         break;
 410                 case 1:
 411                         imx_iomux_v3_setup_multiple_pads(
 412                                 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 413                         break;
 414                 case 2:
 415                         imx_iomux_v3_setup_multiple_pads(
 416                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 417                         break;
 418                 default:
 419                         printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n",
 420                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 421                         return status;
 422                 }
 423
 424                 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 425         }
 426
 427         return status;
 428 #else
 429         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 430         unsigned reg = readl(&psrc->sbmr1) >> 11;
 431         /*
 432          * Upon reading BOOT_CFG register the following map is done:
 433          * Bit 11 and 12 of BOOT_CFG register can determine the current
 434          * mmc port
 435          * 0x1                  SD1
 436          * 0x2                  SD2
 437          * 0x3                  SD4
 438          */
 439
 440         switch (reg & 0x3) {
 441         case 0x0:
 442                 imx_iomux_v3_setup_multiple_pads(
 443                         usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 444                 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
 445                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 446                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 447                 break;
 448         case 0x1:
 449                 imx_iomux_v3_setup_multiple_pads(
 450                         usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 451                 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
 452                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 453                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 454                 break;
 455         case 0x2:
 456                 imx_iomux_v3_setup_multiple_pads(
 457                         usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 458                 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 459                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 460                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 461                 break;
 462         default:
 463                 puts("MMC boot device not available");
 464         }
 465
 466         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 467 #endif
 468 }
 469 #endif
 470
 471 int board_phy_config(struct phy_device *phydev)
 472 {
 473         mx6_rgmii_rework(phydev);
 474         if (phydev->drv->config)
 475                 phydev->drv->config(phydev);
 476
 477         return 0;
 478 }
 479
 480 int board_eth_init(bd_t *bis)
 481 {
 482         uint32_t base = IMX_FEC_BASE;
 483         struct mii_dev *bus = NULL;
 484         struct phy_device *phydev = NULL;
 485         int ret;
 486
 487         setup_iomux_enet();
 488
 489 #ifdef CONFIG_FEC_MXC
 490         bus = fec_get_miibus(base, -1);
 491         if (!bus)
 492                 return 0;
 493         bus->reset = reset_enet_phy;
 494         /* scan PHY 4,5,6,7 */
 495         phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
 496         if (!phydev) {
 497                 free(bus);
 498                 puts("no PHY found\n");
 499                 return 0;
 500         }
 501         printf("using PHY at %d\n", phydev->addr);
 502         ret = fec_probe(bis, -1, base, bus, phydev);
 503         if (ret) {
 504                 printf("FEC MXC: %s:failed\n", __func__);
 505                 free(phydev);
 506                 free(bus);
 507         }
 508 #endif
 509         return 0;
 510 }
 511
 512 static iomux_v3_cfg_t const pwr_intb_pads[] = {
 513         /*
 514          * the bootrom sets the iomux to vselect, potentially connecting
 515          * two outputs. Set this back to GPIO
 516          */
 517         MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
 518 };
 519
 520 #if defined(CONFIG_VIDEO_IPUV3)
 521
 522 static iomux_v3_cfg_t const backlight_pads[] = {
 523         /* Backlight on RGB connector: J15 */
 524         MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
 525 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13)
 526         /* additional CPU pin on BKL_PWM, keep in tristate */
 527         MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE),
 528         /* Backlight PWM, used as GPIO in U-Boot */
 529         MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
 530 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10)
 531         /* buffer output enable 0: buffer enabled */
 532         MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP),
 533 #define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2)
 534         /* PSAVE# integrated VDAC */
 535         MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
 536 #define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31)
 537 };
 538
 539 static iomux_v3_cfg_t const rgb_pads[] = {
 540         MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
 541         MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
 542         MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
 543         MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
 544         MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
 545         MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
 546         MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
 547         MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
 548         MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
 549         MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
 550         MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
 551         MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
 552         MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
 553         MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
 554         MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
 555         MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
 556         MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
 557         MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
 558         MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
 559         MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
 560         MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
 561         MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
 562         MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 | MUX_PAD_CTRL(OUTPUT_RGB),
 563         MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 | MUX_PAD_CTRL(OUTPUT_RGB),
 564         MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 | MUX_PAD_CTRL(OUTPUT_RGB),
 565         MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 | MUX_PAD_CTRL(OUTPUT_RGB),
 566         MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 | MUX_PAD_CTRL(OUTPUT_RGB),
 567         MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 | MUX_PAD_CTRL(OUTPUT_RGB),
 568 };
 569
 570 static void do_enable_hdmi(struct display_info_t const *dev)
 571 {
 572         imx_enable_hdmi_phy();
 573 }
 574
 575 static int detect_i2c(struct display_info_t const *dev)
 576 {
 577         return (0 == i2c_set_bus_num(dev->bus)) &&
 578                (0 == i2c_probe(dev->addr));
 579 }
 580
 581 static void enable_lvds(struct display_info_t const *dev)
 582 {
 583         struct iomuxc *iomux = (struct iomuxc *)
 584                                 IOMUXC_BASE_ADDR;
 585         u32 reg = readl(&iomux->gpr[2]);
 586         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 587         writel(reg, &iomux->gpr[2]);
 588         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 589         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 590         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 591 }
 592
 593 static void enable_rgb(struct display_info_t const *dev)
 594 {
 595         imx_iomux_v3_setup_multiple_pads(
 596                 rgb_pads,
 597                 ARRAY_SIZE(rgb_pads));
 598         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 599         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 600         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 601 }
 602
 603 static int detect_default(struct display_info_t const *dev)
 604 {
 605         (void) dev;
 606         return 1;
 607 }
 608
 609 struct display_info_t const displays[] = {{
 610         .bus    = -1,
 611         .addr   = 0,
 612         .pixfmt = IPU_PIX_FMT_RGB24,
 613         .detect = detect_hdmi,
 614         .enable = do_enable_hdmi,
 615         .mode   = {
 616                 .name           = "HDMI",
 617                 .refresh        = 60,
 618                 .xres           = 1024,
 619                 .yres           = 768,
 620                 .pixclock       = 15385,
 621                 .left_margin    = 220,
 622                 .right_margin   = 40,
 623                 .upper_margin   = 21,
 624                 .lower_margin   = 7,
 625                 .hsync_len      = 60,
 626                 .vsync_len      = 10,
 627                 .sync           = FB_SYNC_EXT,
 628                 .vmode          = FB_VMODE_NONINTERLACED
 629 } }, {
 630         .bus    = -1,
 631         .addr   = 0,
 632         .di     = 1,
 633         .pixfmt = IPU_PIX_FMT_RGB24,
 634         .detect = detect_default,
 635         .enable = enable_rgb,
 636         .mode   = {
 637                 .name           = "vga-rgb",
 638                 .refresh        = 60,
 639                 .xres           = 640,
 640                 .yres           = 480,
 641                 .pixclock       = 33000,
 642                 .left_margin    = 48,
 643                 .right_margin   = 16,
 644                 .upper_margin   = 31,
 645                 .lower_margin   = 11,
 646                 .hsync_len      = 96,
 647                 .vsync_len      = 2,
 648                 .sync           = 0,
 649                 .vmode          = FB_VMODE_NONINTERLACED
 650 } }, {
 651         .bus    = -1,
 652         .addr   = 0,
 653         .di     = 1,
 654         .pixfmt = IPU_PIX_FMT_RGB24,
 655         .enable = enable_rgb,
 656         .mode   = {
 657                 .name           = "wvga-rgb",
 658                 .refresh        = 60,
 659                 .xres           = 800,
 660                 .yres           = 480,
 661                 .pixclock       = 25000,
 662                 .left_margin    = 40,
 663                 .right_margin   = 88,
 664                 .upper_margin   = 33,
 665                 .lower_margin   = 10,
 666                 .hsync_len      = 128,
 667                 .vsync_len      = 2,
 668                 .sync           = 0,
 669                 .vmode          = FB_VMODE_NONINTERLACED
 670 } }, {
 671         .bus    = -1,
 672         .addr   = 0,
 673         .pixfmt = IPU_PIX_FMT_LVDS666,
 674         .detect = detect_i2c,
 675         .enable = enable_lvds,
 676         .mode   = {
 677                 .name           = "wsvga-lvds",
 678                 .refresh        = 60,
 679                 .xres           = 1024,
 680                 .yres           = 600,
 681                 .pixclock       = 15385,
 682                 .left_margin    = 220,
 683                 .right_margin   = 40,
 684                 .upper_margin   = 21,
 685                 .lower_margin   = 7,
 686                 .hsync_len      = 60,
 687                 .vsync_len      = 10,
 688                 .sync           = FB_SYNC_EXT,
 689                 .vmode          = FB_VMODE_NONINTERLACED
 690 } } };
 691 size_t display_count = ARRAY_SIZE(displays);
 692
 693 static void setup_display(void)
 694 {
 695         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 696         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 697         int reg;
 698
 699         enable_ipu_clock();
 700         imx_setup_hdmi();
 701         /* Turn on LDB0,IPU,IPU DI0 clocks */
 702         reg = __raw_readl(&mxc_ccm->CCGR3);
 703         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 704         writel(reg, &mxc_ccm->CCGR3);
 705
 706         /* set LDB0, LDB1 clk select to 011/011 */
 707         reg = readl(&mxc_ccm->cs2cdr);
 708         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 709                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 710         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 711               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 712         writel(reg, &mxc_ccm->cs2cdr);
 713
 714         reg = readl(&mxc_ccm->cscmr2);
 715         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 716         writel(reg, &mxc_ccm->cscmr2);
 717
 718         reg = readl(&mxc_ccm->chsccdr);
 719         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 720                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 721         writel(reg, &mxc_ccm->chsccdr);
 722
 723         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 724              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 725              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 726              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 727              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 728              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 729              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 730              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 731              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 732         writel(reg, &iomux->gpr[2]);
 733
 734         reg = readl(&iomux->gpr[3]);
 735         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 736                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 737             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 738                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 739         writel(reg, &iomux->gpr[3]);
 740
 741         /* backlight unconditionally on for now */
 742         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 743                                          ARRAY_SIZE(backlight_pads));
 744         /* use 0 for EDT 7", use 1 for LG fullHD panel */
 745         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 746         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 747         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 748 }
 749 #endif /* defined(CONFIG_VIDEO_IPUV3) */
 750
 751 int board_early_init_f(void)
 752 {
 753         imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
 754                                          ARRAY_SIZE(pwr_intb_pads));
 755 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
 756         setup_iomux_dte_uart();
 757 #else
 758         setup_iomux_dce_uart();
 759 #endif
 760         return 0;
 761 }
 762
 763 /*
 764  * Do not overwrite the console
 765  * Use always serial for U-Boot console
 766  */
 767 int overwrite_console(void)
 768 {
 769         return 1;
 770 }
 771
 772 int board_init(void)
 773 {
 774         /* address of boot parameters */
 775         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 776
 777         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 778         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc);
 779         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
 780
 781 #if defined(CONFIG_VIDEO_IPUV3)
 782         setup_display();
 783 #endif
 784
 785 #ifdef CONFIG_TDX_CMD_IMX_MFGR
 786         (void) pmic_init();
 787 #endif
 788
 789 #ifdef CONFIG_SATA
 790         setup_sata();
 791 #endif
 792
 793         setup_iomux_gpio();
 794
 795         return 0;
 796 }
 797
 798 #ifdef CONFIG_BOARD_LATE_INIT
 799 int board_late_init(void)
 800 {
 801 #if defined(CONFIG_REVISION_TAG) && \
 802     defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
 803         char env_str[256];
 804         u32 rev;
 805
 806         rev = get_board_rev();
 807         snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
 808         env_set("board_rev", env_str);
 809
 810 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
 811         if ((rev & 0xfff0) == 0x0100) {
 812                 char *fdt_env;
 813
 814                 /* reconfigure the UART to DCE mode dynamically if on V1.0 HW */
 815                 setup_iomux_dce_uart();
 816
 817                 /* if using the default device tree, use version for V1.0 HW */
 818                 fdt_env = env_get("fdt_file");
 819                 if ((fdt_env != NULL) && (strcmp(FDT_FILE, fdt_env) == 0)) {
 820                         env_set("fdt_file", FDT_FILE_V1_0);
 821                         printf("patching fdt_file to " FDT_FILE_V1_0 "\n");
 822 #ifndef CONFIG_ENV_IS_NOWHERE
 823                         env_save();
 824 #endif
 825                 }
 826         }
 827 #endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */
 828 #endif /* CONFIG_REVISION_TAG */
 829
 830         return 0;
 831 }
 832 #endif /* CONFIG_BOARD_LATE_INIT */
 833
 834 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP)
 835 int ft_system_setup(void *blob, bd_t *bd)
 836 {
 837         return 0;
 838 }
 839 #endif
 840
 841 int checkboard(void)
 842 {
 843         char it[] = " IT";
 844         int minc, maxc;
 845
 846         switch (get_cpu_temp_grade(&minc, &maxc)) {
 847         case TEMP_AUTOMOTIVE:
 848         case TEMP_INDUSTRIAL:
 849                 break;
 850         case TEMP_EXTCOMMERCIAL:
 851         default:
 852                 it[0] = 0;
 853         };
 854         printf("Model: Toradex Apalis iMX6 %s %s%s\n",
 855                is_cpu_type(MXC_CPU_MX6D) ? "Dual" : "Quad",
 856                (gd->ram_size == 0x80000000) ? "2GB" :
 857                (gd->ram_size == 0x40000000) ? "1GB" : "512MB", it);
 858         return 0;
 859 }
 860
 861 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 862 int ft_board_setup(void *blob, bd_t *bd)
 863 {
 864         return ft_common_board_setup(blob, bd);
 865 }
 866 #endif
 867
 868 #ifdef CONFIG_CMD_BMODE
 869 static const struct boot_mode board_boot_modes[] = {
 870         /* 4-bit bus width */
 871         {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 872         {"sd",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 873         {NULL,  0},
 874 };
 875 #endif
 876
 877 int misc_init_r(void)
 878 {
 879 #ifdef CONFIG_CMD_BMODE
 880         add_board_boot_modes(board_boot_modes);
 881 #endif
 882         return 0;
 883 }
 884
 885 #ifdef CONFIG_LDO_BYPASS_CHECK
 886 /* TODO, use external pmic, for now always ldo_enable */
 887 void ldo_mode_set(int ldo_bypass)
 888 {
 889         return;
 890 }
 891 #endif
 892
 893 #ifdef CONFIG_SPL_BUILD
 894 #include <spl.h>
 895 #include <libfdt.h>
 896 #include "asm/arch/mx6q-ddr.h"
 897 #include "asm/arch/iomux.h"
 898 #include "asm/arch/crm_regs.h"
 899
 900 static int mx6_com_dcd_table[] = {
 901 /* ddr-setup.cfg */
 902 MX6_IOM_DRAM_SDQS0, 0x00000030,
 903 MX6_IOM_DRAM_SDQS1, 0x00000030,
 904 MX6_IOM_DRAM_SDQS2, 0x00000030,
 905 MX6_IOM_DRAM_SDQS3, 0x00000030,
 906 MX6_IOM_DRAM_SDQS4, 0x00000030,
 907 MX6_IOM_DRAM_SDQS5, 0x00000030,
 908 MX6_IOM_DRAM_SDQS6, 0x00000030,
 909 MX6_IOM_DRAM_SDQS7, 0x00000030,
 910
 911 MX6_IOM_GRP_B0DS, 0x00000030,
 912 MX6_IOM_GRP_B1DS, 0x00000030,
 913 MX6_IOM_GRP_B2DS, 0x00000030,
 914 MX6_IOM_GRP_B3DS, 0x00000030,
 915 MX6_IOM_GRP_B4DS, 0x00000030,
 916 MX6_IOM_GRP_B5DS, 0x00000030,
 917 MX6_IOM_GRP_B6DS, 0x00000030,
 918 MX6_IOM_GRP_B7DS, 0x00000030,
 919 MX6_IOM_GRP_ADDDS, 0x00000030,
 920 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 921 MX6_IOM_GRP_CTLDS, 0x00000030,
 922
 923 MX6_IOM_DRAM_DQM0, 0x00020030,
 924 MX6_IOM_DRAM_DQM1, 0x00020030,
 925 MX6_IOM_DRAM_DQM2, 0x00020030,
 926 MX6_IOM_DRAM_DQM3, 0x00020030,
 927 MX6_IOM_DRAM_DQM4, 0x00020030,
 928 MX6_IOM_DRAM_DQM5, 0x00020030,
 929 MX6_IOM_DRAM_DQM6, 0x00020030,
 930 MX6_IOM_DRAM_DQM7, 0x00020030,
 931
 932 MX6_IOM_DRAM_CAS, 0x00020030,
 933 MX6_IOM_DRAM_RAS, 0x00020030,
 934 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 935 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 936
 937 MX6_IOM_DRAM_RESET, 0x00020030,
 938 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 939 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 940
 941 MX6_IOM_DRAM_SDODT0, 0x00003030,
 942 MX6_IOM_DRAM_SDODT1, 0x00003030,
 943
 944 /* (differential input) */
 945 MX6_IOM_DDRMODE_CTL, 0x00020000,
 946 /* (differential input) */
 947 MX6_IOM_GRP_DDRMODE, 0x00020000,
 948 /* disable ddr pullups */
 949 MX6_IOM_GRP_DDRPKE, 0x00000000,
 950 MX6_IOM_DRAM_SDBA2, 0x00000000,
 951 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 952 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 953
 954 /* Read data DQ Byte0-3 delay */
 955 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 956 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 957 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 958 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 959 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 960 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 961 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 962 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 963
 964 /*
 965  * MDMISC       mirroring       interleaved (row/bank/col)
 966  */
 967 MX6_MMDC_P0_MDMISC, 0x00081740,
 968
 969 /*
 970  * MDSCR        con_req
 971  */
 972 MX6_MMDC_P0_MDSCR, 0x00008000,
 973
 974 /* 1066mhz_4x128mx16.cfg */
 975
 976 MX6_MMDC_P0_MDPDC, 0x00020036,
 977 MX6_MMDC_P0_MDCFG0, 0x555A7954,
 978 MX6_MMDC_P0_MDCFG1, 0xDB328F64,
 979 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 980 MX6_MMDC_P0_MDRWD, 0x000026D2,
 981 MX6_MMDC_P0_MDOR, 0x005A1023,
 982 MX6_MMDC_P0_MDOTC, 0x09555050,
 983 MX6_MMDC_P0_MDPDC, 0x00025576,
 984 MX6_MMDC_P0_MDASP, 0x00000027,
 985 MX6_MMDC_P0_MDCTL, 0x831A0000,
 986 MX6_MMDC_P0_MDSCR, 0x04088032,
 987 MX6_MMDC_P0_MDSCR, 0x00008033,
 988 MX6_MMDC_P0_MDSCR, 0x00428031,
 989 MX6_MMDC_P0_MDSCR, 0x19308030,
 990 MX6_MMDC_P0_MDSCR, 0x04008040,
 991 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
 992 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
 993 MX6_MMDC_P0_MDREF, 0x00005800,
 994 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
 995 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
 996
 997 MX6_MMDC_P0_MPDGCTRL0, 0x432A0338,
 998 MX6_MMDC_P0_MPDGCTRL1, 0x03260324,
 999 MX6_MMDC_P1_MPDGCTRL0, 0x43340344,
1000 MX6_MMDC_P1_MPDGCTRL1, 0x031E027C,
1001
1002 MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E,
1003 MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37,
1004
1005 MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C,
1006 MX6_MMDC_P1_MPWRDLCTL, 0x4336453F,
1007
1008 MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
1009 MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
1010 MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
1011 MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
1012
1013 MX6_MMDC_P0_MPMUR0, 0x00000800,
1014 MX6_MMDC_P1_MPMUR0, 0x00000800,
1015 MX6_MMDC_P0_MDSCR, 0x00000000,
1016 MX6_MMDC_P0_MAPSR, 0x00011006,
1017 };
1018
1019 static int mx6_it_dcd_table[] = {
1020 /* ddr-setup.cfg */
1021 MX6_IOM_DRAM_SDQS0, 0x00000030,
1022 MX6_IOM_DRAM_SDQS1, 0x00000030,
1023 MX6_IOM_DRAM_SDQS2, 0x00000030,
1024 MX6_IOM_DRAM_SDQS3, 0x00000030,
1025 MX6_IOM_DRAM_SDQS4, 0x00000030,
1026 MX6_IOM_DRAM_SDQS5, 0x00000030,
1027 MX6_IOM_DRAM_SDQS6, 0x00000030,
1028 MX6_IOM_DRAM_SDQS7, 0x00000030,
1029
1030 MX6_IOM_GRP_B0DS, 0x00000030,
1031 MX6_IOM_GRP_B1DS, 0x00000030,
1032 MX6_IOM_GRP_B2DS, 0x00000030,
1033 MX6_IOM_GRP_B3DS, 0x00000030,
1034 MX6_IOM_GRP_B4DS, 0x00000030,
1035 MX6_IOM_GRP_B5DS, 0x00000030,
1036 MX6_IOM_GRP_B6DS, 0x00000030,
1037 MX6_IOM_GRP_B7DS, 0x00000030,
1038 MX6_IOM_GRP_ADDDS, 0x00000030,
1039 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
1040 MX6_IOM_GRP_CTLDS, 0x00000030,
1041
1042 MX6_IOM_DRAM_DQM0, 0x00020030,
1043 MX6_IOM_DRAM_DQM1, 0x00020030,
1044 MX6_IOM_DRAM_DQM2, 0x00020030,
1045 MX6_IOM_DRAM_DQM3, 0x00020030,
1046 MX6_IOM_DRAM_DQM4, 0x00020030,
1047 MX6_IOM_DRAM_DQM5, 0x00020030,
1048 MX6_IOM_DRAM_DQM6, 0x00020030,
1049 MX6_IOM_DRAM_DQM7, 0x00020030,
1050
1051 MX6_IOM_DRAM_CAS, 0x00020030,
1052 MX6_IOM_DRAM_RAS, 0x00020030,
1053 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
1054 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
1055
1056 MX6_IOM_DRAM_RESET, 0x00020030,
1057 MX6_IOM_DRAM_SDCKE0, 0x00003000,
1058 MX6_IOM_DRAM_SDCKE1, 0x00003000,
1059
1060 MX6_IOM_DRAM_SDODT0, 0x00003030,
1061 MX6_IOM_DRAM_SDODT1, 0x00003030,
1062
1063 /* (differential input) */
1064 MX6_IOM_DDRMODE_CTL, 0x00020000,
1065 /* (differential input) */
1066 MX6_IOM_GRP_DDRMODE, 0x00020000,
1067 /* disable ddr pullups */
1068 MX6_IOM_GRP_DDRPKE, 0x00000000,
1069 MX6_IOM_DRAM_SDBA2, 0x00000000,
1070 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
1071 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
1072
1073 /* Read data DQ Byte0-3 delay */
1074 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
1075 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
1076 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
1077 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
1078 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
1079 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
1080 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
1081 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
1082
1083 /*
1084  * MDMISC       mirroring       interleaved (row/bank/col)
1085  */
1086 MX6_MMDC_P0_MDMISC, 0x00081740,
1087
1088 /*
1089  * MDSCR        con_req
1090  */
1091 MX6_MMDC_P0_MDSCR, 0x00008000,
1092
1093 /* 1066mhz_4x256mx16.cfg */
1094
1095 MX6_MMDC_P0_MDPDC, 0x00020036,
1096 MX6_MMDC_P0_MDCFG0, 0x898E78f5,
1097 MX6_MMDC_P0_MDCFG1, 0xff328f64,
1098 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
1099 MX6_MMDC_P0_MDRWD, 0x000026D2,
1100 MX6_MMDC_P0_MDOR, 0x008E1023,
1101 MX6_MMDC_P0_MDOTC, 0x09444040,
1102 MX6_MMDC_P0_MDPDC, 0x00025576,
1103 MX6_MMDC_P0_MDASP, 0x00000047,
1104 MX6_MMDC_P0_MDCTL, 0x841A0000,
1105 MX6_MMDC_P0_MDSCR, 0x02888032,
1106 MX6_MMDC_P0_MDSCR, 0x00008033,
1107 MX6_MMDC_P0_MDSCR, 0x00048031,
1108 MX6_MMDC_P0_MDSCR, 0x19408030,
1109 MX6_MMDC_P0_MDSCR, 0x04008040,
1110 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
1111 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
1112 MX6_MMDC_P0_MDREF, 0x00007800,
1113 MX6_MMDC_P0_MPODTCTRL, 0x00022227,
1114 MX6_MMDC_P1_MPODTCTRL, 0x00022227,
1115
1116 MX6_MMDC_P0_MPDGCTRL0, 0x03300338,
1117 MX6_MMDC_P0_MPDGCTRL1, 0x03240324,
1118 MX6_MMDC_P1_MPDGCTRL0, 0x03440350,
1119 MX6_MMDC_P1_MPDGCTRL1, 0x032C0308,
1120
1121 MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E,
1122 MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46,
1123
1124 MX6_MMDC_P0_MPWRDLCTL, 0x403E463E,
1125 MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46,
1126
1127 MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
1128 MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
1129 MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
1130 MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
1131
1132 MX6_MMDC_P0_MPMUR0, 0x00000800,
1133 MX6_MMDC_P1_MPMUR0, 0x00000800,
1134 MX6_MMDC_P0_MDSCR, 0x00000000,
1135 MX6_MMDC_P0_MAPSR, 0x00011006,
1136 };
1137
1138
1139 static void ccgr_init(void)
1140 {
1141         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1142
1143         writel(0x00C03F3F, &ccm->CCGR0);
1144         writel(0x0030FC03, &ccm->CCGR1);
1145         writel(0x0FFFFFF3, &ccm->CCGR2);
1146         writel(0x3FF0300F, &ccm->CCGR3);
1147         writel(0x00FFF300, &ccm->CCGR4);
1148         writel(0x0F0000F3, &ccm->CCGR5);
1149         writel(0x000003FF, &ccm->CCGR6);
1150
1151 /*
1152  * Setup CCM_CCOSR register as follows:
1153  *
1154  * cko1_en  = 1    --> CKO1 enabled
1155  * cko1_div = 111  --> divide by 8
1156  * cko1_sel = 1011 --> ahb_clk_root
1157  *
1158  * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
1159  */
1160         writel(0x000000FB, &ccm->ccosr);
1161 }
1162
1163 static void ddr_init(int *table, int size)
1164 {
1165         int i;
1166
1167         for (i = 0; i < size / 2 ; i++)
1168                 writel(table[2 * i + 1], table[2 * i]);
1169 }
1170
1171 static void spl_dram_init(void)
1172 {
1173         int minc, maxc;
1174
1175         switch (get_cpu_temp_grade(&minc, &maxc)) {
1176         case TEMP_COMMERCIAL:
1177         case TEMP_EXTCOMMERCIAL:
1178                 puts("Commercial temperature grade DDR3 timings.\n");
1179                 ddr_init(mx6_com_dcd_table, ARRAY_SIZE(mx6_com_dcd_table));
1180                 break;
1181         case TEMP_INDUSTRIAL:
1182         case TEMP_AUTOMOTIVE:
1183         default:
1184                 puts("Industrial temperature grade DDR3 timings.\n");
1185                 ddr_init(mx6_it_dcd_table, ARRAY_SIZE(mx6_it_dcd_table));
1186                 break;
1187         };
1188         udelay(100);
1189 }
1190
1191 void board_init_f(ulong dummy)
1192 {
1193         /* setup AIPS and disable watchdog */
1194         arch_cpu_init();
1195
1196         ccgr_init();
1197         gpr_init();
1198
1199         /* iomux and setup of i2c */
1200         board_early_init_f();
1201
1202         /* setup GP timer */
1203         timer_init();
1204
1205         /* UART clocks enabled and gd valid - init serial console */
1206         preloader_console_init();
1207
1208 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
1209         /* Make sure we use dte mode */
1210         setup_dtemode_uart();
1211 #endif
1212
1213         /* DDR initialization */
1214         spl_dram_init();
1215
1216         /* Clear the BSS. */
1217         memset(__bss_start, 0, __bss_end - __bss_start);
1218
1219         /* load/boot image from boot device */
1220         board_init_r(NULL, 0);
1221 }
1222
1223 void reset_cpu(ulong addr)
1224 {
1225 }
1226
1227 #endif
1228
1229 static struct mxc_serial_platdata mxc_serial_plat = {
1230         .reg = (struct mxc_uart *)UART1_BASE,
1231         .use_dte = true,
1232 };
1233
1234 U_BOOT_DEVICE(mxc_serial) = {
1235         .name = "serial_mxc",
1236         .platdata = &mxc_serial_plat,
1237 };