board/toradex/apalis_imx6/apalis_imx6.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   5  * Copyright (C) 2014-2019, Toradex AG
   6  * copied from nitrogen6x
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11
  12 #include <ahci.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/crm_regs.h>
  15 #include <asm/arch/imx-regs.h>
  16 #include <asm/arch/mx6-ddr.h>
  17 #include <asm/arch/mx6-pins.h>
  18 #include <asm/arch/mxc_hdmi.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/bootm.h>
  21 #include <asm/gpio.h>
  22 #include <asm/mach-imx/boot_mode.h>
  23 #include <asm/mach-imx/iomux-v3.h>
  24 #include <asm/mach-imx/sata.h>
  25 #include <asm/mach-imx/video.h>
  26 #include <dm/device-internal.h>
  27 #include <dm/platform_data/serial_mxc.h>
  28 #include <dwc_ahsata.h>
  29 #include <env.h>
  30 #include <environment.h>
  31 #include <fsl_esdhc_imx.h>
  32 #include <imx_thermal.h>
  33 #include <micrel.h>
  34 #include <miiphy.h>
  35 #include <netdev.h>
  36
  37 #include "../common/tdx-cfg-block.h"
  38 #ifdef CONFIG_TDX_CMD_IMX_MFGR
  39 #include "pf0100.h"
  40 #endif
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  45         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  46         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  47
  48 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  49         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |                 \
  50         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  51
  52 #define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP |               \
  53         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  54         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  55
  56 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  57         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  58
  59 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  60         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  61         PAD_CTL_SRE_SLOW)
  62
  63 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  64         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  65         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  66
  67 #define TRISTATE        (PAD_CTL_HYS | PAD_CTL_SPEED_MED)
  68
  69 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
  70
  71 #define APALIS_IMX6_SATA_INIT_RETRIES   10
  72
  73 int dram_init(void)
  74 {
  75         /* use the DDR controllers configured size */
  76         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  77                                     (ulong)imx_ddr_size());
  78
  79         return 0;
  80 }
  81
  82 /* Apalis UART1 */
  83 iomux_v3_cfg_t const uart1_pads_dce[] = {
  84         MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  85         MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  86 };
  87 iomux_v3_cfg_t const uart1_pads_dte[] = {
  88         MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  89         MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  90 };
  91
  92 #if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
  93 /* Apalis MMC1 */
  94 iomux_v3_cfg_t const usdhc1_pads[] = {
  95         MX6_PAD_SD1_CLK__SD1_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  96         MX6_PAD_SD1_CMD__SD1_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  97         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  98         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  99         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 100         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 101         MX6_PAD_NANDF_D0__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 102         MX6_PAD_NANDF_D1__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 103         MX6_PAD_NANDF_D2__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 104         MX6_PAD_NANDF_D3__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 105         MX6_PAD_DI0_PIN4__GPIO4_IO20   | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 106 #       define GPIO_MMC_CD IMX_GPIO_NR(4, 20)
 107 };
 108
 109 /* Apalis SD1 */
 110 iomux_v3_cfg_t const usdhc2_pads[] = {
 111         MX6_PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 112         MX6_PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 113         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 114         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 115         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 116         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 117         MX6_PAD_NANDF_CS1__GPIO6_IO14  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 118 #       define GPIO_SD_CD IMX_GPIO_NR(6, 14)
 119 };
 120
 121 /* eMMC */
 122 iomux_v3_cfg_t const usdhc3_pads[] = {
 123         MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 124         MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 125         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 126         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 127         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 128         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 129         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 130         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 131         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 132         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 133         MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
 134 };
 135 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
 136
 137 int mx6_rgmii_rework(struct phy_device *phydev)
 138 {
 139         /* control data pad skew - devaddr = 0x02, register = 0x04 */
 140         ksz9031_phy_extended_write(phydev, 0x02,
 141                                    MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
 142                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 143         /* rx data pad skew - devaddr = 0x02, register = 0x05 */
 144         ksz9031_phy_extended_write(phydev, 0x02,
 145                                    MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
 146                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 147         /* tx data pad skew - devaddr = 0x02, register = 0x05 */
 148         ksz9031_phy_extended_write(phydev, 0x02,
 149                                    MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
 150                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 151         /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
 152         ksz9031_phy_extended_write(phydev, 0x02,
 153                                    MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
 154                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
 155         return 0;
 156 }
 157
 158 iomux_v3_cfg_t const enet_pads[] = {
 159         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 160         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 161         MX6_PAD_RGMII_TXC__RGMII_TXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 162         MX6_PAD_RGMII_TD0__RGMII_TD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 163         MX6_PAD_RGMII_TD1__RGMII_TD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 164         MX6_PAD_RGMII_TD2__RGMII_TD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 165         MX6_PAD_RGMII_TD3__RGMII_TD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 166         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 167         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 168         MX6_PAD_RGMII_RXC__RGMII_RXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 169         MX6_PAD_RGMII_RD0__RGMII_RD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 170         MX6_PAD_RGMII_RD1__RGMII_RD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 171         MX6_PAD_RGMII_RD2__RGMII_RD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 172         MX6_PAD_RGMII_RD3__RGMII_RD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 173         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 174         /* KSZ9031 PHY Reset */
 175         MX6_PAD_ENET_CRS_DV__GPIO1_IO25         | MUX_PAD_CTRL(NO_PAD_CTRL) |
 176                                                   MUX_MODE_SION,
 177 #       define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25)
 178 };
 179
 180 static void setup_iomux_enet(void)
 181 {
 182         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 183 }
 184
 185 static int reset_enet_phy(struct mii_dev *bus)
 186 {
 187         /* Reset KSZ9031 PHY */
 188         gpio_request(GPIO_ENET_PHY_RESET, "ETH_RESET#");
 189         gpio_direction_output(GPIO_ENET_PHY_RESET, 0);
 190         mdelay(10);
 191         gpio_set_value(GPIO_ENET_PHY_RESET, 1);
 192
 193         return 0;
 194 }
 195
 196 /* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */
 197 iomux_v3_cfg_t const gpio_pads[] = {
 198         /* Apalis GPIO1 - GPIO8 */
 199         MX6_PAD_NANDF_D4__GPIO2_IO04    | MUX_PAD_CTRL(WEAK_PULLUP) |
 200                                           MUX_MODE_SION,
 201         MX6_PAD_NANDF_D5__GPIO2_IO05    | MUX_PAD_CTRL(WEAK_PULLUP) |
 202                                           MUX_MODE_SION,
 203         MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(WEAK_PULLUP) |
 204                                           MUX_MODE_SION,
 205         MX6_PAD_NANDF_D7__GPIO2_IO07    | MUX_PAD_CTRL(WEAK_PULLUP) |
 206                                           MUX_MODE_SION,
 207         MX6_PAD_NANDF_RB0__GPIO6_IO10   | MUX_PAD_CTRL(WEAK_PULLUP) |
 208                                           MUX_MODE_SION,
 209         MX6_PAD_NANDF_WP_B__GPIO6_IO09  | MUX_PAD_CTRL(WEAK_PULLUP) |
 210                                           MUX_MODE_SION,
 211         MX6_PAD_GPIO_2__GPIO1_IO02      | MUX_PAD_CTRL(WEAK_PULLDOWN) |
 212                                           MUX_MODE_SION,
 213         MX6_PAD_GPIO_6__GPIO1_IO06      | MUX_PAD_CTRL(WEAK_PULLUP) |
 214                                           MUX_MODE_SION,
 215         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(WEAK_PULLUP) |
 216                                           MUX_MODE_SION,
 217 };
 218
 219 static void setup_iomux_gpio(void)
 220 {
 221         imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
 222 }
 223
 224 iomux_v3_cfg_t const usb_pads[] = {
 225         /* USBH_EN */
 226         MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 227 #       define GPIO_USBH_EN IMX_GPIO_NR(1, 0)
 228         /* USB_VBUS_DET */
 229         MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
 230 #       define GPIO_USB_VBUS_DET IMX_GPIO_NR(3, 28)
 231         /* USBO1_ID */
 232         MX6_PAD_ENET_RX_ER__USB_OTG_ID  | MUX_PAD_CTRL(WEAK_PULLUP),
 233         /* USBO1_EN */
 234         MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 235 #       define GPIO_USBO_EN IMX_GPIO_NR(3, 22)
 236 };
 237
 238 /*
 239  * UARTs are used in DTE mode, switch the mode on all UARTs before
 240  * any pinmuxing connects a (DCE) output to a transceiver output.
 241  */
 242 #define UCR3            0x88    /* FIFO Control Register */
 243 #define UCR3_RI         BIT(8)  /* RIDELT DTE mode */
 244 #define UCR3_DCD        BIT(9)  /* DCDDELT DTE mode */
 245 #define UFCR            0x90    /* FIFO Control Register */
 246 #define UFCR_DCEDTE     BIT(6)  /* DCE=0 */
 247
 248 static void setup_dtemode_uart(void)
 249 {
 250         setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 251         setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 252         setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
 253         setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
 254
 255         clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
 256         clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
 257         clrbits_le32((u32 *)(UART4_BASE + UCR3), UCR3_DCD | UCR3_RI);
 258         clrbits_le32((u32 *)(UART5_BASE + UCR3), UCR3_DCD | UCR3_RI);
 259 }
 260 static void setup_dcemode_uart(void)
 261 {
 262         clrbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 263         clrbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 264         clrbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
 265         clrbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
 266 }
 267
 268 static void setup_iomux_dte_uart(void)
 269 {
 270         setup_dtemode_uart();
 271         imx_iomux_v3_setup_multiple_pads(uart1_pads_dte,
 272                                          ARRAY_SIZE(uart1_pads_dte));
 273 }
 274 static void setup_iomux_dce_uart(void)
 275 {
 276         setup_dcemode_uart();
 277         imx_iomux_v3_setup_multiple_pads(uart1_pads_dce,
 278                                          ARRAY_SIZE(uart1_pads_dce));
 279 }
 280
 281 #ifdef CONFIG_USB_EHCI_MX6
 282 int board_ehci_hcd_init(int port)
 283 {
 284         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 285         return 0;
 286 }
 287 #endif
 288
 289 #if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
 290 /* use the following sequence: eMMC, MMC1, SD1 */
 291 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
 292         {USDHC3_BASE_ADDR},
 293         {USDHC1_BASE_ADDR},
 294         {USDHC2_BASE_ADDR},
 295 };
 296
 297 int board_mmc_getcd(struct mmc *mmc)
 298 {
 299         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 300         int ret = true; /* default: assume inserted */
 301
 302         switch (cfg->esdhc_base) {
 303         case USDHC1_BASE_ADDR:
 304                 gpio_request(GPIO_MMC_CD, "MMC_CD");
 305                 gpio_direction_input(GPIO_MMC_CD);
 306                 ret = !gpio_get_value(GPIO_MMC_CD);
 307                 break;
 308         case USDHC2_BASE_ADDR:
 309                 gpio_request(GPIO_MMC_CD, "SD_CD");
 310                 gpio_direction_input(GPIO_SD_CD);
 311                 ret = !gpio_get_value(GPIO_SD_CD);
 312                 break;
 313         }
 314
 315         return ret;
 316 }
 317
 318 int board_mmc_init(bd_t *bis)
 319 {
 320         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 321         unsigned reg = readl(&psrc->sbmr1) >> 11;
 322         /*
 323          * Upon reading BOOT_CFG register the following map is done:
 324          * Bit 11 and 12 of BOOT_CFG register can determine the current
 325          * mmc port
 326          * 0x1                  SD1
 327          * 0x2                  SD2
 328          * 0x3                  SD4
 329          */
 330
 331         switch (reg & 0x3) {
 332         case 0x0:
 333                 imx_iomux_v3_setup_multiple_pads(
 334                         usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 335                 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
 336                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 337                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 338                 break;
 339         case 0x1:
 340                 imx_iomux_v3_setup_multiple_pads(
 341                         usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 342                 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
 343                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 344                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 345                 break;
 346         case 0x2:
 347                 imx_iomux_v3_setup_multiple_pads(
 348                         usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 349                 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 350                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 351                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 352                 break;
 353         default:
 354                 puts("MMC boot device not available");
 355         }
 356
 357         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 358 }
 359 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
 360
 361 int board_phy_config(struct phy_device *phydev)
 362 {
 363         mx6_rgmii_rework(phydev);
 364         if (phydev->drv->config)
 365                 phydev->drv->config(phydev);
 366
 367         return 0;
 368 }
 369
 370 int board_eth_init(bd_t *bis)
 371 {
 372         uint32_t base = IMX_FEC_BASE;
 373         struct mii_dev *bus = NULL;
 374         struct phy_device *phydev = NULL;
 375         int ret;
 376
 377         setup_iomux_enet();
 378
 379 #ifdef CONFIG_FEC_MXC
 380         bus = fec_get_miibus(base, -1);
 381         if (!bus)
 382                 return 0;
 383
 384         bus->reset = reset_enet_phy;
 385         /* scan PHY 4,5,6,7 */
 386         phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
 387         if (!phydev) {
 388                 free(bus);
 389                 puts("no PHY found\n");
 390                 return 0;
 391         }
 392
 393         printf("using PHY at %d\n", phydev->addr);
 394         ret = fec_probe(bis, -1, base, bus, phydev);
 395         if (ret) {
 396                 printf("FEC MXC: %s:failed\n", __func__);
 397                 free(phydev);
 398                 free(bus);
 399         }
 400 #endif /* CONFIG_FEC_MXC */
 401
 402         return 0;
 403 }
 404
 405 static iomux_v3_cfg_t const pwr_intb_pads[] = {
 406         /*
 407          * the bootrom sets the iomux to vselect, potentially connecting
 408          * two outputs. Set this back to GPIO
 409          */
 410         MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
 411 };
 412
 413 #if defined(CONFIG_VIDEO_IPUV3)
 414
 415 static iomux_v3_cfg_t const backlight_pads[] = {
 416         /* Backlight on RGB connector: J15 */
 417         MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 418                                        MUX_MODE_SION,
 419 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13)
 420         /* additional CPU pin on BKL_PWM, keep in tristate */
 421         MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE),
 422         /* Backlight PWM, used as GPIO in U-Boot */
 423         MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 424                                        MUX_MODE_SION,
 425 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10)
 426         /* buffer output enable 0: buffer enabled */
 427         MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
 428 #define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2)
 429         /* PSAVE# integrated VDAC */
 430         MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 431                                        MUX_MODE_SION,
 432 #define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31)
 433 };
 434
 435 static iomux_v3_cfg_t const rgb_pads[] = {
 436         MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
 437         MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
 438         MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
 439         MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
 440         MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
 441         MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
 442         MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
 443         MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
 444         MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
 445         MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
 446         MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
 447         MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
 448         MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
 449         MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
 450         MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
 451         MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
 452         MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
 453         MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
 454         MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
 455         MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
 456         MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
 457         MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
 458         MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 | MUX_PAD_CTRL(OUTPUT_RGB),
 459         MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 | MUX_PAD_CTRL(OUTPUT_RGB),
 460         MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 | MUX_PAD_CTRL(OUTPUT_RGB),
 461         MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 | MUX_PAD_CTRL(OUTPUT_RGB),
 462         MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 | MUX_PAD_CTRL(OUTPUT_RGB),
 463         MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 | MUX_PAD_CTRL(OUTPUT_RGB),
 464 };
 465
 466 static void do_enable_hdmi(struct display_info_t const *dev)
 467 {
 468         imx_enable_hdmi_phy();
 469 }
 470
 471 static void enable_lvds(struct display_info_t const *dev)
 472 {
 473         struct iomuxc *iomux = (struct iomuxc *)
 474                                 IOMUXC_BASE_ADDR;
 475         u32 reg = readl(&iomux->gpr[2]);
 476         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 477         writel(reg, &iomux->gpr[2]);
 478         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 479         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 480         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 481 }
 482
 483 static void enable_rgb(struct display_info_t const *dev)
 484 {
 485         imx_iomux_v3_setup_multiple_pads(
 486                 rgb_pads,
 487                 ARRAY_SIZE(rgb_pads));
 488         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 489         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 490         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 491 }
 492
 493 static int detect_default(struct display_info_t const *dev)
 494 {
 495         (void) dev;
 496         return 1;
 497 }
 498
 499 struct display_info_t const displays[] = {{
 500         .bus    = -1,
 501         .addr   = 0,
 502         .pixfmt = IPU_PIX_FMT_RGB24,
 503         .detect = detect_hdmi,
 504         .enable = do_enable_hdmi,
 505         .mode   = {
 506                 .name           = "HDMI",
 507                 .refresh        = 60,
 508                 .xres           = 1024,
 509                 .yres           = 768,
 510                 .pixclock       = 15385,
 511                 .left_margin    = 220,
 512                 .right_margin   = 40,
 513                 .upper_margin   = 21,
 514                 .lower_margin   = 7,
 515                 .hsync_len      = 60,
 516                 .vsync_len      = 10,
 517                 .sync           = FB_SYNC_EXT,
 518                 .vmode          = FB_VMODE_NONINTERLACED
 519 } }, {
 520         .bus    = -1,
 521         .addr   = 0,
 522         .di     = 1,
 523         .pixfmt = IPU_PIX_FMT_RGB24,
 524         .detect = detect_default,
 525         .enable = enable_rgb,
 526         .mode   = {
 527                 .name           = "vga-rgb",
 528                 .refresh        = 60,
 529                 .xres           = 640,
 530                 .yres           = 480,
 531                 .pixclock       = 33000,
 532                 .left_margin    = 48,
 533                 .right_margin   = 16,
 534                 .upper_margin   = 31,
 535                 .lower_margin   = 11,
 536                 .hsync_len      = 96,
 537                 .vsync_len      = 2,
 538                 .sync           = 0,
 539                 .vmode          = FB_VMODE_NONINTERLACED
 540 } }, {
 541         .bus    = -1,
 542         .addr   = 0,
 543         .di     = 1,
 544         .pixfmt = IPU_PIX_FMT_RGB24,
 545         .enable = enable_rgb,
 546         .mode   = {
 547                 .name           = "wvga-rgb",
 548                 .refresh        = 60,
 549                 .xres           = 800,
 550                 .yres           = 480,
 551                 .pixclock       = 25000,
 552                 .left_margin    = 40,
 553                 .right_margin   = 88,
 554                 .upper_margin   = 33,
 555                 .lower_margin   = 10,
 556                 .hsync_len      = 128,
 557                 .vsync_len      = 2,
 558                 .sync           = 0,
 559                 .vmode          = FB_VMODE_NONINTERLACED
 560 } }, {
 561         .bus    = -1,
 562         .addr   = 0,
 563         .pixfmt = IPU_PIX_FMT_LVDS666,
 564         .enable = enable_lvds,
 565         .mode   = {
 566                 .name           = "wsvga-lvds",
 567                 .refresh        = 60,
 568                 .xres           = 1024,
 569                 .yres           = 600,
 570                 .pixclock       = 15385,
 571                 .left_margin    = 220,
 572                 .right_margin   = 40,
 573                 .upper_margin   = 21,
 574                 .lower_margin   = 7,
 575                 .hsync_len      = 60,
 576                 .vsync_len      = 10,
 577                 .sync           = FB_SYNC_EXT,
 578                 .vmode          = FB_VMODE_NONINTERLACED
 579 } } };
 580 size_t display_count = ARRAY_SIZE(displays);
 581
 582 static void setup_display(void)
 583 {
 584         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 585         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 586         int reg;
 587
 588         enable_ipu_clock();
 589         imx_setup_hdmi();
 590         /* Turn on LDB0,IPU,IPU DI0 clocks */
 591         reg = __raw_readl(&mxc_ccm->CCGR3);
 592         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 593         writel(reg, &mxc_ccm->CCGR3);
 594
 595         /* set LDB0, LDB1 clk select to 011/011 */
 596         reg = readl(&mxc_ccm->cs2cdr);
 597         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 598                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 599         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 600               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 601         writel(reg, &mxc_ccm->cs2cdr);
 602
 603         reg = readl(&mxc_ccm->cscmr2);
 604         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 605         writel(reg, &mxc_ccm->cscmr2);
 606
 607         reg = readl(&mxc_ccm->chsccdr);
 608         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 609                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 610         writel(reg, &mxc_ccm->chsccdr);
 611
 612         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 613              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 614              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 615              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 616              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 617              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 618              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 619              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 620              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 621         writel(reg, &iomux->gpr[2]);
 622
 623         reg = readl(&iomux->gpr[3]);
 624         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 625                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 626             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 627                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 628         writel(reg, &iomux->gpr[3]);
 629
 630         /* backlight unconditionally on for now */
 631         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 632                                          ARRAY_SIZE(backlight_pads));
 633         /* use 0 for EDT 7", use 1 for LG fullHD panel */
 634         gpio_request(RGB_BACKLIGHTPWM_GP, "BKL1_PWM");
 635         gpio_request(RGB_BACKLIGHTPWM_OE, "BKL1_PWM_EN");
 636         gpio_request(RGB_BACKLIGHT_GP, "BKL1_ON");
 637         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 638         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 639         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 640 }
 641
 642 /*
 643  * Backlight off before OS handover
 644  */
 645 void board_preboot_os(void)
 646 {
 647         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
 648         gpio_direction_output(RGB_BACKLIGHT_GP, 0);
 649 }
 650 #endif /* defined(CONFIG_VIDEO_IPUV3) */
 651
 652 int board_early_init_f(void)
 653 {
 654         imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
 655                                          ARRAY_SIZE(pwr_intb_pads));
 656 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
 657         setup_iomux_dte_uart();
 658 #else
 659         setup_iomux_dce_uart();
 660 #endif
 661         return 0;
 662 }
 663
 664 /*
 665  * Do not overwrite the console
 666  * Use always serial for U-Boot console
 667  */
 668 int overwrite_console(void)
 669 {
 670         return 1;
 671 }
 672
 673 int board_init(void)
 674 {
 675         /* address of boot parameters */
 676         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 677
 678 #if defined(CONFIG_VIDEO_IPUV3)
 679         setup_display();
 680 #endif
 681
 682 #ifdef CONFIG_TDX_CMD_IMX_MFGR
 683         (void) pmic_init();
 684 #endif
 685
 686 #ifdef CONFIG_SATA
 687         setup_sata();
 688 #endif
 689
 690         setup_iomux_gpio();
 691
 692         return 0;
 693 }
 694
 695 #ifdef CONFIG_BOARD_LATE_INIT
 696 int board_late_init(void)
 697 {
 698 #if defined(CONFIG_REVISION_TAG) && \
 699     defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
 700         char env_str[256];
 701         u32 rev;
 702
 703         rev = get_board_rev();
 704         snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
 705         env_set("board_rev", env_str);
 706
 707 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
 708         if ((rev & 0xfff0) == 0x0100) {
 709                 char *fdt_env;
 710
 711                 /* reconfigure the UART to DCE mode dynamically if on V1.0 HW */
 712                 setup_iomux_dce_uart();
 713
 714                 /* if using the default device tree, use version for V1.0 HW */
 715                 fdt_env = env_get("fdt_file");
 716                 if ((fdt_env != NULL) && (strcmp(FDT_FILE, fdt_env) == 0)) {
 717                         env_set("fdt_file", FDT_FILE_V1_0);
 718                         printf("patching fdt_file to " FDT_FILE_V1_0 "\n");
 719 #ifndef CONFIG_ENV_IS_NOWHERE
 720                         env_save();
 721 #endif
 722                 }
 723         }
 724 #endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */
 725 #endif /* CONFIG_REVISION_TAG */
 726
 727 #ifdef CONFIG_CMD_USB_SDP
 728         if (is_boot_from_usb()) {
 729                 printf("Serial Downloader recovery mode, using sdp command\n");
 730                 env_set("bootdelay", "0");
 731                 env_set("bootcmd", "sdp 0");
 732         }
 733 #endif /* CONFIG_CMD_USB_SDP */
 734
 735         return 0;
 736 }
 737 #endif /* CONFIG_BOARD_LATE_INIT */
 738
 739 int checkboard(void)
 740 {
 741         char it[] = " IT";
 742         int minc, maxc;
 743
 744         switch (get_cpu_temp_grade(&minc, &maxc)) {
 745         case TEMP_AUTOMOTIVE:
 746         case TEMP_INDUSTRIAL:
 747                 break;
 748         case TEMP_EXTCOMMERCIAL:
 749         default:
 750                 it[0] = 0;
 751         };
 752         printf("Model: Toradex Apalis iMX6 %s %s%s\n",
 753                is_cpu_type(MXC_CPU_MX6D) ? "Dual" : "Quad",
 754                (gd->ram_size == 0x80000000) ? "2GB" :
 755                (gd->ram_size == 0x40000000) ? "1GB" : "512MB", it);
 756         return 0;
 757 }
 758
 759 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 760 int ft_board_setup(void *blob, bd_t *bd)
 761 {
 762         return ft_common_board_setup(blob, bd);
 763 }
 764 #endif
 765
 766 #ifdef CONFIG_CMD_BMODE
 767 static const struct boot_mode board_boot_modes[] = {
 768         /* 4-bit bus width */
 769         {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 770         {"sd",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 771         {NULL,  0},
 772 };
 773 #endif
 774
 775 int misc_init_r(void)
 776 {
 777 #ifdef CONFIG_CMD_BMODE
 778         add_board_boot_modes(board_boot_modes);
 779 #endif
 780         return 0;
 781 }
 782
 783 #ifdef CONFIG_LDO_BYPASS_CHECK
 784 /* TODO, use external pmic, for now always ldo_enable */
 785 void ldo_mode_set(int ldo_bypass)
 786 {
 787         return;
 788 }
 789 #endif
 790
 791 #ifdef CONFIG_SPL_BUILD
 792 #include <spl.h>
 793 #include <linux/libfdt.h>
 794 #include "asm/arch/mx6q-ddr.h"
 795 #include "asm/arch/iomux.h"
 796 #include "asm/arch/crm_regs.h"
 797
 798 static int mx6_com_dcd_table[] = {
 799 /* ddr-setup.cfg */
 800 MX6_IOM_DRAM_SDQS0, 0x00000030,
 801 MX6_IOM_DRAM_SDQS1, 0x00000030,
 802 MX6_IOM_DRAM_SDQS2, 0x00000030,
 803 MX6_IOM_DRAM_SDQS3, 0x00000030,
 804 MX6_IOM_DRAM_SDQS4, 0x00000030,
 805 MX6_IOM_DRAM_SDQS5, 0x00000030,
 806 MX6_IOM_DRAM_SDQS6, 0x00000030,
 807 MX6_IOM_DRAM_SDQS7, 0x00000030,
 808
 809 MX6_IOM_GRP_B0DS, 0x00000030,
 810 MX6_IOM_GRP_B1DS, 0x00000030,
 811 MX6_IOM_GRP_B2DS, 0x00000030,
 812 MX6_IOM_GRP_B3DS, 0x00000030,
 813 MX6_IOM_GRP_B4DS, 0x00000030,
 814 MX6_IOM_GRP_B5DS, 0x00000030,
 815 MX6_IOM_GRP_B6DS, 0x00000030,
 816 MX6_IOM_GRP_B7DS, 0x00000030,
 817 MX6_IOM_GRP_ADDDS, 0x00000030,
 818 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 819 MX6_IOM_GRP_CTLDS, 0x00000030,
 820
 821 MX6_IOM_DRAM_DQM0, 0x00020030,
 822 MX6_IOM_DRAM_DQM1, 0x00020030,
 823 MX6_IOM_DRAM_DQM2, 0x00020030,
 824 MX6_IOM_DRAM_DQM3, 0x00020030,
 825 MX6_IOM_DRAM_DQM4, 0x00020030,
 826 MX6_IOM_DRAM_DQM5, 0x00020030,
 827 MX6_IOM_DRAM_DQM6, 0x00020030,
 828 MX6_IOM_DRAM_DQM7, 0x00020030,
 829
 830 MX6_IOM_DRAM_CAS, 0x00020030,
 831 MX6_IOM_DRAM_RAS, 0x00020030,
 832 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 833 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 834
 835 MX6_IOM_DRAM_RESET, 0x00020030,
 836 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 837 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 838
 839 MX6_IOM_DRAM_SDODT0, 0x00003030,
 840 MX6_IOM_DRAM_SDODT1, 0x00003030,
 841
 842 /* (differential input) */
 843 MX6_IOM_DDRMODE_CTL, 0x00020000,
 844 /* (differential input) */
 845 MX6_IOM_GRP_DDRMODE, 0x00020000,
 846 /* disable ddr pullups */
 847 MX6_IOM_GRP_DDRPKE, 0x00000000,
 848 MX6_IOM_DRAM_SDBA2, 0x00000000,
 849 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 850 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 851
 852 /* Read data DQ Byte0-3 delay */
 853 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 854 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 855 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 856 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 857 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 858 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 859 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 860 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 861
 862 /*
 863  * MDMISC       mirroring       interleaved (row/bank/col)
 864  */
 865 MX6_MMDC_P0_MDMISC, 0x00081740,
 866
 867 /*
 868  * MDSCR        con_req
 869  */
 870 MX6_MMDC_P0_MDSCR, 0x00008000,
 871
 872 /* 1066mhz_4x128mx16.cfg */
 873
 874 MX6_MMDC_P0_MDPDC, 0x00020036,
 875 MX6_MMDC_P0_MDCFG0, 0x555A7954,
 876 MX6_MMDC_P0_MDCFG1, 0xDB328F64,
 877 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 878 MX6_MMDC_P0_MDRWD, 0x000026D2,
 879 MX6_MMDC_P0_MDOR, 0x005A1023,
 880 MX6_MMDC_P0_MDOTC, 0x09555050,
 881 MX6_MMDC_P0_MDPDC, 0x00025576,
 882 MX6_MMDC_P0_MDASP, 0x00000027,
 883 MX6_MMDC_P0_MDCTL, 0x831A0000,
 884 MX6_MMDC_P0_MDSCR, 0x04088032,
 885 MX6_MMDC_P0_MDSCR, 0x00008033,
 886 MX6_MMDC_P0_MDSCR, 0x00428031,
 887 MX6_MMDC_P0_MDSCR, 0x19308030,
 888 MX6_MMDC_P0_MDSCR, 0x04008040,
 889 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
 890 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
 891 MX6_MMDC_P0_MDREF, 0x00005800,
 892 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
 893 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
 894
 895 MX6_MMDC_P0_MPDGCTRL0, 0x432A0338,
 896 MX6_MMDC_P0_MPDGCTRL1, 0x03260324,
 897 MX6_MMDC_P1_MPDGCTRL0, 0x43340344,
 898 MX6_MMDC_P1_MPDGCTRL1, 0x031E027C,
 899
 900 MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E,
 901 MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37,
 902
 903 MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C,
 904 MX6_MMDC_P1_MPWRDLCTL, 0x4336453F,
 905
 906 MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
 907 MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
 908 MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
 909 MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
 910
 911 MX6_MMDC_P0_MPMUR0, 0x00000800,
 912 MX6_MMDC_P1_MPMUR0, 0x00000800,
 913 MX6_MMDC_P0_MDSCR, 0x00000000,
 914 MX6_MMDC_P0_MAPSR, 0x00011006,
 915 };
 916
 917 static int mx6_it_dcd_table[] = {
 918 /* ddr-setup.cfg */
 919 MX6_IOM_DRAM_SDQS0, 0x00000030,
 920 MX6_IOM_DRAM_SDQS1, 0x00000030,
 921 MX6_IOM_DRAM_SDQS2, 0x00000030,
 922 MX6_IOM_DRAM_SDQS3, 0x00000030,
 923 MX6_IOM_DRAM_SDQS4, 0x00000030,
 924 MX6_IOM_DRAM_SDQS5, 0x00000030,
 925 MX6_IOM_DRAM_SDQS6, 0x00000030,
 926 MX6_IOM_DRAM_SDQS7, 0x00000030,
 927
 928 MX6_IOM_GRP_B0DS, 0x00000030,
 929 MX6_IOM_GRP_B1DS, 0x00000030,
 930 MX6_IOM_GRP_B2DS, 0x00000030,
 931 MX6_IOM_GRP_B3DS, 0x00000030,
 932 MX6_IOM_GRP_B4DS, 0x00000030,
 933 MX6_IOM_GRP_B5DS, 0x00000030,
 934 MX6_IOM_GRP_B6DS, 0x00000030,
 935 MX6_IOM_GRP_B7DS, 0x00000030,
 936 MX6_IOM_GRP_ADDDS, 0x00000030,
 937 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 938 MX6_IOM_GRP_CTLDS, 0x00000030,
 939
 940 MX6_IOM_DRAM_DQM0, 0x00020030,
 941 MX6_IOM_DRAM_DQM1, 0x00020030,
 942 MX6_IOM_DRAM_DQM2, 0x00020030,
 943 MX6_IOM_DRAM_DQM3, 0x00020030,
 944 MX6_IOM_DRAM_DQM4, 0x00020030,
 945 MX6_IOM_DRAM_DQM5, 0x00020030,
 946 MX6_IOM_DRAM_DQM6, 0x00020030,
 947 MX6_IOM_DRAM_DQM7, 0x00020030,
 948
 949 MX6_IOM_DRAM_CAS, 0x00020030,
 950 MX6_IOM_DRAM_RAS, 0x00020030,
 951 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 952 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 953
 954 MX6_IOM_DRAM_RESET, 0x00020030,
 955 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 956 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 957
 958 MX6_IOM_DRAM_SDODT0, 0x00003030,
 959 MX6_IOM_DRAM_SDODT1, 0x00003030,
 960
 961 /* (differential input) */
 962 MX6_IOM_DDRMODE_CTL, 0x00020000,
 963 /* (differential input) */
 964 MX6_IOM_GRP_DDRMODE, 0x00020000,
 965 /* disable ddr pullups */
 966 MX6_IOM_GRP_DDRPKE, 0x00000000,
 967 MX6_IOM_DRAM_SDBA2, 0x00000000,
 968 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 969 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 970
 971 /* Read data DQ Byte0-3 delay */
 972 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 973 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 974 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 975 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 976 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 977 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 978 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 979 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 980
 981 /*
 982  * MDMISC       mirroring       interleaved (row/bank/col)
 983  */
 984 MX6_MMDC_P0_MDMISC, 0x00081740,
 985
 986 /*
 987  * MDSCR        con_req
 988  */
 989 MX6_MMDC_P0_MDSCR, 0x00008000,
 990
 991 /* 1066mhz_4x256mx16.cfg */
 992
 993 MX6_MMDC_P0_MDPDC, 0x00020036,
 994 MX6_MMDC_P0_MDCFG0, 0x898E78f5,
 995 MX6_MMDC_P0_MDCFG1, 0xff328f64,
 996 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 997 MX6_MMDC_P0_MDRWD, 0x000026D2,
 998 MX6_MMDC_P0_MDOR, 0x008E1023,
 999 MX6_MMDC_P0_MDOTC, 0x09444040,
1000 MX6_MMDC_P0_MDPDC, 0x00025576,
1001 MX6_MMDC_P0_MDASP, 0x00000047,
1002 MX6_MMDC_P0_MDCTL, 0x841A0000,
1003 MX6_MMDC_P0_MDSCR, 0x02888032,
1004 MX6_MMDC_P0_MDSCR, 0x00008033,
1005 MX6_MMDC_P0_MDSCR, 0x00048031,
1006 MX6_MMDC_P0_MDSCR, 0x19408030,
1007 MX6_MMDC_P0_MDSCR, 0x04008040,
1008 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
1009 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
1010 MX6_MMDC_P0_MDREF, 0x00007800,
1011 MX6_MMDC_P0_MPODTCTRL, 0x00022227,
1012 MX6_MMDC_P1_MPODTCTRL, 0x00022227,
1013
1014 MX6_MMDC_P0_MPDGCTRL0, 0x03300338,
1015 MX6_MMDC_P0_MPDGCTRL1, 0x03240324,
1016 MX6_MMDC_P1_MPDGCTRL0, 0x03440350,
1017 MX6_MMDC_P1_MPDGCTRL1, 0x032C0308,
1018
1019 MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E,
1020 MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46,
1021
1022 MX6_MMDC_P0_MPWRDLCTL, 0x403E463E,
1023 MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46,
1024
1025 MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
1026 MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
1027 MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
1028 MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
1029
1030 MX6_MMDC_P0_MPMUR0, 0x00000800,
1031 MX6_MMDC_P1_MPMUR0, 0x00000800,
1032 MX6_MMDC_P0_MDSCR, 0x00000000,
1033 MX6_MMDC_P0_MAPSR, 0x00011006,
1034 };
1035
1036 static void ccgr_init(void)
1037 {
1038         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1039
1040         writel(0x00C03F3F, &ccm->CCGR0);
1041         writel(0x0030FC03, &ccm->CCGR1);
1042         writel(0x0FFFFFF3, &ccm->CCGR2);
1043         writel(0x3FF0300F, &ccm->CCGR3);
1044         writel(0x00FFF300, &ccm->CCGR4);
1045         writel(0x0F0000F3, &ccm->CCGR5);
1046         writel(0x000003FF, &ccm->CCGR6);
1047
1048 /*
1049  * Setup CCM_CCOSR register as follows:
1050  *
1051  * cko1_en  = 1    --> CKO1 enabled
1052  * cko1_div = 111  --> divide by 8
1053  * cko1_sel = 1011 --> ahb_clk_root
1054  *
1055  * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
1056  */
1057         writel(0x000000FB, &ccm->ccosr);
1058 }
1059
1060 static void ddr_init(int *table, int size)
1061 {
1062         int i;
1063
1064         for (i = 0; i < size / 2 ; i++)
1065                 writel(table[2 * i + 1], table[2 * i]);
1066 }
1067
1068 static void spl_dram_init(void)
1069 {
1070         int minc, maxc;
1071
1072         switch (get_cpu_temp_grade(&minc, &maxc)) {
1073         case TEMP_COMMERCIAL:
1074         case TEMP_EXTCOMMERCIAL:
1075                 puts("Commercial temperature grade DDR3 timings.\n");
1076                 ddr_init(mx6_com_dcd_table, ARRAY_SIZE(mx6_com_dcd_table));
1077                 break;
1078         case TEMP_INDUSTRIAL:
1079         case TEMP_AUTOMOTIVE:
1080         default:
1081                 puts("Industrial temperature grade DDR3 timings.\n");
1082                 ddr_init(mx6_it_dcd_table, ARRAY_SIZE(mx6_it_dcd_table));
1083                 break;
1084         };
1085         udelay(100);
1086 }
1087
1088 void board_init_f(ulong dummy)
1089 {
1090         /* setup AIPS and disable watchdog */
1091         arch_cpu_init();
1092
1093         ccgr_init();
1094         gpr_init();
1095
1096         /* iomux */
1097         board_early_init_f();
1098
1099         /* setup GP timer */
1100         timer_init();
1101
1102         /* UART clocks enabled and gd valid - init serial console */
1103         preloader_console_init();
1104
1105 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
1106         /* Make sure we use dte mode */
1107         setup_dtemode_uart();
1108 #endif
1109
1110         /* DDR initialization */
1111         spl_dram_init();
1112
1113         /* Clear the BSS. */
1114         memset(__bss_start, 0, __bss_end - __bss_start);
1115
1116         /* load/boot image from boot device */
1117         board_init_r(NULL, 0);
1118 }
1119
1120 void reset_cpu(ulong addr)
1121 {
1122 }
1123
1124 #endif /* CONFIG_SPL_BUILD */
1125
1126 static struct mxc_serial_platdata mxc_serial_plat = {
1127         .reg = (struct mxc_uart *)UART1_BASE,
1128         .use_dte = true,
1129 };
1130
1131 U_BOOT_DEVICE(mxc_serial) = {
1132         .name = "serial_mxc",
1133         .platdata = &mxc_serial_plat,
1134 };