board/toradex/apalis_imx6/apalis_imx6.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   5  * Copyright (C) 2014-2019, Toradex AG
   6  * copied from nitrogen6x
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11
  12 #include <ahci.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/crm_regs.h>
  15 #include <asm/arch/imx-regs.h>
  16 #include <asm/arch/mx6-ddr.h>
  17 #include <asm/arch/mx6-pins.h>
  18 #include <asm/arch/mxc_hdmi.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/bootm.h>
  21 #include <asm/gpio.h>
  22 #include <asm/mach-imx/boot_mode.h>
  23 #include <asm/mach-imx/iomux-v3.h>
  24 #include <asm/mach-imx/sata.h>
  25 #include <asm/mach-imx/video.h>
  26 #include <dm/device-internal.h>
  27 #include <dm/platform_data/serial_mxc.h>
  28 #include <dwc_ahsata.h>
  29 #include <environment.h>
  30 #include <fsl_esdhc_imx.h>
  31 #include <imx_thermal.h>
  32 #include <micrel.h>
  33 #include <miiphy.h>
  34 #include <netdev.h>
  35
  36 #include "../common/tdx-cfg-block.h"
  37 #ifdef CONFIG_TDX_CMD_IMX_MFGR
  38 #include "pf0100.h"
  39 #endif
  40
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  44         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  45         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  46
  47 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  48         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |                 \
  49         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  50
  51 #define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP |               \
  52         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  53         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  54
  55 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  56         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  57
  58 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  59         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  60         PAD_CTL_SRE_SLOW)
  61
  62 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  63         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  64         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  65
  66 #define TRISTATE        (PAD_CTL_HYS | PAD_CTL_SPEED_MED)
  67
  68 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
  69
  70 #define APALIS_IMX6_SATA_INIT_RETRIES   10
  71
  72 int dram_init(void)
  73 {
  74         /* use the DDR controllers configured size */
  75         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  76                                     (ulong)imx_ddr_size());
  77
  78         return 0;
  79 }
  80
  81 /* Apalis UART1 */
  82 iomux_v3_cfg_t const uart1_pads_dce[] = {
  83         MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  84         MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  85 };
  86 iomux_v3_cfg_t const uart1_pads_dte[] = {
  87         MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  88         MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  89 };
  90
  91 #if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
  92 /* Apalis MMC1 */
  93 iomux_v3_cfg_t const usdhc1_pads[] = {
  94         MX6_PAD_SD1_CLK__SD1_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  95         MX6_PAD_SD1_CMD__SD1_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  96         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  97         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  98         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  99         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 100         MX6_PAD_NANDF_D0__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 101         MX6_PAD_NANDF_D1__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 102         MX6_PAD_NANDF_D2__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 103         MX6_PAD_NANDF_D3__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 104         MX6_PAD_DI0_PIN4__GPIO4_IO20   | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 105 #       define GPIO_MMC_CD IMX_GPIO_NR(4, 20)
 106 };
 107
 108 /* Apalis SD1 */
 109 iomux_v3_cfg_t const usdhc2_pads[] = {
 110         MX6_PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 111         MX6_PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 112         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 113         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 114         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 115         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 116         MX6_PAD_NANDF_CS1__GPIO6_IO14  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 117 #       define GPIO_SD_CD IMX_GPIO_NR(6, 14)
 118 };
 119
 120 /* eMMC */
 121 iomux_v3_cfg_t const usdhc3_pads[] = {
 122         MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 123         MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 124         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 125         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 126         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 127         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 128         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 129         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 130         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 131         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 132         MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
 133 };
 134 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
 135
 136 int mx6_rgmii_rework(struct phy_device *phydev)
 137 {
 138         /* control data pad skew - devaddr = 0x02, register = 0x04 */
 139         ksz9031_phy_extended_write(phydev, 0x02,
 140                                    MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
 141                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 142         /* rx data pad skew - devaddr = 0x02, register = 0x05 */
 143         ksz9031_phy_extended_write(phydev, 0x02,
 144                                    MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
 145                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 146         /* tx data pad skew - devaddr = 0x02, register = 0x05 */
 147         ksz9031_phy_extended_write(phydev, 0x02,
 148                                    MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
 149                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 150         /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
 151         ksz9031_phy_extended_write(phydev, 0x02,
 152                                    MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
 153                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
 154         return 0;
 155 }
 156
 157 iomux_v3_cfg_t const enet_pads[] = {
 158         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 159         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 160         MX6_PAD_RGMII_TXC__RGMII_TXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 161         MX6_PAD_RGMII_TD0__RGMII_TD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 162         MX6_PAD_RGMII_TD1__RGMII_TD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 163         MX6_PAD_RGMII_TD2__RGMII_TD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 164         MX6_PAD_RGMII_TD3__RGMII_TD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 165         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 166         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 167         MX6_PAD_RGMII_RXC__RGMII_RXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 168         MX6_PAD_RGMII_RD0__RGMII_RD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 169         MX6_PAD_RGMII_RD1__RGMII_RD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 170         MX6_PAD_RGMII_RD2__RGMII_RD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 171         MX6_PAD_RGMII_RD3__RGMII_RD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 172         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 173         /* KSZ9031 PHY Reset */
 174         MX6_PAD_ENET_CRS_DV__GPIO1_IO25         | MUX_PAD_CTRL(NO_PAD_CTRL) |
 175                                                   MUX_MODE_SION,
 176 #       define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25)
 177 };
 178
 179 static void setup_iomux_enet(void)
 180 {
 181         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 182 }
 183
 184 static int reset_enet_phy(struct mii_dev *bus)
 185 {
 186         /* Reset KSZ9031 PHY */
 187         gpio_request(GPIO_ENET_PHY_RESET, "ETH_RESET#");
 188         gpio_direction_output(GPIO_ENET_PHY_RESET, 0);
 189         mdelay(10);
 190         gpio_set_value(GPIO_ENET_PHY_RESET, 1);
 191
 192         return 0;
 193 }
 194
 195 /* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */
 196 iomux_v3_cfg_t const gpio_pads[] = {
 197         /* Apalis GPIO1 - GPIO8 */
 198         MX6_PAD_NANDF_D4__GPIO2_IO04    | MUX_PAD_CTRL(WEAK_PULLUP) |
 199                                           MUX_MODE_SION,
 200         MX6_PAD_NANDF_D5__GPIO2_IO05    | MUX_PAD_CTRL(WEAK_PULLUP) |
 201                                           MUX_MODE_SION,
 202         MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(WEAK_PULLUP) |
 203                                           MUX_MODE_SION,
 204         MX6_PAD_NANDF_D7__GPIO2_IO07    | MUX_PAD_CTRL(WEAK_PULLUP) |
 205                                           MUX_MODE_SION,
 206         MX6_PAD_NANDF_RB0__GPIO6_IO10   | MUX_PAD_CTRL(WEAK_PULLUP) |
 207                                           MUX_MODE_SION,
 208         MX6_PAD_NANDF_WP_B__GPIO6_IO09  | MUX_PAD_CTRL(WEAK_PULLUP) |
 209                                           MUX_MODE_SION,
 210         MX6_PAD_GPIO_2__GPIO1_IO02      | MUX_PAD_CTRL(WEAK_PULLDOWN) |
 211                                           MUX_MODE_SION,
 212         MX6_PAD_GPIO_6__GPIO1_IO06      | MUX_PAD_CTRL(WEAK_PULLUP) |
 213                                           MUX_MODE_SION,
 214         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(WEAK_PULLUP) |
 215                                           MUX_MODE_SION,
 216 };
 217
 218 static void setup_iomux_gpio(void)
 219 {
 220         imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
 221 }
 222
 223 iomux_v3_cfg_t const usb_pads[] = {
 224         /* USBH_EN */
 225         MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 226 #       define GPIO_USBH_EN IMX_GPIO_NR(1, 0)
 227         /* USB_VBUS_DET */
 228         MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
 229 #       define GPIO_USB_VBUS_DET IMX_GPIO_NR(3, 28)
 230         /* USBO1_ID */
 231         MX6_PAD_ENET_RX_ER__USB_OTG_ID  | MUX_PAD_CTRL(WEAK_PULLUP),
 232         /* USBO1_EN */
 233         MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 234 #       define GPIO_USBO_EN IMX_GPIO_NR(3, 22)
 235 };
 236
 237 /*
 238  * UARTs are used in DTE mode, switch the mode on all UARTs before
 239  * any pinmuxing connects a (DCE) output to a transceiver output.
 240  */
 241 #define UCR3            0x88    /* FIFO Control Register */
 242 #define UCR3_RI         BIT(8)  /* RIDELT DTE mode */
 243 #define UCR3_DCD        BIT(9)  /* DCDDELT DTE mode */
 244 #define UFCR            0x90    /* FIFO Control Register */
 245 #define UFCR_DCEDTE     BIT(6)  /* DCE=0 */
 246
 247 static void setup_dtemode_uart(void)
 248 {
 249         setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 250         setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 251         setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
 252         setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
 253
 254         clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
 255         clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
 256         clrbits_le32((u32 *)(UART4_BASE + UCR3), UCR3_DCD | UCR3_RI);
 257         clrbits_le32((u32 *)(UART5_BASE + UCR3), UCR3_DCD | UCR3_RI);
 258 }
 259 static void setup_dcemode_uart(void)
 260 {
 261         clrbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 262         clrbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 263         clrbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
 264         clrbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
 265 }
 266
 267 static void setup_iomux_dte_uart(void)
 268 {
 269         setup_dtemode_uart();
 270         imx_iomux_v3_setup_multiple_pads(uart1_pads_dte,
 271                                          ARRAY_SIZE(uart1_pads_dte));
 272 }
 273 static void setup_iomux_dce_uart(void)
 274 {
 275         setup_dcemode_uart();
 276         imx_iomux_v3_setup_multiple_pads(uart1_pads_dce,
 277                                          ARRAY_SIZE(uart1_pads_dce));
 278 }
 279
 280 #ifdef CONFIG_USB_EHCI_MX6
 281 int board_ehci_hcd_init(int port)
 282 {
 283         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 284         return 0;
 285 }
 286 #endif
 287
 288 #if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
 289 /* use the following sequence: eMMC, MMC1, SD1 */
 290 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
 291         {USDHC3_BASE_ADDR},
 292         {USDHC1_BASE_ADDR},
 293         {USDHC2_BASE_ADDR},
 294 };
 295
 296 int board_mmc_getcd(struct mmc *mmc)
 297 {
 298         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 299         int ret = true; /* default: assume inserted */
 300
 301         switch (cfg->esdhc_base) {
 302         case USDHC1_BASE_ADDR:
 303                 gpio_request(GPIO_MMC_CD, "MMC_CD");
 304                 gpio_direction_input(GPIO_MMC_CD);
 305                 ret = !gpio_get_value(GPIO_MMC_CD);
 306                 break;
 307         case USDHC2_BASE_ADDR:
 308                 gpio_request(GPIO_MMC_CD, "SD_CD");
 309                 gpio_direction_input(GPIO_SD_CD);
 310                 ret = !gpio_get_value(GPIO_SD_CD);
 311                 break;
 312         }
 313
 314         return ret;
 315 }
 316
 317 int board_mmc_init(bd_t *bis)
 318 {
 319         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 320         unsigned reg = readl(&psrc->sbmr1) >> 11;
 321         /*
 322          * Upon reading BOOT_CFG register the following map is done:
 323          * Bit 11 and 12 of BOOT_CFG register can determine the current
 324          * mmc port
 325          * 0x1                  SD1
 326          * 0x2                  SD2
 327          * 0x3                  SD4
 328          */
 329
 330         switch (reg & 0x3) {
 331         case 0x0:
 332                 imx_iomux_v3_setup_multiple_pads(
 333                         usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 334                 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
 335                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 336                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 337                 break;
 338         case 0x1:
 339                 imx_iomux_v3_setup_multiple_pads(
 340                         usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 341                 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
 342                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 343                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 344                 break;
 345         case 0x2:
 346                 imx_iomux_v3_setup_multiple_pads(
 347                         usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 348                 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 349                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 350                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 351                 break;
 352         default:
 353                 puts("MMC boot device not available");
 354         }
 355
 356         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 357 }
 358 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
 359
 360 int board_phy_config(struct phy_device *phydev)
 361 {
 362         mx6_rgmii_rework(phydev);
 363         if (phydev->drv->config)
 364                 phydev->drv->config(phydev);
 365
 366         return 0;
 367 }
 368
 369 int board_eth_init(bd_t *bis)
 370 {
 371         uint32_t base = IMX_FEC_BASE;
 372         struct mii_dev *bus = NULL;
 373         struct phy_device *phydev = NULL;
 374         int ret;
 375
 376         setup_iomux_enet();
 377
 378 #ifdef CONFIG_FEC_MXC
 379         bus = fec_get_miibus(base, -1);
 380         if (!bus)
 381                 return 0;
 382
 383         bus->reset = reset_enet_phy;
 384         /* scan PHY 4,5,6,7 */
 385         phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
 386         if (!phydev) {
 387                 free(bus);
 388                 puts("no PHY found\n");
 389                 return 0;
 390         }
 391
 392         printf("using PHY at %d\n", phydev->addr);
 393         ret = fec_probe(bis, -1, base, bus, phydev);
 394         if (ret) {
 395                 printf("FEC MXC: %s:failed\n", __func__);
 396                 free(phydev);
 397                 free(bus);
 398         }
 399 #endif /* CONFIG_FEC_MXC */
 400
 401         return 0;
 402 }
 403
 404 static iomux_v3_cfg_t const pwr_intb_pads[] = {
 405         /*
 406          * the bootrom sets the iomux to vselect, potentially connecting
 407          * two outputs. Set this back to GPIO
 408          */
 409         MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
 410 };
 411
 412 #if defined(CONFIG_VIDEO_IPUV3)
 413
 414 static iomux_v3_cfg_t const backlight_pads[] = {
 415         /* Backlight on RGB connector: J15 */
 416         MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 417                                        MUX_MODE_SION,
 418 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13)
 419         /* additional CPU pin on BKL_PWM, keep in tristate */
 420         MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE),
 421         /* Backlight PWM, used as GPIO in U-Boot */
 422         MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 423                                        MUX_MODE_SION,
 424 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10)
 425         /* buffer output enable 0: buffer enabled */
 426         MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
 427 #define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2)
 428         /* PSAVE# integrated VDAC */
 429         MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 430                                        MUX_MODE_SION,
 431 #define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31)
 432 };
 433
 434 static iomux_v3_cfg_t const rgb_pads[] = {
 435         MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
 436         MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
 437         MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
 438         MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
 439         MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
 440         MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
 441         MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
 442         MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
 443         MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
 444         MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
 445         MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
 446         MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
 447         MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
 448         MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
 449         MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
 450         MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
 451         MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
 452         MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
 453         MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
 454         MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
 455         MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
 456         MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
 457         MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 | MUX_PAD_CTRL(OUTPUT_RGB),
 458         MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 | MUX_PAD_CTRL(OUTPUT_RGB),
 459         MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 | MUX_PAD_CTRL(OUTPUT_RGB),
 460         MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 | MUX_PAD_CTRL(OUTPUT_RGB),
 461         MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 | MUX_PAD_CTRL(OUTPUT_RGB),
 462         MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 | MUX_PAD_CTRL(OUTPUT_RGB),
 463 };
 464
 465 static void do_enable_hdmi(struct display_info_t const *dev)
 466 {
 467         imx_enable_hdmi_phy();
 468 }
 469
 470 static void enable_lvds(struct display_info_t const *dev)
 471 {
 472         struct iomuxc *iomux = (struct iomuxc *)
 473                                 IOMUXC_BASE_ADDR;
 474         u32 reg = readl(&iomux->gpr[2]);
 475         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 476         writel(reg, &iomux->gpr[2]);
 477         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 478         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 479         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 480 }
 481
 482 static void enable_rgb(struct display_info_t const *dev)
 483 {
 484         imx_iomux_v3_setup_multiple_pads(
 485                 rgb_pads,
 486                 ARRAY_SIZE(rgb_pads));
 487         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 488         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 489         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 490 }
 491
 492 static int detect_default(struct display_info_t const *dev)
 493 {
 494         (void) dev;
 495         return 1;
 496 }
 497
 498 struct display_info_t const displays[] = {{
 499         .bus    = -1,
 500         .addr   = 0,
 501         .pixfmt = IPU_PIX_FMT_RGB24,
 502         .detect = detect_hdmi,
 503         .enable = do_enable_hdmi,
 504         .mode   = {
 505                 .name           = "HDMI",
 506                 .refresh        = 60,
 507                 .xres           = 1024,
 508                 .yres           = 768,
 509                 .pixclock       = 15385,
 510                 .left_margin    = 220,
 511                 .right_margin   = 40,
 512                 .upper_margin   = 21,
 513                 .lower_margin   = 7,
 514                 .hsync_len      = 60,
 515                 .vsync_len      = 10,
 516                 .sync           = FB_SYNC_EXT,
 517                 .vmode          = FB_VMODE_NONINTERLACED
 518 } }, {
 519         .bus    = -1,
 520         .addr   = 0,
 521         .di     = 1,
 522         .pixfmt = IPU_PIX_FMT_RGB24,
 523         .detect = detect_default,
 524         .enable = enable_rgb,
 525         .mode   = {
 526                 .name           = "vga-rgb",
 527                 .refresh        = 60,
 528                 .xres           = 640,
 529                 .yres           = 480,
 530                 .pixclock       = 33000,
 531                 .left_margin    = 48,
 532                 .right_margin   = 16,
 533                 .upper_margin   = 31,
 534                 .lower_margin   = 11,
 535                 .hsync_len      = 96,
 536                 .vsync_len      = 2,
 537                 .sync           = 0,
 538                 .vmode          = FB_VMODE_NONINTERLACED
 539 } }, {
 540         .bus    = -1,
 541         .addr   = 0,
 542         .di     = 1,
 543         .pixfmt = IPU_PIX_FMT_RGB24,
 544         .enable = enable_rgb,
 545         .mode   = {
 546                 .name           = "wvga-rgb",
 547                 .refresh        = 60,
 548                 .xres           = 800,
 549                 .yres           = 480,
 550                 .pixclock       = 25000,
 551                 .left_margin    = 40,
 552                 .right_margin   = 88,
 553                 .upper_margin   = 33,
 554                 .lower_margin   = 10,
 555                 .hsync_len      = 128,
 556                 .vsync_len      = 2,
 557                 .sync           = 0,
 558                 .vmode          = FB_VMODE_NONINTERLACED
 559 } }, {
 560         .bus    = -1,
 561         .addr   = 0,
 562         .pixfmt = IPU_PIX_FMT_LVDS666,
 563         .enable = enable_lvds,
 564         .mode   = {
 565                 .name           = "wsvga-lvds",
 566                 .refresh        = 60,
 567                 .xres           = 1024,
 568                 .yres           = 600,
 569                 .pixclock       = 15385,
 570                 .left_margin    = 220,
 571                 .right_margin   = 40,
 572                 .upper_margin   = 21,
 573                 .lower_margin   = 7,
 574                 .hsync_len      = 60,
 575                 .vsync_len      = 10,
 576                 .sync           = FB_SYNC_EXT,
 577                 .vmode          = FB_VMODE_NONINTERLACED
 578 } } };
 579 size_t display_count = ARRAY_SIZE(displays);
 580
 581 static void setup_display(void)
 582 {
 583         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 584         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 585         int reg;
 586
 587         enable_ipu_clock();
 588         imx_setup_hdmi();
 589         /* Turn on LDB0,IPU,IPU DI0 clocks */
 590         reg = __raw_readl(&mxc_ccm->CCGR3);
 591         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 592         writel(reg, &mxc_ccm->CCGR3);
 593
 594         /* set LDB0, LDB1 clk select to 011/011 */
 595         reg = readl(&mxc_ccm->cs2cdr);
 596         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 597                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 598         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 599               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 600         writel(reg, &mxc_ccm->cs2cdr);
 601
 602         reg = readl(&mxc_ccm->cscmr2);
 603         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 604         writel(reg, &mxc_ccm->cscmr2);
 605
 606         reg = readl(&mxc_ccm->chsccdr);
 607         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 608                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 609         writel(reg, &mxc_ccm->chsccdr);
 610
 611         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 612              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 613              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 614              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 615              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 616              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 617              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 618              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 619              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 620         writel(reg, &iomux->gpr[2]);
 621
 622         reg = readl(&iomux->gpr[3]);
 623         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 624                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 625             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 626                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 627         writel(reg, &iomux->gpr[3]);
 628
 629         /* backlight unconditionally on for now */
 630         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 631                                          ARRAY_SIZE(backlight_pads));
 632         /* use 0 for EDT 7", use 1 for LG fullHD panel */
 633         gpio_request(RGB_BACKLIGHTPWM_GP, "BKL1_PWM");
 634         gpio_request(RGB_BACKLIGHTPWM_OE, "BKL1_PWM_EN");
 635         gpio_request(RGB_BACKLIGHT_GP, "BKL1_ON");
 636         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 637         gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
 638         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 639 }
 640
 641 /*
 642  * Backlight off before OS handover
 643  */
 644 void board_preboot_os(void)
 645 {
 646         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
 647         gpio_direction_output(RGB_BACKLIGHT_GP, 0);
 648 }
 649 #endif /* defined(CONFIG_VIDEO_IPUV3) */
 650
 651 int board_early_init_f(void)
 652 {
 653         imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
 654                                          ARRAY_SIZE(pwr_intb_pads));
 655 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
 656         setup_iomux_dte_uart();
 657 #else
 658         setup_iomux_dce_uart();
 659 #endif
 660         return 0;
 661 }
 662
 663 /*
 664  * Do not overwrite the console
 665  * Use always serial for U-Boot console
 666  */
 667 int overwrite_console(void)
 668 {
 669         return 1;
 670 }
 671
 672 int board_init(void)
 673 {
 674         /* address of boot parameters */
 675         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 676
 677 #if defined(CONFIG_VIDEO_IPUV3)
 678         setup_display();
 679 #endif
 680
 681 #ifdef CONFIG_TDX_CMD_IMX_MFGR
 682         (void) pmic_init();
 683 #endif
 684
 685 #ifdef CONFIG_SATA
 686         setup_sata();
 687 #endif
 688
 689         setup_iomux_gpio();
 690
 691         return 0;
 692 }
 693
 694 #ifdef CONFIG_BOARD_LATE_INIT
 695 int board_late_init(void)
 696 {
 697 #if defined(CONFIG_REVISION_TAG) && \
 698     defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
 699         char env_str[256];
 700         u32 rev;
 701
 702         rev = get_board_rev();
 703         snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
 704         env_set("board_rev", env_str);
 705
 706 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
 707         if ((rev & 0xfff0) == 0x0100) {
 708                 char *fdt_env;
 709
 710                 /* reconfigure the UART to DCE mode dynamically if on V1.0 HW */
 711                 setup_iomux_dce_uart();
 712
 713                 /* if using the default device tree, use version for V1.0 HW */
 714                 fdt_env = env_get("fdt_file");
 715                 if ((fdt_env != NULL) && (strcmp(FDT_FILE, fdt_env) == 0)) {
 716                         env_set("fdt_file", FDT_FILE_V1_0);
 717                         printf("patching fdt_file to " FDT_FILE_V1_0 "\n");
 718 #ifndef CONFIG_ENV_IS_NOWHERE
 719                         env_save();
 720 #endif
 721                 }
 722         }
 723 #endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */
 724 #endif /* CONFIG_REVISION_TAG */
 725
 726 #ifdef CONFIG_CMD_USB_SDP
 727         if (is_boot_from_usb()) {
 728                 printf("Serial Downloader recovery mode, using sdp command\n");
 729                 env_set("bootdelay", "0");
 730                 env_set("bootcmd", "sdp 0");
 731         }
 732 #endif /* CONFIG_CMD_USB_SDP */
 733
 734         return 0;
 735 }
 736 #endif /* CONFIG_BOARD_LATE_INIT */
 737
 738 int checkboard(void)
 739 {
 740         char it[] = " IT";
 741         int minc, maxc;
 742
 743         switch (get_cpu_temp_grade(&minc, &maxc)) {
 744         case TEMP_AUTOMOTIVE:
 745         case TEMP_INDUSTRIAL:
 746                 break;
 747         case TEMP_EXTCOMMERCIAL:
 748         default:
 749                 it[0] = 0;
 750         };
 751         printf("Model: Toradex Apalis iMX6 %s %s%s\n",
 752                is_cpu_type(MXC_CPU_MX6D) ? "Dual" : "Quad",
 753                (gd->ram_size == 0x80000000) ? "2GB" :
 754                (gd->ram_size == 0x40000000) ? "1GB" : "512MB", it);
 755         return 0;
 756 }
 757
 758 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 759 int ft_board_setup(void *blob, bd_t *bd)
 760 {
 761         return ft_common_board_setup(blob, bd);
 762 }
 763 #endif
 764
 765 #ifdef CONFIG_CMD_BMODE
 766 static const struct boot_mode board_boot_modes[] = {
 767         /* 4-bit bus width */
 768         {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 769         {"sd",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 770         {NULL,  0},
 771 };
 772 #endif
 773
 774 int misc_init_r(void)
 775 {
 776 #ifdef CONFIG_CMD_BMODE
 777         add_board_boot_modes(board_boot_modes);
 778 #endif
 779         return 0;
 780 }
 781
 782 #ifdef CONFIG_LDO_BYPASS_CHECK
 783 /* TODO, use external pmic, for now always ldo_enable */
 784 void ldo_mode_set(int ldo_bypass)
 785 {
 786         return;
 787 }
 788 #endif
 789
 790 #ifdef CONFIG_SPL_BUILD
 791 #include <spl.h>
 792 #include <linux/libfdt.h>
 793 #include "asm/arch/mx6q-ddr.h"
 794 #include "asm/arch/iomux.h"
 795 #include "asm/arch/crm_regs.h"
 796
 797 static int mx6_com_dcd_table[] = {
 798 /* ddr-setup.cfg */
 799 MX6_IOM_DRAM_SDQS0, 0x00000030,
 800 MX6_IOM_DRAM_SDQS1, 0x00000030,
 801 MX6_IOM_DRAM_SDQS2, 0x00000030,
 802 MX6_IOM_DRAM_SDQS3, 0x00000030,
 803 MX6_IOM_DRAM_SDQS4, 0x00000030,
 804 MX6_IOM_DRAM_SDQS5, 0x00000030,
 805 MX6_IOM_DRAM_SDQS6, 0x00000030,
 806 MX6_IOM_DRAM_SDQS7, 0x00000030,
 807
 808 MX6_IOM_GRP_B0DS, 0x00000030,
 809 MX6_IOM_GRP_B1DS, 0x00000030,
 810 MX6_IOM_GRP_B2DS, 0x00000030,
 811 MX6_IOM_GRP_B3DS, 0x00000030,
 812 MX6_IOM_GRP_B4DS, 0x00000030,
 813 MX6_IOM_GRP_B5DS, 0x00000030,
 814 MX6_IOM_GRP_B6DS, 0x00000030,
 815 MX6_IOM_GRP_B7DS, 0x00000030,
 816 MX6_IOM_GRP_ADDDS, 0x00000030,
 817 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 818 MX6_IOM_GRP_CTLDS, 0x00000030,
 819
 820 MX6_IOM_DRAM_DQM0, 0x00020030,
 821 MX6_IOM_DRAM_DQM1, 0x00020030,
 822 MX6_IOM_DRAM_DQM2, 0x00020030,
 823 MX6_IOM_DRAM_DQM3, 0x00020030,
 824 MX6_IOM_DRAM_DQM4, 0x00020030,
 825 MX6_IOM_DRAM_DQM5, 0x00020030,
 826 MX6_IOM_DRAM_DQM6, 0x00020030,
 827 MX6_IOM_DRAM_DQM7, 0x00020030,
 828
 829 MX6_IOM_DRAM_CAS, 0x00020030,
 830 MX6_IOM_DRAM_RAS, 0x00020030,
 831 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 832 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 833
 834 MX6_IOM_DRAM_RESET, 0x00020030,
 835 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 836 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 837
 838 MX6_IOM_DRAM_SDODT0, 0x00003030,
 839 MX6_IOM_DRAM_SDODT1, 0x00003030,
 840
 841 /* (differential input) */
 842 MX6_IOM_DDRMODE_CTL, 0x00020000,
 843 /* (differential input) */
 844 MX6_IOM_GRP_DDRMODE, 0x00020000,
 845 /* disable ddr pullups */
 846 MX6_IOM_GRP_DDRPKE, 0x00000000,
 847 MX6_IOM_DRAM_SDBA2, 0x00000000,
 848 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 849 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 850
 851 /* Read data DQ Byte0-3 delay */
 852 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 853 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 854 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 855 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 856 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 857 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 858 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 859 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 860
 861 /*
 862  * MDMISC       mirroring       interleaved (row/bank/col)
 863  */
 864 MX6_MMDC_P0_MDMISC, 0x00081740,
 865
 866 /*
 867  * MDSCR        con_req
 868  */
 869 MX6_MMDC_P0_MDSCR, 0x00008000,
 870
 871 /* 1066mhz_4x128mx16.cfg */
 872
 873 MX6_MMDC_P0_MDPDC, 0x00020036,
 874 MX6_MMDC_P0_MDCFG0, 0x555A7954,
 875 MX6_MMDC_P0_MDCFG1, 0xDB328F64,
 876 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 877 MX6_MMDC_P0_MDRWD, 0x000026D2,
 878 MX6_MMDC_P0_MDOR, 0x005A1023,
 879 MX6_MMDC_P0_MDOTC, 0x09555050,
 880 MX6_MMDC_P0_MDPDC, 0x00025576,
 881 MX6_MMDC_P0_MDASP, 0x00000027,
 882 MX6_MMDC_P0_MDCTL, 0x831A0000,
 883 MX6_MMDC_P0_MDSCR, 0x04088032,
 884 MX6_MMDC_P0_MDSCR, 0x00008033,
 885 MX6_MMDC_P0_MDSCR, 0x00428031,
 886 MX6_MMDC_P0_MDSCR, 0x19308030,
 887 MX6_MMDC_P0_MDSCR, 0x04008040,
 888 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
 889 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
 890 MX6_MMDC_P0_MDREF, 0x00005800,
 891 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
 892 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
 893
 894 MX6_MMDC_P0_MPDGCTRL0, 0x432A0338,
 895 MX6_MMDC_P0_MPDGCTRL1, 0x03260324,
 896 MX6_MMDC_P1_MPDGCTRL0, 0x43340344,
 897 MX6_MMDC_P1_MPDGCTRL1, 0x031E027C,
 898
 899 MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E,
 900 MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37,
 901
 902 MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C,
 903 MX6_MMDC_P1_MPWRDLCTL, 0x4336453F,
 904
 905 MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
 906 MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
 907 MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
 908 MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
 909
 910 MX6_MMDC_P0_MPMUR0, 0x00000800,
 911 MX6_MMDC_P1_MPMUR0, 0x00000800,
 912 MX6_MMDC_P0_MDSCR, 0x00000000,
 913 MX6_MMDC_P0_MAPSR, 0x00011006,
 914 };
 915
 916 static int mx6_it_dcd_table[] = {
 917 /* ddr-setup.cfg */
 918 MX6_IOM_DRAM_SDQS0, 0x00000030,
 919 MX6_IOM_DRAM_SDQS1, 0x00000030,
 920 MX6_IOM_DRAM_SDQS2, 0x00000030,
 921 MX6_IOM_DRAM_SDQS3, 0x00000030,
 922 MX6_IOM_DRAM_SDQS4, 0x00000030,
 923 MX6_IOM_DRAM_SDQS5, 0x00000030,
 924 MX6_IOM_DRAM_SDQS6, 0x00000030,
 925 MX6_IOM_DRAM_SDQS7, 0x00000030,
 926
 927 MX6_IOM_GRP_B0DS, 0x00000030,
 928 MX6_IOM_GRP_B1DS, 0x00000030,
 929 MX6_IOM_GRP_B2DS, 0x00000030,
 930 MX6_IOM_GRP_B3DS, 0x00000030,
 931 MX6_IOM_GRP_B4DS, 0x00000030,
 932 MX6_IOM_GRP_B5DS, 0x00000030,
 933 MX6_IOM_GRP_B6DS, 0x00000030,
 934 MX6_IOM_GRP_B7DS, 0x00000030,
 935 MX6_IOM_GRP_ADDDS, 0x00000030,
 936 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 937 MX6_IOM_GRP_CTLDS, 0x00000030,
 938
 939 MX6_IOM_DRAM_DQM0, 0x00020030,
 940 MX6_IOM_DRAM_DQM1, 0x00020030,
 941 MX6_IOM_DRAM_DQM2, 0x00020030,
 942 MX6_IOM_DRAM_DQM3, 0x00020030,
 943 MX6_IOM_DRAM_DQM4, 0x00020030,
 944 MX6_IOM_DRAM_DQM5, 0x00020030,
 945 MX6_IOM_DRAM_DQM6, 0x00020030,
 946 MX6_IOM_DRAM_DQM7, 0x00020030,
 947
 948 MX6_IOM_DRAM_CAS, 0x00020030,
 949 MX6_IOM_DRAM_RAS, 0x00020030,
 950 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 951 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 952
 953 MX6_IOM_DRAM_RESET, 0x00020030,
 954 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 955 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 956
 957 MX6_IOM_DRAM_SDODT0, 0x00003030,
 958 MX6_IOM_DRAM_SDODT1, 0x00003030,
 959
 960 /* (differential input) */
 961 MX6_IOM_DDRMODE_CTL, 0x00020000,
 962 /* (differential input) */
 963 MX6_IOM_GRP_DDRMODE, 0x00020000,
 964 /* disable ddr pullups */
 965 MX6_IOM_GRP_DDRPKE, 0x00000000,
 966 MX6_IOM_DRAM_SDBA2, 0x00000000,
 967 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 968 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 969
 970 /* Read data DQ Byte0-3 delay */
 971 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 972 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 973 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 974 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 975 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 976 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 977 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 978 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 979
 980 /*
 981  * MDMISC       mirroring       interleaved (row/bank/col)
 982  */
 983 MX6_MMDC_P0_MDMISC, 0x00081740,
 984
 985 /*
 986  * MDSCR        con_req
 987  */
 988 MX6_MMDC_P0_MDSCR, 0x00008000,
 989
 990 /* 1066mhz_4x256mx16.cfg */
 991
 992 MX6_MMDC_P0_MDPDC, 0x00020036,
 993 MX6_MMDC_P0_MDCFG0, 0x898E78f5,
 994 MX6_MMDC_P0_MDCFG1, 0xff328f64,
 995 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 996 MX6_MMDC_P0_MDRWD, 0x000026D2,
 997 MX6_MMDC_P0_MDOR, 0x008E1023,
 998 MX6_MMDC_P0_MDOTC, 0x09444040,
 999 MX6_MMDC_P0_MDPDC, 0x00025576,
1000 MX6_MMDC_P0_MDASP, 0x00000047,
1001 MX6_MMDC_P0_MDCTL, 0x841A0000,
1002 MX6_MMDC_P0_MDSCR, 0x02888032,
1003 MX6_MMDC_P0_MDSCR, 0x00008033,
1004 MX6_MMDC_P0_MDSCR, 0x00048031,
1005 MX6_MMDC_P0_MDSCR, 0x19408030,
1006 MX6_MMDC_P0_MDSCR, 0x04008040,
1007 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
1008 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
1009 MX6_MMDC_P0_MDREF, 0x00007800,
1010 MX6_MMDC_P0_MPODTCTRL, 0x00022227,
1011 MX6_MMDC_P1_MPODTCTRL, 0x00022227,
1012
1013 MX6_MMDC_P0_MPDGCTRL0, 0x03300338,
1014 MX6_MMDC_P0_MPDGCTRL1, 0x03240324,
1015 MX6_MMDC_P1_MPDGCTRL0, 0x03440350,
1016 MX6_MMDC_P1_MPDGCTRL1, 0x032C0308,
1017
1018 MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E,
1019 MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46,
1020
1021 MX6_MMDC_P0_MPWRDLCTL, 0x403E463E,
1022 MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46,
1023
1024 MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
1025 MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
1026 MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
1027 MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
1028
1029 MX6_MMDC_P0_MPMUR0, 0x00000800,
1030 MX6_MMDC_P1_MPMUR0, 0x00000800,
1031 MX6_MMDC_P0_MDSCR, 0x00000000,
1032 MX6_MMDC_P0_MAPSR, 0x00011006,
1033 };
1034
1035 static void ccgr_init(void)
1036 {
1037         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1038
1039         writel(0x00C03F3F, &ccm->CCGR0);
1040         writel(0x0030FC03, &ccm->CCGR1);
1041         writel(0x0FFFFFF3, &ccm->CCGR2);
1042         writel(0x3FF0300F, &ccm->CCGR3);
1043         writel(0x00FFF300, &ccm->CCGR4);
1044         writel(0x0F0000F3, &ccm->CCGR5);
1045         writel(0x000003FF, &ccm->CCGR6);
1046
1047 /*
1048  * Setup CCM_CCOSR register as follows:
1049  *
1050  * cko1_en  = 1    --> CKO1 enabled
1051  * cko1_div = 111  --> divide by 8
1052  * cko1_sel = 1011 --> ahb_clk_root
1053  *
1054  * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
1055  */
1056         writel(0x000000FB, &ccm->ccosr);
1057 }
1058
1059 static void ddr_init(int *table, int size)
1060 {
1061         int i;
1062
1063         for (i = 0; i < size / 2 ; i++)
1064                 writel(table[2 * i + 1], table[2 * i]);
1065 }
1066
1067 static void spl_dram_init(void)
1068 {
1069         int minc, maxc;
1070
1071         switch (get_cpu_temp_grade(&minc, &maxc)) {
1072         case TEMP_COMMERCIAL:
1073         case TEMP_EXTCOMMERCIAL:
1074                 puts("Commercial temperature grade DDR3 timings.\n");
1075                 ddr_init(mx6_com_dcd_table, ARRAY_SIZE(mx6_com_dcd_table));
1076                 break;
1077         case TEMP_INDUSTRIAL:
1078         case TEMP_AUTOMOTIVE:
1079         default:
1080                 puts("Industrial temperature grade DDR3 timings.\n");
1081                 ddr_init(mx6_it_dcd_table, ARRAY_SIZE(mx6_it_dcd_table));
1082                 break;
1083         };
1084         udelay(100);
1085 }
1086
1087 void board_init_f(ulong dummy)
1088 {
1089         /* setup AIPS and disable watchdog */
1090         arch_cpu_init();
1091
1092         ccgr_init();
1093         gpr_init();
1094
1095         /* iomux */
1096         board_early_init_f();
1097
1098         /* setup GP timer */
1099         timer_init();
1100
1101         /* UART clocks enabled and gd valid - init serial console */
1102         preloader_console_init();
1103
1104 #ifndef CONFIG_TDX_APALIS_IMX6_V1_0
1105         /* Make sure we use dte mode */
1106         setup_dtemode_uart();
1107 #endif
1108
1109         /* DDR initialization */
1110         spl_dram_init();
1111
1112         /* Clear the BSS. */
1113         memset(__bss_start, 0, __bss_end - __bss_start);
1114
1115         /* load/boot image from boot device */
1116         board_init_r(NULL, 0);
1117 }
1118
1119 void reset_cpu(ulong addr)
1120 {
1121 }
1122
1123 #endif /* CONFIG_SPL_BUILD */
1124
1125 static struct mxc_serial_platdata mxc_serial_plat = {
1126         .reg = (struct mxc_uart *)UART1_BASE,
1127         .use_dte = true,
1128 };
1129
1130 U_BOOT_DEVICE(mxc_serial) = {
1131         .name = "serial_mxc",
1132         .platdata = &mxc_serial_plat,
1133 };