board/toradex/apalis-tk1/as3722_init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2012-2016 Toradex, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <asm/io.h>
   8 #include <asm/arch-tegra/tegra_i2c.h>
   9 #include "as3722_init.h"
  10
  11 /* AS3722-PMIC-specific early init code - get CPU rails up, etc */
  12
  13 void tegra_i2c_ll_write_addr(uint addr, uint config)
  14 {
  15         struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
  16
  17         writel(addr, &reg->cmd_addr0);
  18         writel(config, &reg->cnfg);
  19 }
  20
  21 void tegra_i2c_ll_write_data(uint data, uint config)
  22 {
  23         struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
  24
  25         writel(data, &reg->cmd_data1);
  26         writel(config, &reg->cnfg);
  27 }
  28
  29 void pmic_enable_cpu_vdd(void)
  30 {
  31         debug("%s entry\n", __func__);
  32
  33 #ifdef AS3722_SD1VOLTAGE_DATA
  34         /* Set up VDD_CORE, for boards where OTP is incorrect*/
  35         debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);
  36         /* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */
  37         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  38         tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES);
  39         /*
  40          * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
  41          * tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES);
  42          */
  43         udelay(10 * 1000);
  44 #endif
  45
  46         /*
  47          * Make sure all non-fused regulators are down.
  48          * That way we're in known state after software reboot from linux
  49          */
  50         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  51         tegra_i2c_ll_write_data(0x0003, I2C_SEND_2_BYTES);
  52         udelay(10 * 1000);
  53         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  54         tegra_i2c_ll_write_data(0x0004, I2C_SEND_2_BYTES);
  55         udelay(10 * 1000);
  56         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  57         tegra_i2c_ll_write_data(0x001b, I2C_SEND_2_BYTES);
  58         udelay(10 * 1000);
  59         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  60         tegra_i2c_ll_write_data(0x0014, I2C_SEND_2_BYTES);
  61         udelay(10 * 1000);
  62         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  63         tegra_i2c_ll_write_data(0x001a, I2C_SEND_2_BYTES);
  64         udelay(10 * 1000);
  65         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  66         tegra_i2c_ll_write_data(0x0019, I2C_SEND_2_BYTES);
  67         udelay(10 * 1000);
  68
  69         debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
  70         /*
  71          * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
  72          * First set VDD to 1.0V, then enable the VDD regulator.
  73          */
  74         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  75         tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
  76         /*
  77          * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
  78          * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
  79          */
  80         udelay(10 * 1000);
  81
  82         debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);
  83         /*
  84          * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
  85          * First set VDD to 1.0V, then enable the VDD regulator.
  86          */
  87         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  88         tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
  89         /*
  90          * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
  91          * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
  92          */
  93         udelay(10 * 1000);
  94
  95         debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);
  96         /*
  97          * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
  98          * First set VDD to 1.2V, then enable the VDD regulator.
  99          */
 100         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
 101         tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
 102         /*
 103          * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
 104          * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
 105          */
 106         udelay(10 * 1000);
 107
 108         debug("%s: Set VDD_SDMMC1 to 3.3V via AS3722 reg 0x11/4E\n", __func__);
 109         /*
 110          * Bring up VDD_SDMMC1 via the AS3722 PMIC on the PWR I2C bus.
 111          * First set it to value closest to 3.3V, then enable the regulator
 112          *
 113          * NOTE: We do this early because doing it later seems to hose the CPU
 114          * power rail/partition startup. Need to debug.
 115          */
 116         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
 117         tegra_i2c_ll_write_data(AS3722_LDO1VOLTAGE_DATA, I2C_SEND_2_BYTES);
 118         /*
 119          * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
 120          * tegra_i2c_ll_write_data(AS3722_LDO1CONTROL_DATA, I2C_SEND_2_BYTES);
 121          */
 122         udelay(10 * 1000);
 123
 124         debug("%s: Set VDD_SDMMC3 to 3.3V via AS3722 reg 0x16/4E\n", __func__);
 125         /*
 126          * Bring up VDD_SDMMC3 via the AS3722 PMIC on the PWR I2C bus.
 127          * First set it to bypass 3.3V straight thru, then enable the regulator
 128          *
 129          * NOTE: We do this early because doing it later seems to hose the CPU
 130          * power rail/partition startup. Need to debug.
 131          */
 132         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
 133         tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
 134         /*
 135          * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
 136          * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
 137          */
 138         udelay(10 * 1000);
 139 }