board/toradex/apalis-tk1/as3722_init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2012-2016 Toradex, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <log.h>
   8 #include <asm/io.h>
   9 #include <asm/arch-tegra/tegra_i2c.h>
  10 #include <linux/delay.h>
  11 #include "as3722_init.h"
  12
  13 /* AS3722-PMIC-specific early init code - get CPU rails up, etc */
  14
  15 void tegra_i2c_ll_write_addr(uint addr, uint config)
  16 {
  17         struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
  18
  19         writel(addr, &reg->cmd_addr0);
  20         writel(config, &reg->cnfg);
  21 }
  22
  23 void tegra_i2c_ll_write_data(uint data, uint config)
  24 {
  25         struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
  26
  27         writel(data, &reg->cmd_data1);
  28         writel(config, &reg->cnfg);
  29 }
  30
  31 void pmic_enable_cpu_vdd(void)
  32 {
  33         debug("%s entry\n", __func__);
  34
  35 #ifdef AS3722_SD1VOLTAGE_DATA
  36         /* Set up VDD_CORE, for boards where OTP is incorrect*/
  37         debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);
  38         /* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */
  39         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  40         tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES);
  41         /*
  42          * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
  43          * tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES);
  44          */
  45         udelay(10 * 1000);
  46 #endif
  47
  48         /*
  49          * Make sure all non-fused regulators are down.
  50          * That way we're in known state after software reboot from linux
  51          */
  52         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  53         tegra_i2c_ll_write_data(0x0003, I2C_SEND_2_BYTES);
  54         udelay(10 * 1000);
  55         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  56         tegra_i2c_ll_write_data(0x0004, I2C_SEND_2_BYTES);
  57         udelay(10 * 1000);
  58         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  59         tegra_i2c_ll_write_data(0x001b, I2C_SEND_2_BYTES);
  60         udelay(10 * 1000);
  61         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  62         tegra_i2c_ll_write_data(0x0014, I2C_SEND_2_BYTES);
  63         udelay(10 * 1000);
  64         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  65         tegra_i2c_ll_write_data(0x001a, I2C_SEND_2_BYTES);
  66         udelay(10 * 1000);
  67         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  68         tegra_i2c_ll_write_data(0x0019, I2C_SEND_2_BYTES);
  69         udelay(10 * 1000);
  70
  71         debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
  72         /*
  73          * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
  74          * First set VDD to 1.0V, then enable the VDD regulator.
  75          */
  76         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  77         tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
  78         /*
  79          * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
  80          * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
  81          */
  82         udelay(10 * 1000);
  83
  84         debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);
  85         /*
  86          * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
  87          * First set VDD to 1.0V, then enable the VDD regulator.
  88          */
  89         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  90         tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
  91         /*
  92          * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
  93          * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
  94          */
  95         udelay(10 * 1000);
  96
  97         debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);
  98         /*
  99          * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
 100          * First set VDD to 1.2V, then enable the VDD regulator.
 101          */
 102         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
 103         tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
 104         /*
 105          * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
 106          * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
 107          */
 108         udelay(10 * 1000);
 109
 110         debug("%s: Set VDD_SDMMC1 to 3.3V via AS3722 reg 0x11/4E\n", __func__);
 111         /*
 112          * Bring up VDD_SDMMC1 via the AS3722 PMIC on the PWR I2C bus.
 113          * First set it to value closest to 3.3V, then enable the regulator
 114          *
 115          * NOTE: We do this early because doing it later seems to hose the CPU
 116          * power rail/partition startup. Need to debug.
 117          */
 118         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
 119         tegra_i2c_ll_write_data(AS3722_LDO1VOLTAGE_DATA, I2C_SEND_2_BYTES);
 120         /*
 121          * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
 122          * tegra_i2c_ll_write_data(AS3722_LDO1CONTROL_DATA, I2C_SEND_2_BYTES);
 123          */
 124         udelay(10 * 1000);
 125
 126         debug("%s: Set VDD_SDMMC3 to 3.3V via AS3722 reg 0x16/4E\n", __func__);
 127         /*
 128          * Bring up VDD_SDMMC3 via the AS3722 PMIC on the PWR I2C bus.
 129          * First set it to bypass 3.3V straight thru, then enable the regulator
 130          *
 131          * NOTE: We do this early because doing it later seems to hose the CPU
 132          * power rail/partition startup. Need to debug.
 133          */
 134         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
 135         tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
 136         /*
 137          * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
 138          * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
 139          */
 140         udelay(10 * 1000);
 141 }