board/toradex/apalis-tk1/as3722_init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2012-2016 Toradex, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <log.h>
   8 #include <asm/io.h>
   9 #include <asm/arch-tegra/tegra_i2c.h>
  10 #include "as3722_init.h"
  11
  12 /* AS3722-PMIC-specific early init code - get CPU rails up, etc */
  13
  14 void tegra_i2c_ll_write_addr(uint addr, uint config)
  15 {
  16         struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
  17
  18         writel(addr, &reg->cmd_addr0);
  19         writel(config, &reg->cnfg);
  20 }
  21
  22 void tegra_i2c_ll_write_data(uint data, uint config)
  23 {
  24         struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
  25
  26         writel(data, &reg->cmd_data1);
  27         writel(config, &reg->cnfg);
  28 }
  29
  30 void pmic_enable_cpu_vdd(void)
  31 {
  32         debug("%s entry\n", __func__);
  33
  34 #ifdef AS3722_SD1VOLTAGE_DATA
  35         /* Set up VDD_CORE, for boards where OTP is incorrect*/
  36         debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);
  37         /* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */
  38         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  39         tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES);
  40         /*
  41          * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
  42          * tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES);
  43          */
  44         udelay(10 * 1000);
  45 #endif
  46
  47         /*
  48          * Make sure all non-fused regulators are down.
  49          * That way we're in known state after software reboot from linux
  50          */
  51         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  52         tegra_i2c_ll_write_data(0x0003, I2C_SEND_2_BYTES);
  53         udelay(10 * 1000);
  54         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  55         tegra_i2c_ll_write_data(0x0004, I2C_SEND_2_BYTES);
  56         udelay(10 * 1000);
  57         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  58         tegra_i2c_ll_write_data(0x001b, I2C_SEND_2_BYTES);
  59         udelay(10 * 1000);
  60         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  61         tegra_i2c_ll_write_data(0x0014, I2C_SEND_2_BYTES);
  62         udelay(10 * 1000);
  63         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  64         tegra_i2c_ll_write_data(0x001a, I2C_SEND_2_BYTES);
  65         udelay(10 * 1000);
  66         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  67         tegra_i2c_ll_write_data(0x0019, I2C_SEND_2_BYTES);
  68         udelay(10 * 1000);
  69
  70         debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
  71         /*
  72          * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
  73          * First set VDD to 1.0V, then enable the VDD regulator.
  74          */
  75         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  76         tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
  77         /*
  78          * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
  79          * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
  80          */
  81         udelay(10 * 1000);
  82
  83         debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);
  84         /*
  85          * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
  86          * First set VDD to 1.0V, then enable the VDD regulator.
  87          */
  88         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  89         tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
  90         /*
  91          * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
  92          * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
  93          */
  94         udelay(10 * 1000);
  95
  96         debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);
  97         /*
  98          * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
  99          * First set VDD to 1.2V, then enable the VDD regulator.
 100          */
 101         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
 102         tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
 103         /*
 104          * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
 105          * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
 106          */
 107         udelay(10 * 1000);
 108
 109         debug("%s: Set VDD_SDMMC1 to 3.3V via AS3722 reg 0x11/4E\n", __func__);
 110         /*
 111          * Bring up VDD_SDMMC1 via the AS3722 PMIC on the PWR I2C bus.
 112          * First set it to value closest to 3.3V, then enable the regulator
 113          *
 114          * NOTE: We do this early because doing it later seems to hose the CPU
 115          * power rail/partition startup. Need to debug.
 116          */
 117         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
 118         tegra_i2c_ll_write_data(AS3722_LDO1VOLTAGE_DATA, I2C_SEND_2_BYTES);
 119         /*
 120          * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
 121          * tegra_i2c_ll_write_data(AS3722_LDO1CONTROL_DATA, I2C_SEND_2_BYTES);
 122          */
 123         udelay(10 * 1000);
 124
 125         debug("%s: Set VDD_SDMMC3 to 3.3V via AS3722 reg 0x16/4E\n", __func__);
 126         /*
 127          * Bring up VDD_SDMMC3 via the AS3722 PMIC on the PWR I2C bus.
 128          * First set it to bypass 3.3V straight thru, then enable the regulator
 129          *
 130          * NOTE: We do this early because doing it later seems to hose the CPU
 131          * power rail/partition startup. Need to debug.
 132          */
 133         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
 134         tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
 135         /*
 136          * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
 137          * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
 138          */
 139         udelay(10 * 1000);
 140 }