1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2016-2018 Toradex, Inc.
8 #include <asm/arch-tegra/ap.h>
11 #include <asm/arch/gpio.h>
12 #include <asm/arch/pinmux.h>
13 #include <pci_tegra.h>
14 #include <power/as3722.h>
15 #include <power/pmic.h>
17 #include "../common/tdx-common.h"
18 #include "pinmux-config-apalis-tk1.h"
20 #define LAN_DEV_OFF_N TEGRA_GPIO(O, 6)
21 #define LAN_RESET_N TEGRA_GPIO(S, 2)
22 #define FAN_EN TEGRA_GPIO(DD, 2)
23 #define LAN_WAKE_N TEGRA_GPIO(O, 5)
24 #ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
25 #define PEX_PERST_N TEGRA_GPIO(DD, 1) /* Apalis GPIO7 */
26 #define RESET_MOCI_CTRL TEGRA_GPIO(U, 4)
27 #endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
29 int arch_misc_init(void)
31 if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
33 printf("USB recovery mode\n");
40 puts("Model: Toradex Apalis TK1 2GB\n");
45 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
46 int ft_board_setup(void *blob, bd_t *bd)
48 return ft_common_board_setup(blob, bd);
53 * Routine: pinmux_init
54 * Description: Do individual peripheral pinmux configs
56 void pinmux_init(void)
58 pinmux_clear_tristate_input_clamping();
60 gpio_config_table(apalis_tk1_gpio_inits,
61 ARRAY_SIZE(apalis_tk1_gpio_inits));
63 pinmux_config_pingrp_table(apalis_tk1_pingrps,
64 ARRAY_SIZE(apalis_tk1_pingrps));
66 pinmux_config_drvgrp_table(apalis_tk1_drvgrps,
67 ARRAY_SIZE(apalis_tk1_drvgrps));
70 #ifdef CONFIG_PCI_TEGRA
71 /* TODO: Convert to driver model */
72 static int as3722_sd_enable(struct udevice *pmic, unsigned int sd)
79 err = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd);
81 pr_err("failed to update SD control register: %d", err);
88 /* TODO: Convert to driver model */
89 static int as3722_ldo_enable(struct udevice *pmic, unsigned int ldo)
92 u8 ctrl_reg = AS3722_LDO_CONTROL0;
98 ctrl_reg = AS3722_LDO_CONTROL1;
102 err = pmic_clrsetbits(pmic, ctrl_reg, 0, 1 << ldo);
104 pr_err("failed to update LDO control register: %d", err);
111 int tegra_pcie_board_init(void)
116 ret = uclass_get_device_by_driver(UCLASS_PMIC,
117 DM_GET_DRIVER(pmic_as3722), &dev);
119 pr_err("failed to find AS3722 PMIC: %d\n", ret);
123 ret = as3722_sd_enable(dev, 4);
125 pr_err("failed to enable SD4: %d\n", ret);
129 ret = as3722_sd_set_voltage(dev, 4, 0x24);
131 pr_err("failed to set SD4 voltage: %d\n", ret);
135 gpio_request(LAN_DEV_OFF_N, "LAN_DEV_OFF_N");
136 gpio_request(LAN_RESET_N, "LAN_RESET_N");
137 gpio_request(LAN_WAKE_N, "LAN_WAKE_N");
139 #ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
140 gpio_request(PEX_PERST_N, "PEX_PERST_N");
141 gpio_request(RESET_MOCI_CTRL, "RESET_MOCI_CTRL");
142 #endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
147 void tegra_pcie_board_port_reset(struct tegra_pcie_port *port)
149 int index = tegra_pcie_port_index_of_port(port);
151 if (index == 1) { /* I210 Gigabit Ethernet Controller (On-module) */
155 ret = uclass_get_device_by_driver(UCLASS_PMIC,
156 DM_GET_DRIVER(pmic_as3722),
159 debug("%s: Failed to find PMIC\n", __func__);
163 /* Reset I210 Gigabit Ethernet Controller */
164 gpio_direction_output(LAN_RESET_N, 0);
167 * Make sure we don't get any back feeding from DEV_OFF_N resp.
170 gpio_direction_output(LAN_DEV_OFF_N, 0);
171 gpio_direction_output(LAN_WAKE_N, 0);
173 /* Make sure LDO9 and LDO10 are initially enabled @ 0V */
174 ret = as3722_ldo_enable(dev, 9);
176 pr_err("failed to enable LDO9: %d\n", ret);
179 ret = as3722_ldo_enable(dev, 10);
181 pr_err("failed to enable LDO10: %d\n", ret);
184 ret = as3722_ldo_set_voltage(dev, 9, 0x80);
186 pr_err("failed to set LDO9 voltage: %d\n", ret);
189 ret = as3722_ldo_set_voltage(dev, 10, 0x80);
191 pr_err("failed to set LDO10 voltage: %d\n", ret);
195 /* Make sure controller gets enabled by disabling DEV_OFF_N */
196 gpio_set_value(LAN_DEV_OFF_N, 1);
199 * Enable LDO9 and LDO10 for +V3.3_ETH on patched prototype
200 * V1.0A and sample V1.0B and newer modules
202 ret = as3722_ldo_set_voltage(dev, 9, 0xff);
204 pr_err("failed to set LDO9 voltage: %d\n", ret);
207 ret = as3722_ldo_set_voltage(dev, 10, 0xff);
209 pr_err("failed to set LDO10 voltage: %d\n", ret);
214 * Must be asserted for 100 ms after power and clocks are stable
218 gpio_set_value(LAN_RESET_N, 1);
219 } else if (index == 0) { /* Apalis PCIe */
220 #ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
222 * Reset PLX PEX 8605 PCIe Switch plus PCIe devices on Apalis
225 gpio_direction_output(PEX_PERST_N, 0);
226 gpio_direction_output(RESET_MOCI_CTRL, 0);
229 * Must be asserted for 100 ms after power and clocks are stable
233 gpio_set_value(PEX_PERST_N, 1);
235 * Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not Guaranteed
236 * Until 900 us After PEX_PERST# De-assertion
239 gpio_set_value(RESET_MOCI_CTRL, 1);
240 #endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
243 #endif /* CONFIG_PCI_TEGRA */
246 * Enable/start PWM CPU fan
248 void start_cpu_fan(void)
250 gpio_request(FAN_EN, "FAN_EN");
251 gpio_direction_output(FAN_EN, 1);
255 * Backlight off before OS handover
257 void board_preboot_os(void)
259 gpio_request(TEGRA_GPIO(BB, 5), "BL_ON");
260 gpio_direction_output(TEGRA_GPIO(BB, 5), 0);