board/ti/ks2_evm/board_k2g.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * K2G EVM : Board initialization
   4  *
   5  * (C) Copyright 2015
   6  *     Texas Instruments Incorporated, <www.ti.com>
   7  */
   8 #include <common.h>
   9 #include <eeprom.h>
  10 #include <env.h>
  11 #include <hang.h>
  12 #include <image.h>
  13 #include <init.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/ti-common/keystone_net.h>
  16 #include <asm/arch/psc_defs.h>
  17 #include <asm/arch/mmc_host_def.h>
  18 #include <fdtdec.h>
  19 #include <i2c.h>
  20 #include <remoteproc.h>
  21 #include <linux/delay.h>
  22 #include "mux-k2g.h"
  23 #include "../common/board_detect.h"
  24
  25 #define K2G_GP_AUDIO_CODEC_ADDRESS      0x1B
  26
  27 const unsigned int sysclk_array[MAX_SYSCLK] = {
  28         19200000,
  29         24000000,
  30         25000000,
  31         26000000,
  32 };
  33
  34 unsigned int get_external_clk(u32 clk)
  35 {
  36         unsigned int clk_freq;
  37         u8 sysclk_index = get_sysclk_index();
  38
  39         switch (clk) {
  40         case sys_clk:
  41                 clk_freq = sysclk_array[sysclk_index];
  42                 break;
  43         case pa_clk:
  44                 clk_freq = sysclk_array[sysclk_index];
  45                 break;
  46         case tetris_clk:
  47                 clk_freq = sysclk_array[sysclk_index];
  48                 break;
  49         case ddr3a_clk:
  50                 clk_freq = sysclk_array[sysclk_index];
  51                 break;
  52         case uart_clk:
  53                 clk_freq = sysclk_array[sysclk_index];
  54                 break;
  55         default:
  56                 clk_freq = 0;
  57                 break;
  58         }
  59
  60         return clk_freq;
  61 }
  62
  63 int speeds[DEVSPEED_NUMSPDS] = {
  64         SPD400,
  65         SPD600,
  66         SPD800,
  67         SPD900,
  68         SPD1000,
  69         SPD900,
  70         SPD800,
  71         SPD600,
  72         SPD400,
  73         SPD200,
  74 };
  75
  76 static int dev_speeds[DEVSPEED_NUMSPDS] = {
  77         SPD600,
  78         SPD800,
  79         SPD900,
  80         SPD1000,
  81         SPD900,
  82         SPD800,
  83         SPD600,
  84         SPD400,
  85 };
  86
  87 static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = {
  88         [SYSCLK_19MHz] = {
  89                 [SPD400]        = {MAIN_PLL, 125, 3, 2},
  90                 [SPD600]        = {MAIN_PLL, 125, 2, 2},
  91                 [SPD800]        = {MAIN_PLL, 250, 3, 2},
  92                 [SPD900]        = {MAIN_PLL, 187, 2, 2},
  93                 [SPD1000]       = {MAIN_PLL, 104, 1, 2},
  94         },
  95         [SYSCLK_24MHz] = {
  96                 [SPD400]        = {MAIN_PLL, 100, 3, 2},
  97                 [SPD600]        = {MAIN_PLL, 300, 6, 2},
  98                 [SPD800]        = {MAIN_PLL, 200, 3, 2},
  99                 [SPD900]        = {MAIN_PLL, 75, 1, 2},
 100                 [SPD1000]       = {MAIN_PLL, 250, 3, 2},
 101         },
 102         [SYSCLK_25MHz] = {
 103                 [SPD400]        = {MAIN_PLL, 32, 1, 2},
 104                 [SPD600]        = {MAIN_PLL, 48, 1, 2},
 105                 [SPD800]        = {MAIN_PLL, 64, 1, 2},
 106                 [SPD900]        = {MAIN_PLL, 72, 1, 2},
 107                 [SPD1000]       = {MAIN_PLL, 80, 1, 2},
 108         },
 109         [SYSCLK_26MHz] = {
 110                 [SPD400]        = {MAIN_PLL, 400, 13, 2},
 111                 [SPD600]        = {MAIN_PLL, 230, 5, 2},
 112                 [SPD800]        = {MAIN_PLL, 123, 2, 2},
 113                 [SPD900]        = {MAIN_PLL, 69, 1, 2},
 114                 [SPD1000]       = {MAIN_PLL, 384, 5, 2},
 115         },
 116 };
 117
 118 static struct pll_init_data tetris_pll_config[MAX_SYSCLK][NUM_SPDS] = {
 119         [SYSCLK_19MHz] = {
 120                 [SPD200]        = {TETRIS_PLL, 625, 6, 10},
 121                 [SPD400]        = {TETRIS_PLL, 125, 1, 6},
 122                 [SPD600]        = {TETRIS_PLL, 125, 1, 4},
 123                 [SPD800]        = {TETRIS_PLL, 333, 2, 4},
 124                 [SPD900]        = {TETRIS_PLL, 187, 2, 2},
 125                 [SPD1000]       = {TETRIS_PLL, 104, 1, 2},
 126         },
 127         [SYSCLK_24MHz] = {
 128                 [SPD200]        = {TETRIS_PLL, 250, 3, 10},
 129                 [SPD400]        = {TETRIS_PLL, 100, 1, 6},
 130                 [SPD600]        = {TETRIS_PLL, 100, 1, 4},
 131                 [SPD800]        = {TETRIS_PLL, 400, 3, 4},
 132                 [SPD900]        = {TETRIS_PLL, 75, 1, 2},
 133                 [SPD1000]       = {TETRIS_PLL, 250, 3, 2},
 134         },
 135         [SYSCLK_25MHz] = {
 136                 [SPD200]        = {TETRIS_PLL, 80, 1, 10},
 137                 [SPD400]        = {TETRIS_PLL, 96, 1, 6},
 138                 [SPD600]        = {TETRIS_PLL, 96, 1, 4},
 139                 [SPD800]        = {TETRIS_PLL, 128, 1, 4},
 140                 [SPD900]        = {TETRIS_PLL, 72, 1, 2},
 141                 [SPD1000]       = {TETRIS_PLL, 80, 1, 2},
 142         },
 143         [SYSCLK_26MHz] = {
 144                 [SPD200]        = {TETRIS_PLL, 307, 4, 10},
 145                 [SPD400]        = {TETRIS_PLL, 369, 4, 6},
 146                 [SPD600]        = {TETRIS_PLL, 369, 4, 4},
 147                 [SPD800]        = {TETRIS_PLL, 123, 1, 4},
 148                 [SPD900]        = {TETRIS_PLL, 69, 1, 2},
 149                 [SPD1000]       = {TETRIS_PLL, 384, 5, 2},
 150         },
 151 };
 152
 153 static struct pll_init_data uart_pll_config[MAX_SYSCLK] = {
 154         [SYSCLK_19MHz] = {UART_PLL, 160, 1, 8},
 155         [SYSCLK_24MHz] = {UART_PLL, 128, 1, 8},
 156         [SYSCLK_25MHz] = {UART_PLL, 768, 5, 10},
 157         [SYSCLK_26MHz] = {UART_PLL, 384, 13, 2},
 158 };
 159
 160 static struct pll_init_data nss_pll_config[MAX_SYSCLK] = {
 161         [SYSCLK_19MHz] = {NSS_PLL, 625, 6, 2},
 162         [SYSCLK_24MHz] = {NSS_PLL, 250, 3, 2},
 163         [SYSCLK_25MHz] = {NSS_PLL, 80, 1, 2},
 164         [SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2},
 165 };
 166
 167 static struct pll_init_data ddr3_pll_config_800[MAX_SYSCLK] = {
 168         [SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16},
 169         [SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16},
 170         [SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16},
 171         [SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16},
 172 };
 173
 174 static struct pll_init_data ddr3_pll_config_1066[MAX_SYSCLK] = {
 175         [SYSCLK_19MHz] = {DDR3A_PLL, 194, 1, 14},
 176         [SYSCLK_24MHz] = {DDR3A_PLL, 156, 1, 14},
 177         [SYSCLK_25MHz] = {DDR3A_PLL, 149, 1, 14},
 178         [SYSCLK_26MHz] = {DDR3A_PLL, 144, 1, 14},
 179 };
 180
 181 struct pll_init_data *get_pll_init_data(int pll)
 182 {
 183         int speed;
 184         struct pll_init_data *data = NULL;
 185         u8 sysclk_index = get_sysclk_index();
 186
 187         switch (pll) {
 188         case MAIN_PLL:
 189                 speed = get_max_dev_speed(dev_speeds);
 190                 data = &main_pll_config[sysclk_index][speed];
 191                 break;
 192         case TETRIS_PLL:
 193                 speed = get_max_arm_speed(speeds);
 194                 data = &tetris_pll_config[sysclk_index][speed];
 195                 break;
 196         case NSS_PLL:
 197                 data = &nss_pll_config[sysclk_index];
 198                 break;
 199         case UART_PLL:
 200                 data = &uart_pll_config[sysclk_index];
 201                 break;
 202         case DDR3_PLL:
 203                 if (cpu_revision() & CPU_66AK2G1x) {
 204                         speed = get_max_arm_speed(speeds);
 205                         if (speed == SPD1000)
 206                                 data = &ddr3_pll_config_1066[sysclk_index];
 207                         else
 208                                 data = &ddr3_pll_config_800[sysclk_index];
 209                 } else {
 210                         data = &ddr3_pll_config_800[sysclk_index];
 211                 }
 212                 break;
 213         default:
 214                 data = NULL;
 215         }
 216
 217         return data;
 218 }
 219
 220 s16 divn_val[16] = {
 221         -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
 222 };
 223
 224 #if defined(CONFIG_MMC)
 225 int board_mmc_init(bd_t *bis)
 226 {
 227         if (psc_enable_module(KS2_LPSC_MMC)) {
 228                 printf("%s module enabled failed\n", __func__);
 229                 return -1;
 230         }
 231
 232         if (board_is_k2g_gp() || board_is_k2g_g1())
 233                 omap_mmc_init(0, 0, 0, -1, -1);
 234
 235         omap_mmc_init(1, 0, 0, -1, -1);
 236         return 0;
 237 }
 238 #endif
 239
 240 #if defined(CONFIG_MULTI_DTB_FIT)
 241 int board_fit_config_name_match(const char *name)
 242 {
 243         bool eeprom_read = board_ti_was_eeprom_read();
 244
 245         if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read)
 246                 return 0;
 247         else if (!strcmp(name, "keystone-k2g-evm") &&
 248                 (board_ti_is("66AK2GGP") || board_ti_is("66AK2GG1")))
 249                 return 0;
 250         else if (!strcmp(name, "keystone-k2g-ice") && board_ti_is("66AK2GIC"))
 251                 return 0;
 252         else
 253                 return -1;
 254 }
 255 #endif
 256
 257 #if defined(CONFIG_DTB_RESELECT)
 258 static int k2g_alt_board_detect(void)
 259 {
 260 #ifndef CONFIG_DM_I2C
 261         int rc;
 262
 263         rc = i2c_set_bus_num(1);
 264         if (rc)
 265                 return rc;
 266
 267         rc = i2c_probe(K2G_GP_AUDIO_CODEC_ADDRESS);
 268         if (rc)
 269                 return rc;
 270 #else
 271         struct udevice *bus, *dev;
 272         int rc;
 273
 274         rc = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus);
 275         if (rc)
 276                 return rc;
 277         rc = dm_i2c_probe(bus, K2G_GP_AUDIO_CODEC_ADDRESS, 0, &dev);
 278         if (rc)
 279                 return rc;
 280 #endif
 281         ti_i2c_eeprom_am_set("66AK2GGP", "1.0X");
 282
 283         return 0;
 284 }
 285
 286 static void k2g_reset_mux_config(void)
 287 {
 288         /* Unlock the reset mux register */
 289         clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
 290
 291         /* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
 292         clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
 293                         RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
 294
 295         /* lock the reset mux register to prevent any spurious writes. */
 296         setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
 297 }
 298
 299 int embedded_dtb_select(void)
 300 {
 301         int rc;
 302         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 303                         CONFIG_EEPROM_CHIP_ADDRESS);
 304         if (rc) {
 305                 rc = k2g_alt_board_detect();
 306                 if (rc) {
 307                         printf("Unable to do board detection\n");
 308                         return -1;
 309                 }
 310         }
 311
 312         fdtdec_setup();
 313
 314         k2g_mux_config();
 315
 316         k2g_reset_mux_config();
 317
 318         if (board_is_k2g_gp() || board_is_k2g_g1()) {
 319                 /* deassert FLASH_HOLD */
 320                 clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
 321                              BIT(9));
 322                 setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
 323                              BIT(9));
 324         } else if (board_is_k2g_ice()) {
 325                 /* GBE Phy workaround. For Phy to latch the input
 326                  * configuration, a GPIO reset is asserted at the
 327                  * Phy reset pin to latch configuration correctly after SoC
 328                  * reset. GPIO0 Pin 10 (Ball AA20) is used for this on ICE
 329                  * board. Just do a low to high transition.
 330                  */
 331                 clrbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_DIR_OFFSET,
 332                              BIT(10));
 333                 setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_CLRDATA_OFFSET,
 334                              BIT(10));
 335                 /* Delay just to get a transition to high */
 336                 udelay(100);
 337                 setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_SETDATA_OFFSET,
 338                              BIT(10));
 339         }
 340
 341         return 0;
 342 }
 343 #endif
 344
 345 #ifdef CONFIG_BOARD_LATE_INIT
 346 int board_late_init(void)
 347 {
 348 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
 349         int rc;
 350
 351         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 352                         CONFIG_EEPROM_CHIP_ADDRESS);
 353         if (rc)
 354                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 355
 356         board_ti_set_ethaddr(1);
 357 #endif
 358
 359 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 360         if (board_is_k2g_gp())
 361                 env_set("board_name", "66AK2GGP\0");
 362         else if (board_is_k2g_g1())
 363                 env_set("board_name", "66AK2GG1\0");
 364         else if (board_is_k2g_ice())
 365                 env_set("board_name", "66AK2GIC\0");
 366 #endif
 367         return 0;
 368 }
 369 #endif
 370
 371 #ifdef CONFIG_BOARD_EARLY_INIT_F
 372 int board_early_init_f(void)
 373 {
 374         init_plls();
 375
 376         k2g_mux_config();
 377
 378         return 0;
 379 }
 380 #endif
 381
 382 #ifdef CONFIG_SPL_BUILD
 383 void spl_init_keystone_plls(void)
 384 {
 385         init_plls();
 386 }
 387 #endif
 388
 389 #ifdef CONFIG_TI_SECURE_DEVICE
 390 void board_pmmc_image_process(ulong pmmc_image, size_t pmmc_size)
 391 {
 392         int id = env_get_ulong("dev_pmmc", 10, 0);
 393         int ret;
 394
 395         if (!rproc_is_initialized())
 396                 rproc_init();
 397
 398         ret = rproc_load(id, pmmc_image, pmmc_size);
 399         printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
 400                id, pmmc_image, pmmc_size, ret ? " Failed!" : " Success!");
 401
 402         if (!ret)
 403                 rproc_start(id);
 404 }
 405
 406 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_PMMC, board_pmmc_image_process);
 407 #endif