board/ti/ks2_evm/board_k2g.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * K2G EVM : Board initialization
   4  *
   5  * (C) Copyright 2015
   6  *     Texas Instruments Incorporated, <www.ti.com>
   7  */
   8 #include <common.h>
   9 #include <eeprom.h>
  10 #include <env.h>
  11 #include <hang.h>
  12 #include <image.h>
  13 #include <init.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/ti-common/keystone_net.h>
  16 #include <asm/arch/psc_defs.h>
  17 #include <asm/arch/mmc_host_def.h>
  18 #include <fdtdec.h>
  19 #include <i2c.h>
  20 #include <remoteproc.h>
  21 #include "mux-k2g.h"
  22 #include "../common/board_detect.h"
  23
  24 #define K2G_GP_AUDIO_CODEC_ADDRESS      0x1B
  25
  26 const unsigned int sysclk_array[MAX_SYSCLK] = {
  27         19200000,
  28         24000000,
  29         25000000,
  30         26000000,
  31 };
  32
  33 unsigned int get_external_clk(u32 clk)
  34 {
  35         unsigned int clk_freq;
  36         u8 sysclk_index = get_sysclk_index();
  37
  38         switch (clk) {
  39         case sys_clk:
  40                 clk_freq = sysclk_array[sysclk_index];
  41                 break;
  42         case pa_clk:
  43                 clk_freq = sysclk_array[sysclk_index];
  44                 break;
  45         case tetris_clk:
  46                 clk_freq = sysclk_array[sysclk_index];
  47                 break;
  48         case ddr3a_clk:
  49                 clk_freq = sysclk_array[sysclk_index];
  50                 break;
  51         case uart_clk:
  52                 clk_freq = sysclk_array[sysclk_index];
  53                 break;
  54         default:
  55                 clk_freq = 0;
  56                 break;
  57         }
  58
  59         return clk_freq;
  60 }
  61
  62 int speeds[DEVSPEED_NUMSPDS] = {
  63         SPD400,
  64         SPD600,
  65         SPD800,
  66         SPD900,
  67         SPD1000,
  68         SPD900,
  69         SPD800,
  70         SPD600,
  71         SPD400,
  72         SPD200,
  73 };
  74
  75 static int dev_speeds[DEVSPEED_NUMSPDS] = {
  76         SPD600,
  77         SPD800,
  78         SPD900,
  79         SPD1000,
  80         SPD900,
  81         SPD800,
  82         SPD600,
  83         SPD400,
  84 };
  85
  86 static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = {
  87         [SYSCLK_19MHz] = {
  88                 [SPD400]        = {MAIN_PLL, 125, 3, 2},
  89                 [SPD600]        = {MAIN_PLL, 125, 2, 2},
  90                 [SPD800]        = {MAIN_PLL, 250, 3, 2},
  91                 [SPD900]        = {MAIN_PLL, 187, 2, 2},
  92                 [SPD1000]       = {MAIN_PLL, 104, 1, 2},
  93         },
  94         [SYSCLK_24MHz] = {
  95                 [SPD400]        = {MAIN_PLL, 100, 3, 2},
  96                 [SPD600]        = {MAIN_PLL, 300, 6, 2},
  97                 [SPD800]        = {MAIN_PLL, 200, 3, 2},
  98                 [SPD900]        = {MAIN_PLL, 75, 1, 2},
  99                 [SPD1000]       = {MAIN_PLL, 250, 3, 2},
 100         },
 101         [SYSCLK_25MHz] = {
 102                 [SPD400]        = {MAIN_PLL, 32, 1, 2},
 103                 [SPD600]        = {MAIN_PLL, 48, 1, 2},
 104                 [SPD800]        = {MAIN_PLL, 64, 1, 2},
 105                 [SPD900]        = {MAIN_PLL, 72, 1, 2},
 106                 [SPD1000]       = {MAIN_PLL, 80, 1, 2},
 107         },
 108         [SYSCLK_26MHz] = {
 109                 [SPD400]        = {MAIN_PLL, 400, 13, 2},
 110                 [SPD600]        = {MAIN_PLL, 230, 5, 2},
 111                 [SPD800]        = {MAIN_PLL, 123, 2, 2},
 112                 [SPD900]        = {MAIN_PLL, 69, 1, 2},
 113                 [SPD1000]       = {MAIN_PLL, 384, 5, 2},
 114         },
 115 };
 116
 117 static struct pll_init_data tetris_pll_config[MAX_SYSCLK][NUM_SPDS] = {
 118         [SYSCLK_19MHz] = {
 119                 [SPD200]        = {TETRIS_PLL, 625, 6, 10},
 120                 [SPD400]        = {TETRIS_PLL, 125, 1, 6},
 121                 [SPD600]        = {TETRIS_PLL, 125, 1, 4},
 122                 [SPD800]        = {TETRIS_PLL, 333, 2, 4},
 123                 [SPD900]        = {TETRIS_PLL, 187, 2, 2},
 124                 [SPD1000]       = {TETRIS_PLL, 104, 1, 2},
 125         },
 126         [SYSCLK_24MHz] = {
 127                 [SPD200]        = {TETRIS_PLL, 250, 3, 10},
 128                 [SPD400]        = {TETRIS_PLL, 100, 1, 6},
 129                 [SPD600]        = {TETRIS_PLL, 100, 1, 4},
 130                 [SPD800]        = {TETRIS_PLL, 400, 3, 4},
 131                 [SPD900]        = {TETRIS_PLL, 75, 1, 2},
 132                 [SPD1000]       = {TETRIS_PLL, 250, 3, 2},
 133         },
 134         [SYSCLK_25MHz] = {
 135                 [SPD200]        = {TETRIS_PLL, 80, 1, 10},
 136                 [SPD400]        = {TETRIS_PLL, 96, 1, 6},
 137                 [SPD600]        = {TETRIS_PLL, 96, 1, 4},
 138                 [SPD800]        = {TETRIS_PLL, 128, 1, 4},
 139                 [SPD900]        = {TETRIS_PLL, 72, 1, 2},
 140                 [SPD1000]       = {TETRIS_PLL, 80, 1, 2},
 141         },
 142         [SYSCLK_26MHz] = {
 143                 [SPD200]        = {TETRIS_PLL, 307, 4, 10},
 144                 [SPD400]        = {TETRIS_PLL, 369, 4, 6},
 145                 [SPD600]        = {TETRIS_PLL, 369, 4, 4},
 146                 [SPD800]        = {TETRIS_PLL, 123, 1, 4},
 147                 [SPD900]        = {TETRIS_PLL, 69, 1, 2},
 148                 [SPD1000]       = {TETRIS_PLL, 384, 5, 2},
 149         },
 150 };
 151
 152 static struct pll_init_data uart_pll_config[MAX_SYSCLK] = {
 153         [SYSCLK_19MHz] = {UART_PLL, 160, 1, 8},
 154         [SYSCLK_24MHz] = {UART_PLL, 128, 1, 8},
 155         [SYSCLK_25MHz] = {UART_PLL, 768, 5, 10},
 156         [SYSCLK_26MHz] = {UART_PLL, 384, 13, 2},
 157 };
 158
 159 static struct pll_init_data nss_pll_config[MAX_SYSCLK] = {
 160         [SYSCLK_19MHz] = {NSS_PLL, 625, 6, 2},
 161         [SYSCLK_24MHz] = {NSS_PLL, 250, 3, 2},
 162         [SYSCLK_25MHz] = {NSS_PLL, 80, 1, 2},
 163         [SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2},
 164 };
 165
 166 static struct pll_init_data ddr3_pll_config_800[MAX_SYSCLK] = {
 167         [SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16},
 168         [SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16},
 169         [SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16},
 170         [SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16},
 171 };
 172
 173 static struct pll_init_data ddr3_pll_config_1066[MAX_SYSCLK] = {
 174         [SYSCLK_19MHz] = {DDR3A_PLL, 194, 1, 14},
 175         [SYSCLK_24MHz] = {DDR3A_PLL, 156, 1, 14},
 176         [SYSCLK_25MHz] = {DDR3A_PLL, 149, 1, 14},
 177         [SYSCLK_26MHz] = {DDR3A_PLL, 144, 1, 14},
 178 };
 179
 180 struct pll_init_data *get_pll_init_data(int pll)
 181 {
 182         int speed;
 183         struct pll_init_data *data = NULL;
 184         u8 sysclk_index = get_sysclk_index();
 185
 186         switch (pll) {
 187         case MAIN_PLL:
 188                 speed = get_max_dev_speed(dev_speeds);
 189                 data = &main_pll_config[sysclk_index][speed];
 190                 break;
 191         case TETRIS_PLL:
 192                 speed = get_max_arm_speed(speeds);
 193                 data = &tetris_pll_config[sysclk_index][speed];
 194                 break;
 195         case NSS_PLL:
 196                 data = &nss_pll_config[sysclk_index];
 197                 break;
 198         case UART_PLL:
 199                 data = &uart_pll_config[sysclk_index];
 200                 break;
 201         case DDR3_PLL:
 202                 if (cpu_revision() & CPU_66AK2G1x) {
 203                         speed = get_max_arm_speed(speeds);
 204                         if (speed == SPD1000)
 205                                 data = &ddr3_pll_config_1066[sysclk_index];
 206                         else
 207                                 data = &ddr3_pll_config_800[sysclk_index];
 208                 } else {
 209                         data = &ddr3_pll_config_800[sysclk_index];
 210                 }
 211                 break;
 212         default:
 213                 data = NULL;
 214         }
 215
 216         return data;
 217 }
 218
 219 s16 divn_val[16] = {
 220         -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
 221 };
 222
 223 #if defined(CONFIG_MMC)
 224 int board_mmc_init(bd_t *bis)
 225 {
 226         if (psc_enable_module(KS2_LPSC_MMC)) {
 227                 printf("%s module enabled failed\n", __func__);
 228                 return -1;
 229         }
 230
 231         if (board_is_k2g_gp() || board_is_k2g_g1())
 232                 omap_mmc_init(0, 0, 0, -1, -1);
 233
 234         omap_mmc_init(1, 0, 0, -1, -1);
 235         return 0;
 236 }
 237 #endif
 238
 239 #if defined(CONFIG_MULTI_DTB_FIT)
 240 int board_fit_config_name_match(const char *name)
 241 {
 242         bool eeprom_read = board_ti_was_eeprom_read();
 243
 244         if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read)
 245                 return 0;
 246         else if (!strcmp(name, "keystone-k2g-evm") &&
 247                 (board_ti_is("66AK2GGP") || board_ti_is("66AK2GG1")))
 248                 return 0;
 249         else if (!strcmp(name, "keystone-k2g-ice") && board_ti_is("66AK2GIC"))
 250                 return 0;
 251         else
 252                 return -1;
 253 }
 254 #endif
 255
 256 #if defined(CONFIG_DTB_RESELECT)
 257 static int k2g_alt_board_detect(void)
 258 {
 259 #ifndef CONFIG_DM_I2C
 260         int rc;
 261
 262         rc = i2c_set_bus_num(1);
 263         if (rc)
 264                 return rc;
 265
 266         rc = i2c_probe(K2G_GP_AUDIO_CODEC_ADDRESS);
 267         if (rc)
 268                 return rc;
 269 #else
 270         struct udevice *bus, *dev;
 271         int rc;
 272
 273         rc = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus);
 274         if (rc)
 275                 return rc;
 276         rc = dm_i2c_probe(bus, K2G_GP_AUDIO_CODEC_ADDRESS, 0, &dev);
 277         if (rc)
 278                 return rc;
 279 #endif
 280         ti_i2c_eeprom_am_set("66AK2GGP", "1.0X");
 281
 282         return 0;
 283 }
 284
 285 static void k2g_reset_mux_config(void)
 286 {
 287         /* Unlock the reset mux register */
 288         clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
 289
 290         /* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
 291         clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
 292                         RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
 293
 294         /* lock the reset mux register to prevent any spurious writes. */
 295         setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
 296 }
 297
 298 int embedded_dtb_select(void)
 299 {
 300         int rc;
 301         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 302                         CONFIG_EEPROM_CHIP_ADDRESS);
 303         if (rc) {
 304                 rc = k2g_alt_board_detect();
 305                 if (rc) {
 306                         printf("Unable to do board detection\n");
 307                         return -1;
 308                 }
 309         }
 310
 311         fdtdec_setup();
 312
 313         k2g_mux_config();
 314
 315         k2g_reset_mux_config();
 316
 317         if (board_is_k2g_gp() || board_is_k2g_g1()) {
 318                 /* deassert FLASH_HOLD */
 319                 clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
 320                              BIT(9));
 321                 setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
 322                              BIT(9));
 323         } else if (board_is_k2g_ice()) {
 324                 /* GBE Phy workaround. For Phy to latch the input
 325                  * configuration, a GPIO reset is asserted at the
 326                  * Phy reset pin to latch configuration correctly after SoC
 327                  * reset. GPIO0 Pin 10 (Ball AA20) is used for this on ICE
 328                  * board. Just do a low to high transition.
 329                  */
 330                 clrbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_DIR_OFFSET,
 331                              BIT(10));
 332                 setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_CLRDATA_OFFSET,
 333                              BIT(10));
 334                 /* Delay just to get a transition to high */
 335                 udelay(100);
 336                 setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_SETDATA_OFFSET,
 337                              BIT(10));
 338         }
 339
 340         return 0;
 341 }
 342 #endif
 343
 344 #ifdef CONFIG_BOARD_LATE_INIT
 345 int board_late_init(void)
 346 {
 347 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
 348         int rc;
 349
 350         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 351                         CONFIG_EEPROM_CHIP_ADDRESS);
 352         if (rc)
 353                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 354
 355         board_ti_set_ethaddr(1);
 356 #endif
 357
 358 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 359         if (board_is_k2g_gp())
 360                 env_set("board_name", "66AK2GGP\0");
 361         else if (board_is_k2g_g1())
 362                 env_set("board_name", "66AK2GG1\0");
 363         else if (board_is_k2g_ice())
 364                 env_set("board_name", "66AK2GIC\0");
 365 #endif
 366         return 0;
 367 }
 368 #endif
 369
 370 #ifdef CONFIG_BOARD_EARLY_INIT_F
 371 int board_early_init_f(void)
 372 {
 373         init_plls();
 374
 375         k2g_mux_config();
 376
 377         return 0;
 378 }
 379 #endif
 380
 381 #ifdef CONFIG_SPL_BUILD
 382 void spl_init_keystone_plls(void)
 383 {
 384         init_plls();
 385 }
 386 #endif
 387
 388 #ifdef CONFIG_TI_SECURE_DEVICE
 389 void board_pmmc_image_process(ulong pmmc_image, size_t pmmc_size)
 390 {
 391         int id = env_get_ulong("dev_pmmc", 10, 0);
 392         int ret;
 393
 394         if (!rproc_is_initialized())
 395                 rproc_init();
 396
 397         ret = rproc_load(id, pmmc_image, pmmc_size);
 398         printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
 399                id, pmmc_image, pmmc_size, ret ? " Failed!" : " Success!");
 400
 401         if (!ret)
 402                 rproc_start(id);
 403 }
 404
 405 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_PMMC, board_pmmc_image_process);
 406 #endif