board/ti/ks2_evm/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Keystone : Board initialization
   4  *
   5  * (C) Copyright 2014
   6  *     Texas Instruments Incorporated, <www.ti.com>
   7  */
   8
   9 #include <common.h>
  10 #include "board.h"
  11 #include <env.h>
  12 #include <init.h>
  13 #include <spl.h>
  14 #include <exports.h>
  15 #include <fdt_support.h>
  16 #include <asm/arch/ddr3.h>
  17 #include <asm/arch/psc_defs.h>
  18 #include <asm/arch/clock.h>
  19 #include <asm/ti-common/ti-aemif.h>
  20 #include <asm/ti-common/keystone_net.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #if defined(CONFIG_TI_AEMIF)
  25 static struct aemif_config aemif_configs[] = {
  26         {                       /* CS0 */
  27                 .mode           = AEMIF_MODE_NAND,
  28                 .wr_setup       = 0xf,
  29                 .wr_strobe      = 0x3f,
  30                 .wr_hold        = 7,
  31                 .rd_setup       = 0xf,
  32                 .rd_strobe      = 0x3f,
  33                 .rd_hold        = 7,
  34                 .turn_around    = 3,
  35                 .width          = AEMIF_WIDTH_8,
  36         },
  37 };
  38 #endif
  39
  40 int dram_init(void)
  41 {
  42         u32 ddr3_size;
  43
  44         ddr3_size = ddr3_init();
  45
  46         gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
  47                                     CONFIG_MAX_RAM_BANK_SIZE);
  48 #if defined(CONFIG_TI_AEMIF)
  49         if (!board_is_k2g_ice())
  50                 aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
  51 #endif
  52
  53         if (!board_is_k2g_ice()) {
  54                 if (ddr3_size)
  55                         ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
  56                 else
  57                         ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE,
  58                                       gd->ram_size >> 30);
  59         }
  60
  61         return 0;
  62 }
  63
  64 struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
  65 {
  66         return (struct image_header *)(CONFIG_SYS_TEXT_BASE);
  67 }
  68
  69 int board_init(void)
  70 {
  71         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  72         return 0;
  73 }
  74
  75 #ifdef CONFIG_SPL_BUILD
  76 void spl_board_init(void)
  77 {
  78         spl_init_keystone_plls();
  79         preloader_console_init();
  80 }
  81
  82 u32 spl_boot_device(void)
  83 {
  84 #if defined(CONFIG_SPL_SPI_LOAD)
  85         return BOOT_DEVICE_SPI;
  86 #else
  87         puts("Unknown boot device\n");
  88         hang();
  89 #endif
  90 }
  91 #endif
  92
  93 #ifdef CONFIG_OF_BOARD_SETUP
  94 int ft_board_setup(void *blob, bd_t *bd)
  95 {
  96         int lpae;
  97         char *env;
  98         char *endp;
  99         int nbanks;
 100         u64 size[2];
 101         u64 start[2];
 102         u32 ddr3a_size;
 103
 104         env = env_get("mem_lpae");
 105         lpae = env && simple_strtol(env, NULL, 0);
 106
 107         ddr3a_size = 0;
 108         if (lpae) {
 109                 ddr3a_size = ddr3_get_size();
 110                 if ((ddr3a_size != 8) && (ddr3a_size != 4))
 111                         ddr3a_size = 0;
 112         }
 113
 114         nbanks = 1;
 115         start[0] = bd->bi_dram[0].start;
 116         size[0]  = bd->bi_dram[0].size;
 117
 118         /* adjust memory start address for LPAE */
 119         if (lpae) {
 120                 start[0] -= CONFIG_SYS_SDRAM_BASE;
 121                 start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
 122         }
 123
 124         if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
 125                 size[1] = ((u64)ddr3a_size - 2) << 30;
 126                 start[1] = 0x880000000;
 127                 nbanks++;
 128         }
 129
 130         /* reserve memory at start of bank */
 131         env = env_get("mem_reserve_head");
 132         if (env) {
 133                 start[0] += ustrtoul(env, &endp, 0);
 134                 size[0] -= ustrtoul(env, &endp, 0);
 135         }
 136
 137         env = env_get("mem_reserve");
 138         if (env)
 139                 size[0] -= ustrtoul(env, &endp, 0);
 140
 141         fdt_fixup_memory_banks(blob, start, size, nbanks);
 142
 143         return 0;
 144 }
 145
 146 void ft_board_setup_ex(void *blob, bd_t *bd)
 147 {
 148         int lpae;
 149         u64 size;
 150         char *env;
 151         u64 *reserve_start;
 152         int unitrd_fixup = 0;
 153
 154         env = env_get("mem_lpae");
 155         lpae = env && simple_strtol(env, NULL, 0);
 156         env = env_get("uinitrd_fixup");
 157         unitrd_fixup = env && simple_strtol(env, NULL, 0);
 158
 159         /* Fix up the initrd */
 160         if (lpae && unitrd_fixup) {
 161                 int nodeoffset;
 162                 int err;
 163                 u64 *prop1, *prop2;
 164                 u64 initrd_start, initrd_end;
 165
 166                 nodeoffset = fdt_path_offset(blob, "/chosen");
 167                 if (nodeoffset >= 0) {
 168                         prop1 = (u64 *)fdt_getprop(blob, nodeoffset,
 169                                             "linux,initrd-start", NULL);
 170                         prop2 = (u64 *)fdt_getprop(blob, nodeoffset,
 171                                             "linux,initrd-end", NULL);
 172                         if (prop1 && prop2) {
 173                                 initrd_start = __be64_to_cpu(*prop1);
 174                                 initrd_start -= CONFIG_SYS_SDRAM_BASE;
 175                                 initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
 176                                 initrd_start = __cpu_to_be64(initrd_start);
 177                                 initrd_end = __be64_to_cpu(*prop2);
 178                                 initrd_end -= CONFIG_SYS_SDRAM_BASE;
 179                                 initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
 180                                 initrd_end = __cpu_to_be64(initrd_end);
 181
 182                                 err = fdt_delprop(blob, nodeoffset,
 183                                                   "linux,initrd-start");
 184                                 if (err < 0)
 185                                         puts("error deleting initrd-start\n");
 186
 187                                 err = fdt_delprop(blob, nodeoffset,
 188                                                   "linux,initrd-end");
 189                                 if (err < 0)
 190                                         puts("error deleting initrd-end\n");
 191
 192                                 err = fdt_setprop(blob, nodeoffset,
 193                                                   "linux,initrd-start",
 194                                                   &initrd_start,
 195                                                   sizeof(initrd_start));
 196                                 if (err < 0)
 197                                         puts("error adding initrd-start\n");
 198
 199                                 err = fdt_setprop(blob, nodeoffset,
 200                                                   "linux,initrd-end",
 201                                                   &initrd_end,
 202                                                   sizeof(initrd_end));
 203                                 if (err < 0)
 204                                         puts("error adding linux,initrd-end\n");
 205                         }
 206                 }
 207         }
 208
 209         if (lpae) {
 210                 /*
 211                  * the initrd and other reserved memory areas are
 212                  * embedded in in the DTB itslef. fix up these addresses
 213                  * to 36 bit format
 214                  */
 215                 reserve_start = (u64 *)((char *)blob +
 216                                        fdt_off_mem_rsvmap(blob));
 217                 while (1) {
 218                         *reserve_start = __cpu_to_be64(*reserve_start);
 219                         size = __cpu_to_be64(*(reserve_start + 1));
 220                         if (size) {
 221                                 *reserve_start -= CONFIG_SYS_SDRAM_BASE;
 222                                 *reserve_start +=
 223                                         CONFIG_SYS_LPAE_SDRAM_BASE;
 224                                 *reserve_start =
 225                                         __cpu_to_be64(*reserve_start);
 226                         } else {
 227                                 break;
 228                         }
 229                         reserve_start += 2;
 230                 }
 231         }
 232
 233         ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
 234 }
 235 #endif /* CONFIG_OF_BOARD_SETUP */
 236
 237 #if defined(CONFIG_DTB_RESELECT)
 238 int __weak embedded_dtb_select(void)
 239 {
 240         return 0;
 241 }
 242 #endif