board/ti/am57xx/board.c

   1 /*
   2  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
   3  *
   4  * Author: Felipe Balbi <balbi@ti.com>
   5  *
   6  * Based on board/ti/dra7xx/evm.c
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <palmas.h>
  13 #include <sata.h>
  14 #include <usb.h>
  15 #include <asm/omap_common.h>
  16 #include <asm/omap_sec_common.h>
  17 #include <asm/emif.h>
  18 #include <asm/gpio.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/dra7xx_iodelay.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <asm/arch/mmc_host_def.h>
  24 #include <asm/arch/sata.h>
  25 #include <asm/arch/gpio.h>
  26 #include <asm/arch/omap.h>
  27 #include <environment.h>
  28 #include <usb.h>
  29 #include <linux/usb/gadget.h>
  30 #include <dwc3-uboot.h>
  31 #include <dwc3-omap-uboot.h>
  32 #include <ti-usb-phy-uboot.h>
  33
  34 #include "../common/board_detect.h"
  35 #include "mux_data.h"
  36
  37 #define board_is_x15()          board_ti_is("BBRDX15_")
  38 #define board_is_x15_revb1()    (board_ti_is("BBRDX15_") && \
  39                                  !strncmp("B.10", board_ti_get_rev(), 3))
  40 #define board_is_x15_revc()     (board_ti_is("BBRDX15_") && \
  41                                  !strncmp("C.00", board_ti_get_rev(), 3))
  42 #define board_is_am572x_evm()   board_ti_is("AM572PM_")
  43 #define board_is_am572x_evm_reva3()     \
  44                                 (board_ti_is("AM572PM_") && \
  45                                  !strncmp("A.30", board_ti_get_rev(), 3))
  46 #define board_is_am572x_idk()   board_ti_is("AM572IDK")
  47 #define board_is_am571x_idk()   board_ti_is("AM571IDK")
  48
  49 #ifdef CONFIG_DRIVER_TI_CPSW
  50 #include <cpsw.h>
  51 #endif
  52
  53 DECLARE_GLOBAL_DATA_PTR;
  54
  55 #define GPIO_ETH_LCD            GPIO_TO_PIN(2, 22)
  56 /* GPIO 7_11 */
  57 #define GPIO_DDR_VTT_EN 203
  58
  59 /* Touch screen controller to identify the LCD */
  60 #define OSD_TS_FT_BUS_ADDRESS   0
  61 #define OSD_TS_FT_CHIP_ADDRESS  0x38
  62 #define OSD_TS_FT_REG_ID        0xA3
  63 /*
  64  * Touchscreen IDs for various OSD panels
  65  * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
  66  */
  67 /* Used on newer osd101t2587 Panels */
  68 #define OSD_TS_FT_ID_5x46       0x54
  69 /* Used on older osd101t2045 Panels */
  70 #define OSD_TS_FT_ID_5606       0x08
  71
  72 #define SYSINFO_BOARD_NAME_MAX_LEN      45
  73
  74 #define TPS65903X_PRIMARY_SECONDARY_PAD2        0xFB
  75 #define TPS65903X_PAD2_POWERHOLD_MASK           0x20
  76
  77 const struct omap_sysinfo sysinfo = {
  78         "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
  79 };
  80
  81 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  82         .dmm_lisa_map_3 = 0x80740300,
  83         .is_ma_present  = 0x1
  84 };
  85
  86 static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
  87         .dmm_lisa_map_3 = 0x80640100,
  88         .is_ma_present  = 0x1
  89 };
  90
  91 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  92 {
  93         if (board_is_am571x_idk())
  94                 *dmm_lisa_regs = &am571x_idk_lisa_regs;
  95         else
  96                 *dmm_lisa_regs = &beagle_x15_lisa_regs;
  97 }
  98
  99 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
 100         .sdram_config_init              = 0x61851b32,
 101         .sdram_config                   = 0x61851b32,
 102         .sdram_config2                  = 0x08000000,
 103         .ref_ctrl                       = 0x000040F1,
 104         .ref_ctrl_final                 = 0x00001035,
 105         .sdram_tim1                     = 0xcccf36ab,
 106         .sdram_tim2                     = 0x308f7fda,
 107         .sdram_tim3                     = 0x409f88a8,
 108         .read_idle_ctrl                 = 0x00050000,
 109         .zq_config                      = 0x5007190b,
 110         .temp_alert_config              = 0x00000000,
 111         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 112         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 113         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 114         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 115         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 116         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 117         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 118         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 119         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 120         .emif_rd_wr_lvl_ctl             = 0x00000000,
 121         .emif_rd_wr_exec_thresh         = 0x00000305
 122 };
 123
 124 /* Ext phy ctrl regs 1-35 */
 125 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
 126         0x10040100,
 127         0x00910091,
 128         0x00950095,
 129         0x009B009B,
 130         0x009E009E,
 131         0x00980098,
 132         0x00340034,
 133         0x00350035,
 134         0x00340034,
 135         0x00310031,
 136         0x00340034,
 137         0x007F007F,
 138         0x007F007F,
 139         0x007F007F,
 140         0x007F007F,
 141         0x007F007F,
 142         0x00480048,
 143         0x004A004A,
 144         0x00520052,
 145         0x00550055,
 146         0x00500050,
 147         0x00000000,
 148         0x00600020,
 149         0x40011080,
 150         0x08102040,
 151         0x0,
 152         0x0,
 153         0x0,
 154         0x0,
 155         0x0,
 156         0x0,
 157         0x0,
 158         0x0,
 159         0x0,
 160         0x0
 161 };
 162
 163 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 164         .sdram_config_init              = 0x61851b32,
 165         .sdram_config                   = 0x61851b32,
 166         .sdram_config2                  = 0x08000000,
 167         .ref_ctrl                       = 0x000040F1,
 168         .ref_ctrl_final                 = 0x00001035,
 169         .sdram_tim1                     = 0xcccf36b3,
 170         .sdram_tim2                     = 0x308f7fda,
 171         .sdram_tim3                     = 0x407f88a8,
 172         .read_idle_ctrl                 = 0x00050000,
 173         .zq_config                      = 0x5007190b,
 174         .temp_alert_config              = 0x00000000,
 175         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 176         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 177         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 178         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 179         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 180         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 181         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 182         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 183         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 184         .emif_rd_wr_lvl_ctl             = 0x00000000,
 185         .emif_rd_wr_exec_thresh         = 0x00000305
 186 };
 187
 188 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
 189         0x10040100,
 190         0x00910091,
 191         0x00950095,
 192         0x009B009B,
 193         0x009E009E,
 194         0x00980098,
 195         0x00340034,
 196         0x00350035,
 197         0x00340034,
 198         0x00310031,
 199         0x00340034,
 200         0x007F007F,
 201         0x007F007F,
 202         0x007F007F,
 203         0x007F007F,
 204         0x007F007F,
 205         0x00480048,
 206         0x004A004A,
 207         0x00520052,
 208         0x00550055,
 209         0x00500050,
 210         0x00000000,
 211         0x00600020,
 212         0x40011080,
 213         0x08102040,
 214         0x0,
 215         0x0,
 216         0x0,
 217         0x0,
 218         0x0,
 219         0x0,
 220         0x0,
 221         0x0,
 222         0x0,
 223         0x0
 224 };
 225
 226 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 227 {
 228         switch (emif_nr) {
 229         case 1:
 230                 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
 231                 break;
 232         case 2:
 233                 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
 234                 break;
 235         }
 236 }
 237
 238 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 239 {
 240         switch (emif_nr) {
 241         case 1:
 242                 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
 243                 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
 244                 break;
 245         case 2:
 246                 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
 247                 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
 248                 break;
 249         }
 250 }
 251
 252 struct vcores_data beagle_x15_volts = {
 253         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 254         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 255         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 256         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 257         .mpu.pmic               = &tps659038,
 258         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 259
 260         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 261         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 262         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 263         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 264         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 265         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 266         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 267         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 268         .eve.pmic               = &tps659038,
 269         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 270
 271         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 272         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 273         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 274         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 275         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 276         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 277         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 278         .gpu.addr               = TPS659038_REG_ADDR_SMPS45,
 279         .gpu.pmic               = &tps659038,
 280         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 281
 282         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 283         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 284         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 285         .core.addr              = TPS659038_REG_ADDR_SMPS6,
 286         .core.pmic              = &tps659038,
 287
 288         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 289         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 290         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 291         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 292         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 293         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 294         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 295         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 296         .iva.pmic               = &tps659038,
 297         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 298 };
 299
 300 struct vcores_data am572x_idk_volts = {
 301         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 302         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 303         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 304         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 305         .mpu.pmic               = &tps659038,
 306         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 307
 308         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 309         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 310         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 311         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 312         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 313         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 314         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 315         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 316         .eve.pmic               = &tps659038,
 317         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 318
 319         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 320         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 321         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 322         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 323         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 324         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 325         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 326         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 327         .gpu.pmic               = &tps659038,
 328         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 329
 330         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 331         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 332         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 333         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 334         .core.pmic              = &tps659038,
 335
 336         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 337         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 338         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 339         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 340         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 341         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 342         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 343         .iva.addr               = TPS659038_REG_ADDR_SMPS8,
 344         .iva.pmic               = &tps659038,
 345         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 346 };
 347
 348 struct vcores_data am571x_idk_volts = {
 349         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 350         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 351         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 352         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 353         .mpu.pmic               = &tps659038,
 354         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 355
 356         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 357         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 358         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 359         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 360         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 361         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 362         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 363         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 364         .eve.pmic               = &tps659038,
 365         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 366
 367         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 368         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 369         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 370         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 371         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 372         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 373         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 374         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 375         .gpu.pmic               = &tps659038,
 376         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 377
 378         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 379         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 380         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 381         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 382         .core.pmic              = &tps659038,
 383
 384         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 385         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 386         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 387         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 388         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 389         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 390         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 391         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 392         .iva.pmic               = &tps659038,
 393         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 394 };
 395
 396 int get_voltrail_opp(int rail_offset)
 397 {
 398         int opp;
 399
 400         switch (rail_offset) {
 401         case VOLT_MPU:
 402                 opp = DRA7_MPU_OPP;
 403                 break;
 404         case VOLT_CORE:
 405                 opp = DRA7_CORE_OPP;
 406                 break;
 407         case VOLT_GPU:
 408                 opp = DRA7_GPU_OPP;
 409                 break;
 410         case VOLT_EVE:
 411                 opp = DRA7_DSPEVE_OPP;
 412                 break;
 413         case VOLT_IVA:
 414                 opp = DRA7_IVA_OPP;
 415                 break;
 416         default:
 417                 opp = OPP_NOM;
 418         }
 419
 420         return opp;
 421 }
 422
 423
 424 #ifdef CONFIG_SPL_BUILD
 425 /* No env to setup for SPL */
 426 static inline void setup_board_eeprom_env(void) { }
 427
 428 /* Override function to read eeprom information */
 429 void do_board_detect(void)
 430 {
 431         int rc;
 432
 433         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 434                                   CONFIG_EEPROM_CHIP_ADDRESS);
 435         if (rc)
 436                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 437 }
 438
 439 #else   /* CONFIG_SPL_BUILD */
 440
 441 /* Override function to read eeprom information: actual i2c read done by SPL*/
 442 void do_board_detect(void)
 443 {
 444         char *bname = NULL;
 445         int rc;
 446
 447         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 448                                   CONFIG_EEPROM_CHIP_ADDRESS);
 449         if (rc)
 450                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 451
 452         if (board_is_x15())
 453                 bname = "BeagleBoard X15";
 454         else if (board_is_am572x_evm())
 455                 bname = "AM572x EVM";
 456         else if (board_is_am572x_idk())
 457                 bname = "AM572x IDK";
 458         else if (board_is_am571x_idk())
 459                 bname = "AM571x IDK";
 460
 461         if (bname)
 462                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 463                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 464 }
 465
 466 static void setup_board_eeprom_env(void)
 467 {
 468         char *name = "beagle_x15";
 469         int rc;
 470
 471         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 472                                   CONFIG_EEPROM_CHIP_ADDRESS);
 473         if (rc)
 474                 goto invalid_eeprom;
 475
 476         if (board_is_x15()) {
 477                 if (board_is_x15_revb1())
 478                         name = "beagle_x15_revb1";
 479                 else if (board_is_x15_revc())
 480                         name = "beagle_x15_revc";
 481                 else
 482                         name = "beagle_x15";
 483         } else if (board_is_am572x_evm()) {
 484                 if (board_is_am572x_evm_reva3())
 485                         name = "am57xx_evm_reva3";
 486                 else
 487                         name = "am57xx_evm";
 488         } else if (board_is_am572x_idk()) {
 489                 name = "am572x_idk";
 490         } else if (board_is_am571x_idk()) {
 491                 name = "am571x_idk";
 492         } else {
 493                 printf("Unidentified board claims %s in eeprom header\n",
 494                        board_ti_get_name());
 495         }
 496
 497 invalid_eeprom:
 498         set_board_info_env(name);
 499 }
 500
 501 #endif  /* CONFIG_SPL_BUILD */
 502
 503 void vcores_init(void)
 504 {
 505         if (board_is_am572x_idk())
 506                 *omap_vcores = &am572x_idk_volts;
 507         else if (board_is_am571x_idk())
 508                 *omap_vcores = &am571x_idk_volts;
 509         else
 510                 *omap_vcores = &beagle_x15_volts;
 511 }
 512
 513 void hw_data_init(void)
 514 {
 515         *prcm = &dra7xx_prcm;
 516         *dplls_data = &dra7xx_dplls;
 517         *ctrl = &dra7xx_ctrl;
 518 }
 519
 520 bool am571x_idk_needs_lcd(void)
 521 {
 522         bool needs_lcd;
 523
 524         gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
 525         if (gpio_get_value(GPIO_ETH_LCD))
 526                 needs_lcd = false;
 527         else
 528                 needs_lcd = true;
 529
 530         gpio_free(GPIO_ETH_LCD);
 531
 532         return needs_lcd;
 533 }
 534
 535 int board_init(void)
 536 {
 537         gpmc_init();
 538         gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
 539
 540         return 0;
 541 }
 542
 543 void am57x_idk_lcd_detect(void)
 544 {
 545         int r = -ENODEV;
 546         char *idk_lcd = "no";
 547         uint8_t buf = 0;
 548
 549         /* Only valid for IDKs */
 550         if (board_is_x15() || board_is_am572x_evm())
 551                 return;
 552
 553         /* Only AM571x IDK has gpio control detect.. so check that */
 554         if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
 555                 goto out;
 556
 557         r = i2c_set_bus_num(OSD_TS_FT_BUS_ADDRESS);
 558         if (r) {
 559                 printf("%s: Failed to set bus address to %d: %d\n",
 560                        __func__, OSD_TS_FT_BUS_ADDRESS, r);
 561                 goto out;
 562         }
 563         r = i2c_probe(OSD_TS_FT_CHIP_ADDRESS);
 564         if (r) {
 565                 /* AM572x IDK has no explicit settings for optional LCD kit */
 566                 if (board_is_am571x_idk()) {
 567                         printf("%s: Touch screen detect failed: %d!\n",
 568                                __func__, r);
 569                 }
 570                 goto out;
 571         }
 572
 573         /* Read FT ID */
 574         r = i2c_read(OSD_TS_FT_CHIP_ADDRESS, OSD_TS_FT_REG_ID, 1, &buf, 1);
 575         if (r) {
 576                 printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
 577                        __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
 578                        OSD_TS_FT_REG_ID, r);
 579                 goto out;
 580         }
 581
 582         switch (buf) {
 583         case OSD_TS_FT_ID_5606:
 584                 idk_lcd = "osd101t2045";
 585                 break;
 586         case OSD_TS_FT_ID_5x46:
 587                 idk_lcd = "osd101t2587";
 588                 break;
 589         default:
 590                 printf("%s: Unidentifed Touch screen ID 0x%02x\n",
 591                        __func__, buf);
 592                 /* we will let default be "no lcd" */
 593         }
 594 out:
 595         env_set("idk_lcd", idk_lcd);
 596         return;
 597 }
 598
 599 int board_late_init(void)
 600 {
 601         setup_board_eeprom_env();
 602         u8 val;
 603
 604         /*
 605          * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
 606          * This is the POWERHOLD-in-Low behavior.
 607          */
 608         palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
 609
 610         /*
 611          * Default FIT boot on HS devices. Non FIT images are not allowed
 612          * on HS devices.
 613          */
 614         if (get_device_type() == HS_DEVICE)
 615                 env_set("boot_fit", "1");
 616
 617         /*
 618          * Set the GPIO7 Pad to POWERHOLD. This has higher priority
 619          * over DEV_CTRL.DEV_ON bit. This can be reset in case of
 620          * PMIC Power off. So to be on the safer side set it back
 621          * to POWERHOLD mode irrespective of the current state.
 622          */
 623         palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 624                            &val);
 625         val = val | TPS65903X_PAD2_POWERHOLD_MASK;
 626         palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 627                             val);
 628
 629         omap_die_id_serial();
 630         omap_set_fastboot_vars();
 631
 632         am57x_idk_lcd_detect();
 633
 634 #if !defined(CONFIG_SPL_BUILD)
 635         board_ti_set_ethaddr(2);
 636 #endif
 637
 638         return 0;
 639 }
 640
 641 void set_muxconf_regs(void)
 642 {
 643         do_set_mux32((*ctrl)->control_padconf_core_base,
 644                      early_padconf, ARRAY_SIZE(early_padconf));
 645 }
 646
 647 #ifdef CONFIG_IODELAY_RECALIBRATION
 648 void recalibrate_iodelay(void)
 649 {
 650         const struct pad_conf_entry *pconf;
 651         const struct iodelay_cfg_entry *iod, *delta_iod;
 652         int pconf_sz, iod_sz, delta_iod_sz = 0;
 653         int ret;
 654
 655         if (board_is_am572x_idk()) {
 656                 pconf = core_padconf_array_essential_am572x_idk;
 657                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
 658                 iod = iodelay_cfg_array_am572x_idk;
 659                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
 660         } else if (board_is_am571x_idk()) {
 661                 pconf = core_padconf_array_essential_am571x_idk;
 662                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
 663                 iod = iodelay_cfg_array_am571x_idk;
 664                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
 665         } else {
 666                 /* Common for X15/GPEVM */
 667                 pconf = core_padconf_array_essential_x15;
 668                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
 669                 /* There never was an SR1.0 X15.. So.. */
 670                 if (omap_revision() == DRA752_ES1_1) {
 671                         iod = iodelay_cfg_array_x15_sr1_1;
 672                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
 673                 } else {
 674                         /* Since full production should switch to SR2.0  */
 675                         iod = iodelay_cfg_array_x15_sr2_0;
 676                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
 677                 }
 678         }
 679
 680         /* Setup I/O isolation */
 681         ret = __recalibrate_iodelay_start();
 682         if (ret)
 683                 goto err;
 684
 685         /* Do the muxing here */
 686         do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 687
 688         /* Now do the weird minor deltas that should be safe */
 689         if (board_is_x15() || board_is_am572x_evm()) {
 690                 if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
 691                     board_is_x15_revc()) {
 692                         pconf = core_padconf_array_delta_x15_sr2_0;
 693                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
 694                 } else {
 695                         pconf = core_padconf_array_delta_x15_sr1_1;
 696                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
 697                 }
 698                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 699         }
 700
 701         if (board_is_am571x_idk()) {
 702                 if (am571x_idk_needs_lcd()) {
 703                         pconf = core_padconf_array_vout_am571x_idk;
 704                         pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
 705                         delta_iod = iodelay_cfg_array_am571x_idk_4port;
 706                         delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
 707
 708                 } else {
 709                         pconf = core_padconf_array_icss1eth_am571x_idk;
 710                         pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
 711                 }
 712                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 713         }
 714
 715         /* Setup IOdelay configuration */
 716         ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
 717         if (delta_iod_sz)
 718                 ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
 719                                      delta_iod_sz);
 720
 721 err:
 722         /* Closeup.. remove isolation */
 723         __recalibrate_iodelay_end(ret);
 724 }
 725 #endif
 726
 727 #if defined(CONFIG_MMC)
 728 int board_mmc_init(bd_t *bis)
 729 {
 730         omap_mmc_init(0, 0, 0, -1, -1);
 731         omap_mmc_init(1, 0, 0, -1, -1);
 732         return 0;
 733 }
 734 #endif
 735
 736 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 737 int spl_start_uboot(void)
 738 {
 739         /* break into full u-boot on 'c' */
 740         if (serial_tstc() && serial_getc() == 'c')
 741                 return 1;
 742
 743 #ifdef CONFIG_SPL_ENV_SUPPORT
 744         env_init();
 745         env_load();
 746         if (getenv_yesno("boot_os") != 1)
 747                 return 1;
 748 #endif
 749
 750         return 0;
 751 }
 752 #endif
 753
 754 #ifdef CONFIG_USB_DWC3
 755 static struct dwc3_device usb_otg_ss2 = {
 756         .maximum_speed = USB_SPEED_HIGH,
 757         .base = DRA7_USB_OTG_SS2_BASE,
 758         .tx_fifo_resize = false,
 759         .index = 1,
 760 };
 761
 762 static struct dwc3_omap_device usb_otg_ss2_glue = {
 763         .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
 764         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 765         .index = 1,
 766 };
 767
 768 static struct ti_usb_phy_device usb_phy2_device = {
 769         .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
 770         .index = 1,
 771 };
 772
 773 int usb_gadget_handle_interrupts(int index)
 774 {
 775         u32 status;
 776
 777         status = dwc3_omap_uboot_interrupt_status(index);
 778         if (status)
 779                 dwc3_uboot_handle_interrupt(index);
 780
 781         return 0;
 782 }
 783 #endif /* CONFIG_USB_DWC3 */
 784
 785 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 786 int omap_xhci_board_usb_init(int index, enum usb_init_type init)
 787 {
 788         enable_usb_clocks(index);
 789         switch (index) {
 790         case 0:
 791                 if (init == USB_INIT_DEVICE) {
 792                         printf("port %d can't be used as device\n", index);
 793                         disable_usb_clocks(index);
 794                         return -EINVAL;
 795                 }
 796                 break;
 797         case 1:
 798                 if (init == USB_INIT_DEVICE) {
 799 #ifdef CONFIG_USB_DWC3
 800                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 801                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 802                         ti_usb_phy_uboot_init(&usb_phy2_device);
 803                         dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 804                         dwc3_uboot_init(&usb_otg_ss2);
 805 #endif
 806                 } else {
 807                         printf("port %d can't be used as host\n", index);
 808                         disable_usb_clocks(index);
 809                         return -EINVAL;
 810                 }
 811
 812                 break;
 813         default:
 814                 printf("Invalid Controller Index\n");
 815         }
 816
 817         return 0;
 818 }
 819
 820 int omap_xhci_board_usb_cleanup(int index, enum usb_init_type init)
 821 {
 822 #ifdef CONFIG_USB_DWC3
 823         switch (index) {
 824         case 0:
 825         case 1:
 826                 if (init == USB_INIT_DEVICE) {
 827                         ti_usb_phy_uboot_exit(index);
 828                         dwc3_uboot_exit(index);
 829                         dwc3_omap_uboot_exit(index);
 830                 }
 831                 break;
 832         default:
 833                 printf("Invalid Controller Index\n");
 834         }
 835 #endif
 836         disable_usb_clocks(index);
 837         return 0;
 838 }
 839 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
 840
 841 #ifdef CONFIG_DRIVER_TI_CPSW
 842
 843 /* Delay value to add to calibrated value */
 844 #define RGMII0_TXCTL_DLY_VAL            ((0x3 << 5) + 0x8)
 845 #define RGMII0_TXD0_DLY_VAL             ((0x3 << 5) + 0x8)
 846 #define RGMII0_TXD1_DLY_VAL             ((0x3 << 5) + 0x2)
 847 #define RGMII0_TXD2_DLY_VAL             ((0x4 << 5) + 0x0)
 848 #define RGMII0_TXD3_DLY_VAL             ((0x4 << 5) + 0x0)
 849 #define VIN2A_D13_DLY_VAL               ((0x3 << 5) + 0x8)
 850 #define VIN2A_D17_DLY_VAL               ((0x3 << 5) + 0x8)
 851 #define VIN2A_D16_DLY_VAL               ((0x3 << 5) + 0x2)
 852 #define VIN2A_D15_DLY_VAL               ((0x4 << 5) + 0x0)
 853 #define VIN2A_D14_DLY_VAL               ((0x4 << 5) + 0x0)
 854
 855 static void cpsw_control(int enabled)
 856 {
 857         /* VTP can be added here */
 858 }
 859
 860 static struct cpsw_slave_data cpsw_slaves[] = {
 861         {
 862                 .slave_reg_ofs  = 0x208,
 863                 .sliver_reg_ofs = 0xd80,
 864                 .phy_addr       = 1,
 865         },
 866         {
 867                 .slave_reg_ofs  = 0x308,
 868                 .sliver_reg_ofs = 0xdc0,
 869                 .phy_addr       = 2,
 870         },
 871 };
 872
 873 static struct cpsw_platform_data cpsw_data = {
 874         .mdio_base              = CPSW_MDIO_BASE,
 875         .cpsw_base              = CPSW_BASE,
 876         .mdio_div               = 0xff,
 877         .channels               = 8,
 878         .cpdma_reg_ofs          = 0x800,
 879         .slaves                 = 1,
 880         .slave_data             = cpsw_slaves,
 881         .ale_reg_ofs            = 0xd00,
 882         .ale_entries            = 1024,
 883         .host_port_reg_ofs      = 0x108,
 884         .hw_stats_reg_ofs       = 0x900,
 885         .bd_ram_ofs             = 0x2000,
 886         .mac_control            = (1 << 5),
 887         .control                = cpsw_control,
 888         .host_port_num          = 0,
 889         .version                = CPSW_CTRL_VERSION_2,
 890 };
 891
 892 static u64 mac_to_u64(u8 mac[6])
 893 {
 894         int i;
 895         u64 addr = 0;
 896
 897         for (i = 0; i < 6; i++) {
 898                 addr <<= 8;
 899                 addr |= mac[i];
 900         }
 901
 902         return addr;
 903 }
 904
 905 static void u64_to_mac(u64 addr, u8 mac[6])
 906 {
 907         mac[5] = addr;
 908         mac[4] = addr >> 8;
 909         mac[3] = addr >> 16;
 910         mac[2] = addr >> 24;
 911         mac[1] = addr >> 32;
 912         mac[0] = addr >> 40;
 913 }
 914
 915 int board_eth_init(bd_t *bis)
 916 {
 917         int ret;
 918         uint8_t mac_addr[6];
 919         uint32_t mac_hi, mac_lo;
 920         uint32_t ctrl_val;
 921         int i;
 922         u64 mac1, mac2;
 923         u8 mac_addr1[6], mac_addr2[6];
 924         int num_macs;
 925
 926         /* try reading mac address from efuse */
 927         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 928         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 929         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 930         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 931         mac_addr[2] = mac_hi & 0xFF;
 932         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 933         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 934         mac_addr[5] = mac_lo & 0xFF;
 935
 936         if (!getenv("ethaddr")) {
 937                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 938
 939                 if (is_valid_ethaddr(mac_addr))
 940                         eth_setenv_enetaddr("ethaddr", mac_addr);
 941         }
 942
 943         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 944         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 945         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 946         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 947         mac_addr[2] = mac_hi & 0xFF;
 948         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 949         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 950         mac_addr[5] = mac_lo & 0xFF;
 951
 952         if (!getenv("eth1addr")) {
 953                 if (is_valid_ethaddr(mac_addr))
 954                         eth_setenv_enetaddr("eth1addr", mac_addr);
 955         }
 956
 957         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
 958         ctrl_val |= 0x22;
 959         writel(ctrl_val, (*ctrl)->control_core_control_io1);
 960
 961         /* The phy address for the AM57xx IDK are different than x15 */
 962         if (board_is_am572x_idk() || board_is_am571x_idk()) {
 963                 cpsw_data.slave_data[0].phy_addr = 0;
 964                 cpsw_data.slave_data[1].phy_addr = 1;
 965         }
 966
 967         ret = cpsw_register(&cpsw_data);
 968         if (ret < 0)
 969                 printf("Error %d registering CPSW switch\n", ret);
 970
 971         /*
 972          * Export any Ethernet MAC addresses from EEPROM.
 973          * On AM57xx the 2 MAC addresses define the address range
 974          */
 975         board_ti_get_eth_mac_addr(0, mac_addr1);
 976         board_ti_get_eth_mac_addr(1, mac_addr2);
 977
 978         if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
 979                 mac1 = mac_to_u64(mac_addr1);
 980                 mac2 = mac_to_u64(mac_addr2);
 981
 982                 /* must contain an address range */
 983                 num_macs = mac2 - mac1 + 1;
 984                 /* <= 50 to protect against user programming error */
 985                 if (num_macs > 0 && num_macs <= 50) {
 986                         for (i = 0; i < num_macs; i++) {
 987                                 u64_to_mac(mac1 + i, mac_addr);
 988                                 if (is_valid_ethaddr(mac_addr)) {
 989                                         eth_setenv_enetaddr_by_index("eth",
 990                                                                      i + 2,
 991                                                                      mac_addr);
 992                                 }
 993                         }
 994                 }
 995         }
 996
 997         return ret;
 998 }
 999 #endif
1000
1001 #ifdef CONFIG_BOARD_EARLY_INIT_F
1002 /* VTT regulator enable */
1003 static inline void vtt_regulator_enable(void)
1004 {
1005         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1006                 return;
1007
1008         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1009         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1010 }
1011
1012 int board_early_init_f(void)
1013 {
1014         vtt_regulator_enable();
1015         return 0;
1016 }
1017 #endif
1018
1019 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1020 int ft_board_setup(void *blob, bd_t *bd)
1021 {
1022         ft_cpu_setup(blob, bd);
1023
1024         return 0;
1025 }
1026 #endif
1027
1028 #ifdef CONFIG_SPL_LOAD_FIT
1029 int board_fit_config_name_match(const char *name)
1030 {
1031         if (board_is_x15()) {
1032                 if (board_is_x15_revb1()) {
1033                         if (!strcmp(name, "am57xx-beagle-x15-revb1"))
1034                                 return 0;
1035                 } else if (!strcmp(name, "am57xx-beagle-x15")) {
1036                         return 0;
1037                 }
1038         } else if (board_is_am572x_evm() &&
1039                    !strcmp(name, "am57xx-beagle-x15")) {
1040                 return 0;
1041         } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
1042                 return 0;
1043         } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
1044                 return 0;
1045         }
1046
1047         return -1;
1048 }
1049 #endif
1050
1051 #ifdef CONFIG_TI_SECURE_DEVICE
1052 void board_fit_image_post_process(void **p_image, size_t *p_size)
1053 {
1054         secure_boot_verify_image(p_image, p_size);
1055 }
1056
1057 void board_tee_image_process(ulong tee_image, size_t tee_size)
1058 {
1059         secure_tee_install((u32)tee_image);
1060 }
1061
1062 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
1063 #endif