board/ti/am43xx/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Board functions for TI AM43XX based boards
   6  *
   7  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
   8  */
   9
  10 #include <common.h>
  11 #include <environment.h>
  12 #include <i2c.h>
  13 #include <linux/errno.h>
  14 #include <spl.h>
  15 #include <usb.h>
  16 #include <asm/omap_sec_common.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/arch/mux.h>
  20 #include <asm/arch/ddr_defs.h>
  21 #include <asm/arch/gpio.h>
  22 #include <asm/emif.h>
  23 #include <asm/omap_common.h>
  24 #include "../common/board_detect.h"
  25 #include "board.h"
  26 #include <power/pmic.h>
  27 #include <power/tps65218.h>
  28 #include <power/tps62362.h>
  29 #include <miiphy.h>
  30 #include <cpsw.h>
  31 #include <linux/usb/gadget.h>
  32 #include <dwc3-uboot.h>
  33 #include <dwc3-omap-uboot.h>
  34 #include <ti-usb-phy-uboot.h>
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  39
  40 /*
  41  * Read header information from EEPROM into global structure.
  42  */
  43 #ifdef CONFIG_TI_I2C_BOARD_DETECT
  44 void do_board_detect(void)
  45 {
  46         /* Ensure I2C is initialized for EEPROM access*/
  47         gpi2c_init();
  48         if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  49                                  CONFIG_EEPROM_CHIP_ADDRESS))
  50                 printf("ti_i2c_eeprom_init failed\n");
  51 }
  52 #endif
  53
  54 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  55
  56 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
  57         {       /* 19.2 MHz */
  58                 {125, 3, 2, -1, -1, -1, -1},    /* OPP 50 */
  59                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  60                 {125, 3, 1, -1, -1, -1, -1},    /* OPP 100 */
  61                 {150, 3, 1, -1, -1, -1, -1},    /* OPP 120 */
  62                 {125, 2, 1, -1, -1, -1, -1},    /* OPP TB */
  63                 {625, 11, 1, -1, -1, -1, -1}    /* OPP NT */
  64         },
  65         {       /* 24 MHz */
  66                 {300, 23, 1, -1, -1, -1, -1},   /* OPP 50 */
  67                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  68                 {600, 23, 1, -1, -1, -1, -1},   /* OPP 100 */
  69                 {720, 23, 1, -1, -1, -1, -1},   /* OPP 120 */
  70                 {800, 23, 1, -1, -1, -1, -1},   /* OPP TB */
  71                 {1000, 23, 1, -1, -1, -1, -1}   /* OPP NT */
  72         },
  73         {       /* 25 MHz */
  74                 {300, 24, 1, -1, -1, -1, -1},   /* OPP 50 */
  75                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  76                 {600, 24, 1, -1, -1, -1, -1},   /* OPP 100 */
  77                 {720, 24, 1, -1, -1, -1, -1},   /* OPP 120 */
  78                 {800, 24, 1, -1, -1, -1, -1},   /* OPP TB */
  79                 {1000, 24, 1, -1, -1, -1, -1}   /* OPP NT */
  80         },
  81         {       /* 26 MHz */
  82                 {300, 25, 1, -1, -1, -1, -1},   /* OPP 50 */
  83                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  84                 {600, 25, 1, -1, -1, -1, -1},   /* OPP 100 */
  85                 {720, 25, 1, -1, -1, -1, -1},   /* OPP 120 */
  86                 {800, 25, 1, -1, -1, -1, -1},   /* OPP TB */
  87                 {1000, 25, 1, -1, -1, -1, -1}   /* OPP NT */
  88         },
  89 };
  90
  91 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
  92                 {625, 11, -1, -1, 10, 8, 4},    /* 19.2 MHz */
  93                 {1000, 23, -1, -1, 10, 8, 4},   /* 24 MHz */
  94                 {1000, 24, -1, -1, 10, 8, 4},   /* 25 MHz */
  95                 {1000, 25, -1, -1, 10, 8, 4}    /* 26 MHz */
  96 };
  97
  98 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
  99                 {400, 7, 5, -1, -1, -1, -1},    /* 19.2 MHz */
 100                 {400, 9, 5, -1, -1, -1, -1},    /* 24 MHz */
 101                 {384, 9, 5, -1, -1, -1, -1},    /* 25 MHz */
 102                 {480, 12, 5, -1, -1, -1, -1}    /* 26 MHz */
 103 };
 104
 105 const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
 106                 {665, 47, 1, -1, 4, -1, -1}, /*19.2*/
 107                 {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
 108                 {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
 109                 {133, 12, 1, -1, 4, -1, -1}  /* 26 MHz */
 110 };
 111
 112 const struct dpll_params gp_evm_dpll_ddr = {
 113                 50, 2, 1, -1, 2, -1, -1};
 114
 115 static const struct dpll_params idk_dpll_ddr = {
 116         400, 23, 1, -1, 2, -1, -1
 117 };
 118
 119 static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
 120         0x00500050,
 121         0x00350035,
 122         0x00350035,
 123         0x00350035,
 124         0x00350035,
 125         0x00350035,
 126         0x00000000,
 127         0x00000000,
 128         0x00000000,
 129         0x00000000,
 130         0x00000000,
 131         0x00000000,
 132         0x00000000,
 133         0x00000000,
 134         0x00000000,
 135         0x00000000,
 136         0x00000000,
 137         0x00000000,
 138         0x40001000,
 139         0x08102040
 140 };
 141
 142 const struct ctrl_ioregs ioregs_lpddr2 = {
 143         .cm0ioctl               = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
 144         .cm1ioctl               = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
 145         .cm2ioctl               = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
 146         .dt0ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 147         .dt1ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 148         .dt2ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 149         .dt3ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 150         .emif_sdram_config_ext  = 0x1,
 151 };
 152
 153 const struct emif_regs emif_regs_lpddr2 = {
 154         .sdram_config                   = 0x808012BA,
 155         .ref_ctrl                       = 0x0000040D,
 156         .sdram_tim1                     = 0xEA86B411,
 157         .sdram_tim2                     = 0x103A094A,
 158         .sdram_tim3                     = 0x0F6BA37F,
 159         .read_idle_ctrl                 = 0x00050000,
 160         .zq_config                      = 0x50074BE4,
 161         .temp_alert_config              = 0x0,
 162         .emif_rd_wr_lvl_rmp_win         = 0x0,
 163         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 164         .emif_rd_wr_lvl_ctl             = 0x0,
 165         .emif_ddr_phy_ctlr_1            = 0x0E284006,
 166         .emif_rd_wr_exec_thresh         = 0x80000405,
 167         .emif_ddr_ext_phy_ctrl_1        = 0x04010040,
 168         .emif_ddr_ext_phy_ctrl_2        = 0x00500050,
 169         .emif_ddr_ext_phy_ctrl_3        = 0x00500050,
 170         .emif_ddr_ext_phy_ctrl_4        = 0x00500050,
 171         .emif_ddr_ext_phy_ctrl_5        = 0x00500050,
 172         .emif_prio_class_serv_map       = 0x80000001,
 173         .emif_connect_id_serv_1_map     = 0x80000094,
 174         .emif_connect_id_serv_2_map     = 0x00000000,
 175         .emif_cos_config                        = 0x000FFFFF
 176 };
 177
 178 const struct ctrl_ioregs ioregs_ddr3 = {
 179         .cm0ioctl               = DDR3_ADDRCTRL_IOCTRL_VALUE,
 180         .cm1ioctl               = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
 181         .cm2ioctl               = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
 182         .dt0ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 183         .dt1ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 184         .dt2ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 185         .dt3ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 186         .emif_sdram_config_ext  = 0xc163,
 187 };
 188
 189 const struct emif_regs ddr3_emif_regs_400Mhz = {
 190         .sdram_config                   = 0x638413B2,
 191         .ref_ctrl                       = 0x00000C30,
 192         .sdram_tim1                     = 0xEAAAD4DB,
 193         .sdram_tim2                     = 0x266B7FDA,
 194         .sdram_tim3                     = 0x107F8678,
 195         .read_idle_ctrl                 = 0x00050000,
 196         .zq_config                      = 0x50074BE4,
 197         .temp_alert_config              = 0x0,
 198         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 199         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 200         .emif_ddr_ext_phy_ctrl_2        = 0x00400040,
 201         .emif_ddr_ext_phy_ctrl_3        = 0x00400040,
 202         .emif_ddr_ext_phy_ctrl_4        = 0x00400040,
 203         .emif_ddr_ext_phy_ctrl_5        = 0x00400040,
 204         .emif_rd_wr_lvl_rmp_win         = 0x0,
 205         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 206         .emif_rd_wr_lvl_ctl             = 0x0,
 207         .emif_rd_wr_exec_thresh         = 0x80000405,
 208         .emif_prio_class_serv_map       = 0x80000001,
 209         .emif_connect_id_serv_1_map     = 0x80000094,
 210         .emif_connect_id_serv_2_map     = 0x00000000,
 211         .emif_cos_config                = 0x000FFFFF
 212 };
 213
 214 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
 215 const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
 216         .sdram_config                   = 0x638413B2,
 217         .ref_ctrl                       = 0x00000C30,
 218         .sdram_tim1                     = 0xEAAAD4DB,
 219         .sdram_tim2                     = 0x266B7FDA,
 220         .sdram_tim3                     = 0x107F8678,
 221         .read_idle_ctrl                 = 0x00050000,
 222         .zq_config                      = 0x50074BE4,
 223         .temp_alert_config              = 0x0,
 224         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 225         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 226         .emif_ddr_ext_phy_ctrl_2        = 0x00000065,
 227         .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
 228         .emif_ddr_ext_phy_ctrl_4        = 0x000000B5,
 229         .emif_ddr_ext_phy_ctrl_5        = 0x000000E5,
 230         .emif_rd_wr_exec_thresh         = 0x80000405,
 231         .emif_prio_class_serv_map       = 0x80000001,
 232         .emif_connect_id_serv_1_map     = 0x80000094,
 233         .emif_connect_id_serv_2_map     = 0x00000000,
 234         .emif_cos_config                = 0x000FFFFF
 235 };
 236
 237 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
 238 const struct emif_regs ddr3_emif_regs_400Mhz_production = {
 239         .sdram_config                   = 0x638413B2,
 240         .ref_ctrl                       = 0x00000C30,
 241         .sdram_tim1                     = 0xEAAAD4DB,
 242         .sdram_tim2                     = 0x266B7FDA,
 243         .sdram_tim3                     = 0x107F8678,
 244         .read_idle_ctrl                 = 0x00050000,
 245         .zq_config                      = 0x50074BE4,
 246         .temp_alert_config              = 0x0,
 247         .emif_ddr_phy_ctlr_1            = 0x00048008,
 248         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 249         .emif_ddr_ext_phy_ctrl_2        = 0x00000066,
 250         .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
 251         .emif_ddr_ext_phy_ctrl_4        = 0x000000B9,
 252         .emif_ddr_ext_phy_ctrl_5        = 0x000000E6,
 253         .emif_rd_wr_exec_thresh         = 0x80000405,
 254         .emif_prio_class_serv_map       = 0x80000001,
 255         .emif_connect_id_serv_1_map     = 0x80000094,
 256         .emif_connect_id_serv_2_map     = 0x00000000,
 257         .emif_cos_config                = 0x000FFFFF
 258 };
 259
 260 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
 261         .sdram_config                   = 0x638413b2,
 262         .sdram_config2                  = 0x00000000,
 263         .ref_ctrl                       = 0x00000c30,
 264         .sdram_tim1                     = 0xeaaad4db,
 265         .sdram_tim2                     = 0x266b7fda,
 266         .sdram_tim3                     = 0x107f8678,
 267         .read_idle_ctrl                 = 0x00050000,
 268         .zq_config                      = 0x50074be4,
 269         .temp_alert_config              = 0x0,
 270         .emif_ddr_phy_ctlr_1            = 0x0e084008,
 271         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 272         .emif_ddr_ext_phy_ctrl_2        = 0x89,
 273         .emif_ddr_ext_phy_ctrl_3        = 0x90,
 274         .emif_ddr_ext_phy_ctrl_4        = 0x8e,
 275         .emif_ddr_ext_phy_ctrl_5        = 0x8d,
 276         .emif_rd_wr_lvl_rmp_win         = 0x0,
 277         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 278         .emif_rd_wr_lvl_ctl             = 0x00000000,
 279         .emif_rd_wr_exec_thresh         = 0x80000000,
 280         .emif_prio_class_serv_map       = 0x80000001,
 281         .emif_connect_id_serv_1_map     = 0x80000094,
 282         .emif_connect_id_serv_2_map     = 0x00000000,
 283         .emif_cos_config                = 0x000FFFFF
 284 };
 285
 286 static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
 287         .sdram_config                   = 0x61a11b32,
 288         .sdram_config2                  = 0x00000000,
 289         .ref_ctrl                       = 0x00000c30,
 290         .sdram_tim1                     = 0xeaaad4db,
 291         .sdram_tim2                     = 0x266b7fda,
 292         .sdram_tim3                     = 0x107f8678,
 293         .read_idle_ctrl                 = 0x00050000,
 294         .zq_config                      = 0x50074be4,
 295         .temp_alert_config              = 0x00000000,
 296         .emif_ddr_phy_ctlr_1            = 0x00008009,
 297         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 298         .emif_ddr_ext_phy_ctrl_2        = 0x00000040,
 299         .emif_ddr_ext_phy_ctrl_3        = 0x0000003e,
 300         .emif_ddr_ext_phy_ctrl_4        = 0x00000051,
 301         .emif_ddr_ext_phy_ctrl_5        = 0x00000051,
 302         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 303         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 304         .emif_rd_wr_lvl_ctl             = 0x00000000,
 305         .emif_rd_wr_exec_thresh         = 0x00000405,
 306         .emif_prio_class_serv_map       = 0x00000000,
 307         .emif_connect_id_serv_1_map     = 0x00000000,
 308         .emif_connect_id_serv_2_map     = 0x00000000,
 309         .emif_cos_config                = 0x00ffffff
 310 };
 311
 312 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
 313 {
 314         if (board_is_eposevm()) {
 315                 *regs = ext_phy_ctrl_const_base_lpddr2;
 316                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
 317         }
 318
 319         return;
 320 }
 321
 322 const struct dpll_params *get_dpll_ddr_params(void)
 323 {
 324         int ind = get_sys_clk_index();
 325
 326         if (board_is_eposevm())
 327                 return &epos_evm_dpll_ddr[ind];
 328         else if (board_is_evm() || board_is_sk())
 329                 return &gp_evm_dpll_ddr;
 330         else if (board_is_idk())
 331                 return &idk_dpll_ddr;
 332
 333         printf(" Board '%s' not supported\n", board_ti_get_name());
 334         return NULL;
 335 }
 336
 337
 338 /*
 339  * get_opp_offset:
 340  * Returns the index for safest OPP of the device to boot.
 341  * max_off:     Index of the MAX OPP in DEV ATTRIBUTE register.
 342  * min_off:     Index of the MIN OPP in DEV ATTRIBUTE register.
 343  * This data is read from dev_attribute register which is e-fused.
 344  * A'1' in bit indicates OPP disabled and not available, a '0' indicates
 345  * OPP available. Lowest OPP starts with min_off. So returning the
 346  * bit with rightmost '0'.
 347  */
 348 static int get_opp_offset(int max_off, int min_off)
 349 {
 350         struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
 351         int opp, offset, i;
 352
 353         /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
 354         opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
 355
 356         for (i = max_off; i >= min_off; i--) {
 357                 offset = opp & (1 << i);
 358                 if (!offset)
 359                         return i;
 360         }
 361
 362         return min_off;
 363 }
 364
 365 const struct dpll_params *get_dpll_mpu_params(void)
 366 {
 367         int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
 368         u32 ind = get_sys_clk_index();
 369
 370         return &dpll_mpu[ind][opp];
 371 }
 372
 373 const struct dpll_params *get_dpll_core_params(void)
 374 {
 375         int ind = get_sys_clk_index();
 376
 377         return &dpll_core[ind];
 378 }
 379
 380 const struct dpll_params *get_dpll_per_params(void)
 381 {
 382         int ind = get_sys_clk_index();
 383
 384         return &dpll_per[ind];
 385 }
 386
 387 void scale_vcores_generic(u32 m)
 388 {
 389         int mpu_vdd, ddr_volt;
 390
 391 #ifndef CONFIG_DM_I2C
 392         if (i2c_probe(TPS65218_CHIP_PM))
 393                 return;
 394 #else
 395         if (power_tps65218_init(0))
 396                 return;
 397 #endif
 398
 399         switch (m) {
 400         case 1000:
 401                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
 402                 break;
 403         case 800:
 404                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
 405                 break;
 406         case 720:
 407                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
 408                 break;
 409         case 600:
 410                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
 411                 break;
 412         case 300:
 413                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
 414                 break;
 415         default:
 416                 puts("Unknown MPU clock, not scaling\n");
 417                 return;
 418         }
 419
 420         /* Set DCDC1 (CORE) voltage to 1.1V */
 421         if (tps65218_voltage_update(TPS65218_DCDC1,
 422                                     TPS65218_DCDC_VOLT_SEL_1100MV)) {
 423                 printf("%s failure\n", __func__);
 424                 return;
 425         }
 426
 427         /* Set DCDC2 (MPU) voltage */
 428         if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
 429                 printf("%s failure\n", __func__);
 430                 return;
 431         }
 432
 433         if (board_is_eposevm())
 434                 ddr_volt = TPS65218_DCDC3_VOLT_SEL_1200MV;
 435         else
 436                 ddr_volt = TPS65218_DCDC3_VOLT_SEL_1350MV;
 437
 438         /* Set DCDC3 (DDR) voltage */
 439         if (tps65218_voltage_update(TPS65218_DCDC3, ddr_volt)) {
 440                 printf("%s failure\n", __func__);
 441                 return;
 442         }
 443 }
 444
 445 void scale_vcores_idk(u32 m)
 446 {
 447         int mpu_vdd;
 448
 449 #ifndef CONFIG_DM_I2C
 450         if (i2c_probe(TPS62362_I2C_ADDR))
 451                 return;
 452 #else
 453         if (power_tps62362_init(0))
 454                 return;
 455 #endif
 456
 457         switch (m) {
 458         case 1000:
 459                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
 460                 break;
 461         case 800:
 462                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
 463                 break;
 464         case 720:
 465                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
 466                 break;
 467         case 600:
 468                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
 469                 break;
 470         case 300:
 471                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
 472                 break;
 473         default:
 474                 puts("Unknown MPU clock, not scaling\n");
 475                 return;
 476         }
 477         /* Set VDD_MPU voltage */
 478         if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
 479                 printf("%s failure\n", __func__);
 480                 return;
 481         }
 482 }
 483 void gpi2c_init(void)
 484 {
 485         /* When needed to be invoked prior to BSS initialization */
 486         static bool first_time = true;
 487
 488         if (first_time) {
 489                 enable_i2c0_pin_mux();
 490 #ifndef CONFIG_DM_I2C
 491                 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
 492                          CONFIG_SYS_OMAP24_I2C_SLAVE);
 493 #endif
 494                 first_time = false;
 495         }
 496 }
 497
 498 void scale_vcores(void)
 499 {
 500         const struct dpll_params *mpu_params;
 501
 502         /* Ensure I2C is initialized for PMIC configuration */
 503         gpi2c_init();
 504
 505         /* Get the frequency */
 506         mpu_params = get_dpll_mpu_params();
 507
 508         if (board_is_idk())
 509                 scale_vcores_idk(mpu_params->m);
 510         else
 511                 scale_vcores_generic(mpu_params->m);
 512 }
 513
 514 void set_uart_mux_conf(void)
 515 {
 516         enable_uart0_pin_mux();
 517 }
 518
 519 void set_mux_conf_regs(void)
 520 {
 521         enable_board_pin_mux();
 522 }
 523
 524 static void enable_vtt_regulator(void)
 525 {
 526         u32 temp;
 527
 528         /* enable module */
 529         writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
 530
 531         /* enable output for GPIO5_7 */
 532         writel(GPIO_SETDATAOUT(7),
 533                AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
 534         temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 535         temp = temp & ~(GPIO_OE_ENABLE(7));
 536         writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 537 }
 538
 539 enum {
 540         RTC_BOARD_EPOS = 1,
 541         RTC_BOARD_EVM14,
 542         RTC_BOARD_EVM12,
 543         RTC_BOARD_GPEVM,
 544         RTC_BOARD_SK,
 545 };
 546
 547 /*
 548  * In the rtc_only+DRR in self-refresh boot path we have the board type info
 549  * in the rtc scratch pad register hence we bypass the costly i2c reads to
 550  * eeprom and directly programthe board name string
 551  */
 552 void rtc_only_update_board_type(u32 btype)
 553 {
 554         const char *name = "";
 555         const char *rev = "1.0";
 556
 557         switch (btype) {
 558         case RTC_BOARD_EPOS:
 559                 name = "AM43EPOS";
 560                 break;
 561         case RTC_BOARD_EVM14:
 562                 name = "AM43__GP";
 563                 rev = "1.4";
 564                 break;
 565         case RTC_BOARD_EVM12:
 566                 name = "AM43__GP";
 567                 rev = "1.2";
 568                 break;
 569         case RTC_BOARD_GPEVM:
 570                 name = "AM43__GP";
 571                 break;
 572         case RTC_BOARD_SK:
 573                 name = "AM43__SK";
 574                 break;
 575         }
 576         ti_i2c_eeprom_am_set(name, rev);
 577 }
 578
 579 u32 rtc_only_get_board_type(void)
 580 {
 581         if (board_is_eposevm())
 582                 return RTC_BOARD_EPOS;
 583         else if (board_is_evm_14_or_later())
 584                 return RTC_BOARD_EVM14;
 585         else if (board_is_evm_12_or_later())
 586                 return RTC_BOARD_EVM12;
 587         else if (board_is_gpevm())
 588                 return RTC_BOARD_GPEVM;
 589         else if (board_is_sk())
 590                 return RTC_BOARD_SK;
 591
 592         return 0;
 593 }
 594
 595 void sdram_init(void)
 596 {
 597         /*
 598          * EPOS EVM has 1GB LPDDR2 connected to EMIF.
 599          * GP EMV has 1GB DDR3 connected to EMIF
 600          * along with VTT regulator.
 601          */
 602         if (board_is_eposevm()) {
 603                 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
 604         } else if (board_is_evm_14_or_later()) {
 605                 enable_vtt_regulator();
 606                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 607                            &ddr3_emif_regs_400Mhz_production, 0);
 608         } else if (board_is_evm_12_or_later()) {
 609                 enable_vtt_regulator();
 610                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 611                            &ddr3_emif_regs_400Mhz_beta, 0);
 612         } else if (board_is_evm()) {
 613                 enable_vtt_regulator();
 614                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 615                            &ddr3_emif_regs_400Mhz, 0);
 616         } else if (board_is_sk()) {
 617                 config_ddr(400, &ioregs_ddr3, NULL, NULL,
 618                            &ddr3_sk_emif_regs_400Mhz, 0);
 619         } else if (board_is_idk()) {
 620                 config_ddr(400, &ioregs_ddr3, NULL, NULL,
 621                            &ddr3_idk_emif_regs_400Mhz, 0);
 622         }
 623 }
 624 #endif
 625
 626 /* setup board specific PMIC */
 627 int power_init_board(void)
 628 {
 629         int rc;
 630 #ifndef CONFIG_DM_I2C
 631         struct pmic *p = NULL;
 632 #endif
 633         if (board_is_idk()) {
 634                 rc = power_tps62362_init(0);
 635                 if (rc)
 636                         goto done;
 637 #ifndef CONFIG_DM_I2C
 638                 p = pmic_get("TPS62362");
 639                 if (!p || pmic_probe(p))
 640                         goto done;
 641 #endif
 642                 puts("PMIC:  TPS62362\n");
 643         } else {
 644                 rc = power_tps65218_init(0);
 645                 if (rc)
 646                         goto done;
 647 #ifndef CONFIG_DM_I2C
 648                 p = pmic_get("TPS65218_PMIC");
 649                 if (!p || pmic_probe(p))
 650                         goto done;
 651 #endif
 652                 puts("PMIC:  TPS65218\n");
 653         }
 654 done:
 655         return 0;
 656 }
 657
 658 int board_init(void)
 659 {
 660         struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
 661         u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
 662             modena_init0_bw_integer, modena_init0_watermark_0;
 663
 664         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 665         gpmc_init();
 666
 667         /*
 668          * Call this to initialize *ctrl again
 669          */
 670         hw_data_init();
 671
 672         /* Clear all important bits for DSS errata that may need to be tweaked*/
 673         mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
 674                            MREQPRIO_0_SAB_INIT0_MASK;
 675
 676         mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
 677
 678         modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
 679                                            BW_LIMITER_BW_FRAC_MASK;
 680
 681         modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
 682                                         BW_LIMITER_BW_INT_MASK;
 683
 684         modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
 685                                          BW_LIMITER_BW_WATERMARK_MASK;
 686
 687         /* Setting MReq Priority of the DSS*/
 688         mreqprio_0 |= 0x77;
 689
 690         /*
 691          * Set L3 Fast Configuration Register
 692          * Limiting bandwith for ARM core to 700 MBPS
 693          */
 694         modena_init0_bw_fractional |= 0x10;
 695         modena_init0_bw_integer |= 0x3;
 696
 697         writel(mreqprio_0, &cdev->mreqprio_0);
 698         writel(mreqprio_1, &cdev->mreqprio_1);
 699
 700         writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
 701         writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
 702         writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
 703
 704         return 0;
 705 }
 706
 707 #ifdef CONFIG_BOARD_LATE_INIT
 708 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 709 static int device_okay(const char *path)
 710 {
 711         int node;
 712
 713         node = fdt_path_offset(gd->fdt_blob, path);
 714         if (node < 0)
 715                 return 0;
 716
 717         return fdtdec_get_is_enabled(gd->fdt_blob, node);
 718 }
 719 #endif
 720
 721 int board_late_init(void)
 722 {
 723 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 724         set_board_info_env(NULL);
 725
 726         /*
 727          * Default FIT boot on HS devices. Non FIT images are not allowed
 728          * on HS devices.
 729          */
 730         if (get_device_type() == HS_DEVICE)
 731                 env_set("boot_fit", "1");
 732 #endif
 733
 734 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 735         if (device_okay("/ocp/omap_dwc3@48380000"))
 736                 enable_usb_clocks(0);
 737         if (device_okay("/ocp/omap_dwc3@483c0000"))
 738                 enable_usb_clocks(1);
 739 #endif
 740         return 0;
 741 }
 742 #endif
 743
 744 #if !CONFIG_IS_ENABLED(DM_USB_GADGET)
 745 #ifdef CONFIG_USB_DWC3
 746 static struct dwc3_device usb_otg_ss1 = {
 747         .maximum_speed = USB_SPEED_HIGH,
 748         .base = USB_OTG_SS1_BASE,
 749         .tx_fifo_resize = false,
 750         .index = 0,
 751 };
 752
 753 static struct dwc3_omap_device usb_otg_ss1_glue = {
 754         .base = (void *)USB_OTG_SS1_GLUE_BASE,
 755         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 756         .index = 0,
 757 };
 758
 759 static struct ti_usb_phy_device usb_phy1_device = {
 760         .usb2_phy_power = (void *)USB2_PHY1_POWER,
 761         .index = 0,
 762 };
 763
 764 static struct dwc3_device usb_otg_ss2 = {
 765         .maximum_speed = USB_SPEED_HIGH,
 766         .base = USB_OTG_SS2_BASE,
 767         .tx_fifo_resize = false,
 768         .index = 1,
 769 };
 770
 771 static struct dwc3_omap_device usb_otg_ss2_glue = {
 772         .base = (void *)USB_OTG_SS2_GLUE_BASE,
 773         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 774         .index = 1,
 775 };
 776
 777 static struct ti_usb_phy_device usb_phy2_device = {
 778         .usb2_phy_power = (void *)USB2_PHY2_POWER,
 779         .index = 1,
 780 };
 781
 782 int usb_gadget_handle_interrupts(int index)
 783 {
 784         u32 status;
 785
 786         status = dwc3_omap_uboot_interrupt_status(index);
 787         if (status)
 788                 dwc3_uboot_handle_interrupt(index);
 789
 790         return 0;
 791 }
 792 #endif /* CONFIG_USB_DWC3 */
 793
 794 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 795 int board_usb_init(int index, enum usb_init_type init)
 796 {
 797         enable_usb_clocks(index);
 798 #ifdef CONFIG_USB_DWC3
 799         switch (index) {
 800         case 0:
 801                 if (init == USB_INIT_DEVICE) {
 802                         usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
 803                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 804                         dwc3_omap_uboot_init(&usb_otg_ss1_glue);
 805                         ti_usb_phy_uboot_init(&usb_phy1_device);
 806                         dwc3_uboot_init(&usb_otg_ss1);
 807                 }
 808                 break;
 809         case 1:
 810                 if (init == USB_INIT_DEVICE) {
 811                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 812                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 813                         ti_usb_phy_uboot_init(&usb_phy2_device);
 814                         dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 815                         dwc3_uboot_init(&usb_otg_ss2);
 816                 }
 817                 break;
 818         default:
 819                 printf("Invalid Controller Index\n");
 820         }
 821 #endif
 822
 823         return 0;
 824 }
 825
 826 int board_usb_cleanup(int index, enum usb_init_type init)
 827 {
 828 #ifdef CONFIG_USB_DWC3
 829         switch (index) {
 830         case 0:
 831         case 1:
 832                 if (init == USB_INIT_DEVICE) {
 833                         ti_usb_phy_uboot_exit(index);
 834                         dwc3_uboot_exit(index);
 835                         dwc3_omap_uboot_exit(index);
 836                 }
 837                 break;
 838         default:
 839                 printf("Invalid Controller Index\n");
 840         }
 841 #endif
 842         disable_usb_clocks(index);
 843
 844         return 0;
 845 }
 846 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
 847 #endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
 848
 849 #ifdef CONFIG_DRIVER_TI_CPSW
 850
 851 static void cpsw_control(int enabled)
 852 {
 853         /* Additional controls can be added here */
 854         return;
 855 }
 856
 857 static struct cpsw_slave_data cpsw_slaves[] = {
 858         {
 859                 .slave_reg_ofs  = 0x208,
 860                 .sliver_reg_ofs = 0xd80,
 861                 .phy_addr       = 16,
 862         },
 863         {
 864                 .slave_reg_ofs  = 0x308,
 865                 .sliver_reg_ofs = 0xdc0,
 866                 .phy_addr       = 1,
 867         },
 868 };
 869
 870 static struct cpsw_platform_data cpsw_data = {
 871         .mdio_base              = CPSW_MDIO_BASE,
 872         .cpsw_base              = CPSW_BASE,
 873         .mdio_div               = 0xff,
 874         .channels               = 8,
 875         .cpdma_reg_ofs          = 0x800,
 876         .slaves                 = 1,
 877         .slave_data             = cpsw_slaves,
 878         .ale_reg_ofs            = 0xd00,
 879         .ale_entries            = 1024,
 880         .host_port_reg_ofs      = 0x108,
 881         .hw_stats_reg_ofs       = 0x900,
 882         .bd_ram_ofs             = 0x2000,
 883         .mac_control            = (1 << 5),
 884         .control                = cpsw_control,
 885         .host_port_num          = 0,
 886         .version                = CPSW_CTRL_VERSION_2,
 887 };
 888
 889 int board_eth_init(bd_t *bis)
 890 {
 891         int rv;
 892         uint8_t mac_addr[6];
 893         uint32_t mac_hi, mac_lo;
 894
 895         /* try reading mac address from efuse */
 896         mac_lo = readl(&cdev->macid0l);
 897         mac_hi = readl(&cdev->macid0h);
 898         mac_addr[0] = mac_hi & 0xFF;
 899         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 900         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 901         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 902         mac_addr[4] = mac_lo & 0xFF;
 903         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 904
 905         if (!env_get("ethaddr")) {
 906                 puts("<ethaddr> not set. Validating first E-fuse MAC\n");
 907                 if (is_valid_ethaddr(mac_addr))
 908                         eth_env_set_enetaddr("ethaddr", mac_addr);
 909         }
 910
 911         mac_lo = readl(&cdev->macid1l);
 912         mac_hi = readl(&cdev->macid1h);
 913         mac_addr[0] = mac_hi & 0xFF;
 914         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 915         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 916         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 917         mac_addr[4] = mac_lo & 0xFF;
 918         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 919
 920         if (!env_get("eth1addr")) {
 921                 if (is_valid_ethaddr(mac_addr))
 922                         eth_env_set_enetaddr("eth1addr", mac_addr);
 923         }
 924
 925         if (board_is_eposevm()) {
 926                 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
 927                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
 928                 cpsw_slaves[0].phy_addr = 16;
 929         } else if (board_is_sk()) {
 930                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 931                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
 932                 cpsw_slaves[0].phy_addr = 4;
 933                 cpsw_slaves[1].phy_addr = 5;
 934         } else if (board_is_idk()) {
 935                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 936                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
 937                 cpsw_slaves[0].phy_addr = 0;
 938         } else {
 939                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 940                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
 941                 cpsw_slaves[0].phy_addr = 0;
 942         }
 943
 944         rv = cpsw_register(&cpsw_data);
 945         if (rv < 0)
 946                 printf("Error %d registering CPSW switch\n", rv);
 947
 948         return rv;
 949 }
 950 #endif
 951
 952 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 953 int ft_board_setup(void *blob, bd_t *bd)
 954 {
 955         ft_cpu_setup(blob, bd);
 956
 957         return 0;
 958 }
 959 #endif
 960
 961 #if defined(CONFIG_SPL_LOAD_FIT) || defined(CONFIG_DTB_RESELECT)
 962 int board_fit_config_name_match(const char *name)
 963 {
 964         bool eeprom_read = board_ti_was_eeprom_read();
 965
 966         if (!strcmp(name, "am4372-generic") && !eeprom_read)
 967                 return 0;
 968         else if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
 969                 return 0;
 970         else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
 971                 return 0;
 972         else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
 973                 return 0;
 974         else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
 975                 return 0;
 976         else
 977                 return -1;
 978 }
 979 #endif
 980
 981 #ifdef CONFIG_DTB_RESELECT
 982 int embedded_dtb_select(void)
 983 {
 984         do_board_detect();
 985         fdtdec_setup();
 986
 987         return 0;
 988 }
 989 #endif
 990
 991 #ifdef CONFIG_TI_SECURE_DEVICE
 992 void board_fit_image_post_process(void **p_image, size_t *p_size)
 993 {
 994         secure_boot_verify_image(p_image, p_size);
 995 }
 996
 997 void board_tee_image_process(ulong tee_image, size_t tee_size)
 998 {
 999         secure_tee_install((u32)tee_image);
1000 }
1001
1002 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
1003 #endif