board/ti/am43xx/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Board functions for TI AM43XX based boards
   6  *
   7  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
   8  */
   9
  10 #include <common.h>
  11 #include <env.h>
  12 #include <environment.h>
  13 #include <i2c.h>
  14 #include <linux/errno.h>
  15 #include <spl.h>
  16 #include <usb.h>
  17 #include <asm/omap_sec_common.h>
  18 #include <asm/arch/clock.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/arch/mux.h>
  21 #include <asm/arch/ddr_defs.h>
  22 #include <asm/arch/gpio.h>
  23 #include <asm/emif.h>
  24 #include <asm/omap_common.h>
  25 #include "../common/board_detect.h"
  26 #include "board.h"
  27 #include <power/pmic.h>
  28 #include <power/tps65218.h>
  29 #include <power/tps62362.h>
  30 #include <miiphy.h>
  31 #include <cpsw.h>
  32 #include <linux/usb/gadget.h>
  33 #include <dwc3-uboot.h>
  34 #include <dwc3-omap-uboot.h>
  35 #include <ti-usb-phy-uboot.h>
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  40
  41 /*
  42  * Read header information from EEPROM into global structure.
  43  */
  44 #ifdef CONFIG_TI_I2C_BOARD_DETECT
  45 void do_board_detect(void)
  46 {
  47         /* Ensure I2C is initialized for EEPROM access*/
  48         gpi2c_init();
  49         if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  50                                  CONFIG_EEPROM_CHIP_ADDRESS))
  51                 printf("ti_i2c_eeprom_init failed\n");
  52 }
  53 #endif
  54
  55 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  56
  57 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
  58         {       /* 19.2 MHz */
  59                 {125, 3, 2, -1, -1, -1, -1},    /* OPP 50 */
  60                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  61                 {125, 3, 1, -1, -1, -1, -1},    /* OPP 100 */
  62                 {150, 3, 1, -1, -1, -1, -1},    /* OPP 120 */
  63                 {125, 2, 1, -1, -1, -1, -1},    /* OPP TB */
  64                 {625, 11, 1, -1, -1, -1, -1}    /* OPP NT */
  65         },
  66         {       /* 24 MHz */
  67                 {300, 23, 1, -1, -1, -1, -1},   /* OPP 50 */
  68                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  69                 {600, 23, 1, -1, -1, -1, -1},   /* OPP 100 */
  70                 {720, 23, 1, -1, -1, -1, -1},   /* OPP 120 */
  71                 {800, 23, 1, -1, -1, -1, -1},   /* OPP TB */
  72                 {1000, 23, 1, -1, -1, -1, -1}   /* OPP NT */
  73         },
  74         {       /* 25 MHz */
  75                 {300, 24, 1, -1, -1, -1, -1},   /* OPP 50 */
  76                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  77                 {600, 24, 1, -1, -1, -1, -1},   /* OPP 100 */
  78                 {720, 24, 1, -1, -1, -1, -1},   /* OPP 120 */
  79                 {800, 24, 1, -1, -1, -1, -1},   /* OPP TB */
  80                 {1000, 24, 1, -1, -1, -1, -1}   /* OPP NT */
  81         },
  82         {       /* 26 MHz */
  83                 {300, 25, 1, -1, -1, -1, -1},   /* OPP 50 */
  84                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  85                 {600, 25, 1, -1, -1, -1, -1},   /* OPP 100 */
  86                 {720, 25, 1, -1, -1, -1, -1},   /* OPP 120 */
  87                 {800, 25, 1, -1, -1, -1, -1},   /* OPP TB */
  88                 {1000, 25, 1, -1, -1, -1, -1}   /* OPP NT */
  89         },
  90 };
  91
  92 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
  93                 {625, 11, -1, -1, 10, 8, 4},    /* 19.2 MHz */
  94                 {1000, 23, -1, -1, 10, 8, 4},   /* 24 MHz */
  95                 {1000, 24, -1, -1, 10, 8, 4},   /* 25 MHz */
  96                 {1000, 25, -1, -1, 10, 8, 4}    /* 26 MHz */
  97 };
  98
  99 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
 100                 {400, 7, 5, -1, -1, -1, -1},    /* 19.2 MHz */
 101                 {400, 9, 5, -1, -1, -1, -1},    /* 24 MHz */
 102                 {384, 9, 5, -1, -1, -1, -1},    /* 25 MHz */
 103                 {480, 12, 5, -1, -1, -1, -1}    /* 26 MHz */
 104 };
 105
 106 const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
 107                 {665, 47, 1, -1, 4, -1, -1}, /*19.2*/
 108                 {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
 109                 {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
 110                 {133, 12, 1, -1, 4, -1, -1}  /* 26 MHz */
 111 };
 112
 113 const struct dpll_params gp_evm_dpll_ddr = {
 114                 50, 2, 1, -1, 2, -1, -1};
 115
 116 static const struct dpll_params idk_dpll_ddr = {
 117         400, 23, 1, -1, 2, -1, -1
 118 };
 119
 120 static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
 121         0x00500050,
 122         0x00350035,
 123         0x00350035,
 124         0x00350035,
 125         0x00350035,
 126         0x00350035,
 127         0x00000000,
 128         0x00000000,
 129         0x00000000,
 130         0x00000000,
 131         0x00000000,
 132         0x00000000,
 133         0x00000000,
 134         0x00000000,
 135         0x00000000,
 136         0x00000000,
 137         0x00000000,
 138         0x00000000,
 139         0x40001000,
 140         0x08102040
 141 };
 142
 143 const struct ctrl_ioregs ioregs_lpddr2 = {
 144         .cm0ioctl               = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
 145         .cm1ioctl               = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
 146         .cm2ioctl               = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
 147         .dt0ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 148         .dt1ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 149         .dt2ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 150         .dt3ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 151         .emif_sdram_config_ext  = 0x1,
 152 };
 153
 154 const struct emif_regs emif_regs_lpddr2 = {
 155         .sdram_config                   = 0x808012BA,
 156         .ref_ctrl                       = 0x0000040D,
 157         .sdram_tim1                     = 0xEA86B411,
 158         .sdram_tim2                     = 0x103A094A,
 159         .sdram_tim3                     = 0x0F6BA37F,
 160         .read_idle_ctrl                 = 0x00050000,
 161         .zq_config                      = 0x50074BE4,
 162         .temp_alert_config              = 0x0,
 163         .emif_rd_wr_lvl_rmp_win         = 0x0,
 164         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 165         .emif_rd_wr_lvl_ctl             = 0x0,
 166         .emif_ddr_phy_ctlr_1            = 0x0E284006,
 167         .emif_rd_wr_exec_thresh         = 0x80000405,
 168         .emif_ddr_ext_phy_ctrl_1        = 0x04010040,
 169         .emif_ddr_ext_phy_ctrl_2        = 0x00500050,
 170         .emif_ddr_ext_phy_ctrl_3        = 0x00500050,
 171         .emif_ddr_ext_phy_ctrl_4        = 0x00500050,
 172         .emif_ddr_ext_phy_ctrl_5        = 0x00500050,
 173         .emif_prio_class_serv_map       = 0x80000001,
 174         .emif_connect_id_serv_1_map     = 0x80000094,
 175         .emif_connect_id_serv_2_map     = 0x00000000,
 176         .emif_cos_config                        = 0x000FFFFF
 177 };
 178
 179 const struct ctrl_ioregs ioregs_ddr3 = {
 180         .cm0ioctl               = DDR3_ADDRCTRL_IOCTRL_VALUE,
 181         .cm1ioctl               = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
 182         .cm2ioctl               = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
 183         .dt0ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 184         .dt1ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 185         .dt2ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 186         .dt3ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 187         .emif_sdram_config_ext  = 0xc163,
 188 };
 189
 190 const struct emif_regs ddr3_emif_regs_400Mhz = {
 191         .sdram_config                   = 0x638413B2,
 192         .ref_ctrl                       = 0x00000C30,
 193         .sdram_tim1                     = 0xEAAAD4DB,
 194         .sdram_tim2                     = 0x266B7FDA,
 195         .sdram_tim3                     = 0x107F8678,
 196         .read_idle_ctrl                 = 0x00050000,
 197         .zq_config                      = 0x50074BE4,
 198         .temp_alert_config              = 0x0,
 199         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 200         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 201         .emif_ddr_ext_phy_ctrl_2        = 0x00400040,
 202         .emif_ddr_ext_phy_ctrl_3        = 0x00400040,
 203         .emif_ddr_ext_phy_ctrl_4        = 0x00400040,
 204         .emif_ddr_ext_phy_ctrl_5        = 0x00400040,
 205         .emif_rd_wr_lvl_rmp_win         = 0x0,
 206         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 207         .emif_rd_wr_lvl_ctl             = 0x0,
 208         .emif_rd_wr_exec_thresh         = 0x80000405,
 209         .emif_prio_class_serv_map       = 0x80000001,
 210         .emif_connect_id_serv_1_map     = 0x80000094,
 211         .emif_connect_id_serv_2_map     = 0x00000000,
 212         .emif_cos_config                = 0x000FFFFF
 213 };
 214
 215 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
 216 const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
 217         .sdram_config                   = 0x638413B2,
 218         .ref_ctrl                       = 0x00000C30,
 219         .sdram_tim1                     = 0xEAAAD4DB,
 220         .sdram_tim2                     = 0x266B7FDA,
 221         .sdram_tim3                     = 0x107F8678,
 222         .read_idle_ctrl                 = 0x00050000,
 223         .zq_config                      = 0x50074BE4,
 224         .temp_alert_config              = 0x0,
 225         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 226         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 227         .emif_ddr_ext_phy_ctrl_2        = 0x00000065,
 228         .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
 229         .emif_ddr_ext_phy_ctrl_4        = 0x000000B5,
 230         .emif_ddr_ext_phy_ctrl_5        = 0x000000E5,
 231         .emif_rd_wr_exec_thresh         = 0x80000405,
 232         .emif_prio_class_serv_map       = 0x80000001,
 233         .emif_connect_id_serv_1_map     = 0x80000094,
 234         .emif_connect_id_serv_2_map     = 0x00000000,
 235         .emif_cos_config                = 0x000FFFFF
 236 };
 237
 238 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
 239 const struct emif_regs ddr3_emif_regs_400Mhz_production = {
 240         .sdram_config                   = 0x638413B2,
 241         .ref_ctrl                       = 0x00000C30,
 242         .sdram_tim1                     = 0xEAAAD4DB,
 243         .sdram_tim2                     = 0x266B7FDA,
 244         .sdram_tim3                     = 0x107F8678,
 245         .read_idle_ctrl                 = 0x00050000,
 246         .zq_config                      = 0x50074BE4,
 247         .temp_alert_config              = 0x0,
 248         .emif_ddr_phy_ctlr_1            = 0x00048008,
 249         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 250         .emif_ddr_ext_phy_ctrl_2        = 0x00000066,
 251         .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
 252         .emif_ddr_ext_phy_ctrl_4        = 0x000000B9,
 253         .emif_ddr_ext_phy_ctrl_5        = 0x000000E6,
 254         .emif_rd_wr_exec_thresh         = 0x80000405,
 255         .emif_prio_class_serv_map       = 0x80000001,
 256         .emif_connect_id_serv_1_map     = 0x80000094,
 257         .emif_connect_id_serv_2_map     = 0x00000000,
 258         .emif_cos_config                = 0x000FFFFF
 259 };
 260
 261 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
 262         .sdram_config                   = 0x638413b2,
 263         .sdram_config2                  = 0x00000000,
 264         .ref_ctrl                       = 0x00000c30,
 265         .sdram_tim1                     = 0xeaaad4db,
 266         .sdram_tim2                     = 0x266b7fda,
 267         .sdram_tim3                     = 0x107f8678,
 268         .read_idle_ctrl                 = 0x00050000,
 269         .zq_config                      = 0x50074be4,
 270         .temp_alert_config              = 0x0,
 271         .emif_ddr_phy_ctlr_1            = 0x0e084008,
 272         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 273         .emif_ddr_ext_phy_ctrl_2        = 0x89,
 274         .emif_ddr_ext_phy_ctrl_3        = 0x90,
 275         .emif_ddr_ext_phy_ctrl_4        = 0x8e,
 276         .emif_ddr_ext_phy_ctrl_5        = 0x8d,
 277         .emif_rd_wr_lvl_rmp_win         = 0x0,
 278         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 279         .emif_rd_wr_lvl_ctl             = 0x00000000,
 280         .emif_rd_wr_exec_thresh         = 0x80000000,
 281         .emif_prio_class_serv_map       = 0x80000001,
 282         .emif_connect_id_serv_1_map     = 0x80000094,
 283         .emif_connect_id_serv_2_map     = 0x00000000,
 284         .emif_cos_config                = 0x000FFFFF
 285 };
 286
 287 static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
 288         .sdram_config                   = 0x61a11b32,
 289         .sdram_config2                  = 0x00000000,
 290         .ref_ctrl                       = 0x00000c30,
 291         .sdram_tim1                     = 0xeaaad4db,
 292         .sdram_tim2                     = 0x266b7fda,
 293         .sdram_tim3                     = 0x107f8678,
 294         .read_idle_ctrl                 = 0x00050000,
 295         .zq_config                      = 0x50074be4,
 296         .temp_alert_config              = 0x00000000,
 297         .emif_ddr_phy_ctlr_1            = 0x00008009,
 298         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 299         .emif_ddr_ext_phy_ctrl_2        = 0x00000040,
 300         .emif_ddr_ext_phy_ctrl_3        = 0x0000003e,
 301         .emif_ddr_ext_phy_ctrl_4        = 0x00000051,
 302         .emif_ddr_ext_phy_ctrl_5        = 0x00000051,
 303         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 304         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 305         .emif_rd_wr_lvl_ctl             = 0x00000000,
 306         .emif_rd_wr_exec_thresh         = 0x00000405,
 307         .emif_prio_class_serv_map       = 0x00000000,
 308         .emif_connect_id_serv_1_map     = 0x00000000,
 309         .emif_connect_id_serv_2_map     = 0x00000000,
 310         .emif_cos_config                = 0x00ffffff
 311 };
 312
 313 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
 314 {
 315         if (board_is_eposevm()) {
 316                 *regs = ext_phy_ctrl_const_base_lpddr2;
 317                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
 318         }
 319
 320         return;
 321 }
 322
 323 const struct dpll_params *get_dpll_ddr_params(void)
 324 {
 325         int ind = get_sys_clk_index();
 326
 327         if (board_is_eposevm())
 328                 return &epos_evm_dpll_ddr[ind];
 329         else if (board_is_evm() || board_is_sk())
 330                 return &gp_evm_dpll_ddr;
 331         else if (board_is_idk())
 332                 return &idk_dpll_ddr;
 333
 334         printf(" Board '%s' not supported\n", board_ti_get_name());
 335         return NULL;
 336 }
 337
 338
 339 /*
 340  * get_opp_offset:
 341  * Returns the index for safest OPP of the device to boot.
 342  * max_off:     Index of the MAX OPP in DEV ATTRIBUTE register.
 343  * min_off:     Index of the MIN OPP in DEV ATTRIBUTE register.
 344  * This data is read from dev_attribute register which is e-fused.
 345  * A'1' in bit indicates OPP disabled and not available, a '0' indicates
 346  * OPP available. Lowest OPP starts with min_off. So returning the
 347  * bit with rightmost '0'.
 348  */
 349 static int get_opp_offset(int max_off, int min_off)
 350 {
 351         struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
 352         int opp, offset, i;
 353
 354         /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
 355         opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
 356
 357         for (i = max_off; i >= min_off; i--) {
 358                 offset = opp & (1 << i);
 359                 if (!offset)
 360                         return i;
 361         }
 362
 363         return min_off;
 364 }
 365
 366 const struct dpll_params *get_dpll_mpu_params(void)
 367 {
 368         int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
 369         u32 ind = get_sys_clk_index();
 370
 371         return &dpll_mpu[ind][opp];
 372 }
 373
 374 const struct dpll_params *get_dpll_core_params(void)
 375 {
 376         int ind = get_sys_clk_index();
 377
 378         return &dpll_core[ind];
 379 }
 380
 381 const struct dpll_params *get_dpll_per_params(void)
 382 {
 383         int ind = get_sys_clk_index();
 384
 385         return &dpll_per[ind];
 386 }
 387
 388 void scale_vcores_generic(u32 m)
 389 {
 390         int mpu_vdd, ddr_volt;
 391
 392 #ifndef CONFIG_DM_I2C
 393         if (i2c_probe(TPS65218_CHIP_PM))
 394                 return;
 395 #else
 396         if (power_tps65218_init(0))
 397                 return;
 398 #endif
 399
 400         switch (m) {
 401         case 1000:
 402                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
 403                 break;
 404         case 800:
 405                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
 406                 break;
 407         case 720:
 408                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
 409                 break;
 410         case 600:
 411                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
 412                 break;
 413         case 300:
 414                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
 415                 break;
 416         default:
 417                 puts("Unknown MPU clock, not scaling\n");
 418                 return;
 419         }
 420
 421         /* Set DCDC1 (CORE) voltage to 1.1V */
 422         if (tps65218_voltage_update(TPS65218_DCDC1,
 423                                     TPS65218_DCDC_VOLT_SEL_1100MV)) {
 424                 printf("%s failure\n", __func__);
 425                 return;
 426         }
 427
 428         /* Set DCDC2 (MPU) voltage */
 429         if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
 430                 printf("%s failure\n", __func__);
 431                 return;
 432         }
 433
 434         if (board_is_eposevm())
 435                 ddr_volt = TPS65218_DCDC3_VOLT_SEL_1200MV;
 436         else
 437                 ddr_volt = TPS65218_DCDC3_VOLT_SEL_1350MV;
 438
 439         /* Set DCDC3 (DDR) voltage */
 440         if (tps65218_voltage_update(TPS65218_DCDC3, ddr_volt)) {
 441                 printf("%s failure\n", __func__);
 442                 return;
 443         }
 444 }
 445
 446 void scale_vcores_idk(u32 m)
 447 {
 448         int mpu_vdd;
 449
 450 #ifndef CONFIG_DM_I2C
 451         if (i2c_probe(TPS62362_I2C_ADDR))
 452                 return;
 453 #else
 454         if (power_tps62362_init(0))
 455                 return;
 456 #endif
 457
 458         switch (m) {
 459         case 1000:
 460                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
 461                 break;
 462         case 800:
 463                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
 464                 break;
 465         case 720:
 466                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
 467                 break;
 468         case 600:
 469                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
 470                 break;
 471         case 300:
 472                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
 473                 break;
 474         default:
 475                 puts("Unknown MPU clock, not scaling\n");
 476                 return;
 477         }
 478         /* Set VDD_MPU voltage */
 479         if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
 480                 printf("%s failure\n", __func__);
 481                 return;
 482         }
 483 }
 484 void gpi2c_init(void)
 485 {
 486         /* When needed to be invoked prior to BSS initialization */
 487         static bool first_time = true;
 488
 489         if (first_time) {
 490                 enable_i2c0_pin_mux();
 491 #ifndef CONFIG_DM_I2C
 492                 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
 493                          CONFIG_SYS_OMAP24_I2C_SLAVE);
 494 #endif
 495                 first_time = false;
 496         }
 497 }
 498
 499 void scale_vcores(void)
 500 {
 501         const struct dpll_params *mpu_params;
 502
 503         /* Ensure I2C is initialized for PMIC configuration */
 504         gpi2c_init();
 505
 506         /* Get the frequency */
 507         mpu_params = get_dpll_mpu_params();
 508
 509         if (board_is_idk())
 510                 scale_vcores_idk(mpu_params->m);
 511         else
 512                 scale_vcores_generic(mpu_params->m);
 513 }
 514
 515 void set_uart_mux_conf(void)
 516 {
 517         enable_uart0_pin_mux();
 518 }
 519
 520 void set_mux_conf_regs(void)
 521 {
 522         enable_board_pin_mux();
 523 }
 524
 525 static void enable_vtt_regulator(void)
 526 {
 527         u32 temp;
 528
 529         /* enable module */
 530         writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
 531
 532         /* enable output for GPIO5_7 */
 533         writel(GPIO_SETDATAOUT(7),
 534                AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
 535         temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 536         temp = temp & ~(GPIO_OE_ENABLE(7));
 537         writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 538 }
 539
 540 enum {
 541         RTC_BOARD_EPOS = 1,
 542         RTC_BOARD_EVM14,
 543         RTC_BOARD_EVM12,
 544         RTC_BOARD_GPEVM,
 545         RTC_BOARD_SK,
 546 };
 547
 548 /*
 549  * In the rtc_only+DRR in self-refresh boot path we have the board type info
 550  * in the rtc scratch pad register hence we bypass the costly i2c reads to
 551  * eeprom and directly programthe board name string
 552  */
 553 void rtc_only_update_board_type(u32 btype)
 554 {
 555         const char *name = "";
 556         const char *rev = "1.0";
 557
 558         switch (btype) {
 559         case RTC_BOARD_EPOS:
 560                 name = "AM43EPOS";
 561                 break;
 562         case RTC_BOARD_EVM14:
 563                 name = "AM43__GP";
 564                 rev = "1.4";
 565                 break;
 566         case RTC_BOARD_EVM12:
 567                 name = "AM43__GP";
 568                 rev = "1.2";
 569                 break;
 570         case RTC_BOARD_GPEVM:
 571                 name = "AM43__GP";
 572                 break;
 573         case RTC_BOARD_SK:
 574                 name = "AM43__SK";
 575                 break;
 576         }
 577         ti_i2c_eeprom_am_set(name, rev);
 578 }
 579
 580 u32 rtc_only_get_board_type(void)
 581 {
 582         if (board_is_eposevm())
 583                 return RTC_BOARD_EPOS;
 584         else if (board_is_evm_14_or_later())
 585                 return RTC_BOARD_EVM14;
 586         else if (board_is_evm_12_or_later())
 587                 return RTC_BOARD_EVM12;
 588         else if (board_is_gpevm())
 589                 return RTC_BOARD_GPEVM;
 590         else if (board_is_sk())
 591                 return RTC_BOARD_SK;
 592
 593         return 0;
 594 }
 595
 596 void sdram_init(void)
 597 {
 598         /*
 599          * EPOS EVM has 1GB LPDDR2 connected to EMIF.
 600          * GP EMV has 1GB DDR3 connected to EMIF
 601          * along with VTT regulator.
 602          */
 603         if (board_is_eposevm()) {
 604                 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
 605         } else if (board_is_evm_14_or_later()) {
 606                 enable_vtt_regulator();
 607                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 608                            &ddr3_emif_regs_400Mhz_production, 0);
 609         } else if (board_is_evm_12_or_later()) {
 610                 enable_vtt_regulator();
 611                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 612                            &ddr3_emif_regs_400Mhz_beta, 0);
 613         } else if (board_is_evm()) {
 614                 enable_vtt_regulator();
 615                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 616                            &ddr3_emif_regs_400Mhz, 0);
 617         } else if (board_is_sk()) {
 618                 config_ddr(400, &ioregs_ddr3, NULL, NULL,
 619                            &ddr3_sk_emif_regs_400Mhz, 0);
 620         } else if (board_is_idk()) {
 621                 config_ddr(400, &ioregs_ddr3, NULL, NULL,
 622                            &ddr3_idk_emif_regs_400Mhz, 0);
 623         }
 624 }
 625 #endif
 626
 627 /* setup board specific PMIC */
 628 int power_init_board(void)
 629 {
 630         int rc;
 631 #ifndef CONFIG_DM_I2C
 632         struct pmic *p = NULL;
 633 #endif
 634         if (board_is_idk()) {
 635                 rc = power_tps62362_init(0);
 636                 if (rc)
 637                         goto done;
 638 #ifndef CONFIG_DM_I2C
 639                 p = pmic_get("TPS62362");
 640                 if (!p || pmic_probe(p))
 641                         goto done;
 642 #endif
 643                 puts("PMIC:  TPS62362\n");
 644         } else {
 645                 rc = power_tps65218_init(0);
 646                 if (rc)
 647                         goto done;
 648 #ifndef CONFIG_DM_I2C
 649                 p = pmic_get("TPS65218_PMIC");
 650                 if (!p || pmic_probe(p))
 651                         goto done;
 652 #endif
 653                 puts("PMIC:  TPS65218\n");
 654         }
 655 done:
 656         return 0;
 657 }
 658
 659 int board_init(void)
 660 {
 661         struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
 662         u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
 663             modena_init0_bw_integer, modena_init0_watermark_0;
 664
 665         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 666         gpmc_init();
 667
 668         /*
 669          * Call this to initialize *ctrl again
 670          */
 671         hw_data_init();
 672
 673         /* Clear all important bits for DSS errata that may need to be tweaked*/
 674         mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
 675                            MREQPRIO_0_SAB_INIT0_MASK;
 676
 677         mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
 678
 679         modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
 680                                            BW_LIMITER_BW_FRAC_MASK;
 681
 682         modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
 683                                         BW_LIMITER_BW_INT_MASK;
 684
 685         modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
 686                                          BW_LIMITER_BW_WATERMARK_MASK;
 687
 688         /* Setting MReq Priority of the DSS*/
 689         mreqprio_0 |= 0x77;
 690
 691         /*
 692          * Set L3 Fast Configuration Register
 693          * Limiting bandwith for ARM core to 700 MBPS
 694          */
 695         modena_init0_bw_fractional |= 0x10;
 696         modena_init0_bw_integer |= 0x3;
 697
 698         writel(mreqprio_0, &cdev->mreqprio_0);
 699         writel(mreqprio_1, &cdev->mreqprio_1);
 700
 701         writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
 702         writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
 703         writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
 704
 705         return 0;
 706 }
 707
 708 #ifdef CONFIG_BOARD_LATE_INIT
 709 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 710 static int device_okay(const char *path)
 711 {
 712         int node;
 713
 714         node = fdt_path_offset(gd->fdt_blob, path);
 715         if (node < 0)
 716                 return 0;
 717
 718         return fdtdec_get_is_enabled(gd->fdt_blob, node);
 719 }
 720 #endif
 721
 722 int board_late_init(void)
 723 {
 724 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 725         set_board_info_env(NULL);
 726
 727         /*
 728          * Default FIT boot on HS devices. Non FIT images are not allowed
 729          * on HS devices.
 730          */
 731         if (get_device_type() == HS_DEVICE)
 732                 env_set("boot_fit", "1");
 733 #endif
 734
 735 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 736         if (device_okay("/ocp/omap_dwc3@48380000"))
 737                 enable_usb_clocks(0);
 738         if (device_okay("/ocp/omap_dwc3@483c0000"))
 739                 enable_usb_clocks(1);
 740 #endif
 741         return 0;
 742 }
 743 #endif
 744
 745 #if !CONFIG_IS_ENABLED(DM_USB_GADGET)
 746 #ifdef CONFIG_USB_DWC3
 747 static struct dwc3_device usb_otg_ss1 = {
 748         .maximum_speed = USB_SPEED_HIGH,
 749         .base = USB_OTG_SS1_BASE,
 750         .tx_fifo_resize = false,
 751         .index = 0,
 752 };
 753
 754 static struct dwc3_omap_device usb_otg_ss1_glue = {
 755         .base = (void *)USB_OTG_SS1_GLUE_BASE,
 756         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 757         .index = 0,
 758 };
 759
 760 static struct ti_usb_phy_device usb_phy1_device = {
 761         .usb2_phy_power = (void *)USB2_PHY1_POWER,
 762         .index = 0,
 763 };
 764
 765 static struct dwc3_device usb_otg_ss2 = {
 766         .maximum_speed = USB_SPEED_HIGH,
 767         .base = USB_OTG_SS2_BASE,
 768         .tx_fifo_resize = false,
 769         .index = 1,
 770 };
 771
 772 static struct dwc3_omap_device usb_otg_ss2_glue = {
 773         .base = (void *)USB_OTG_SS2_GLUE_BASE,
 774         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 775         .index = 1,
 776 };
 777
 778 static struct ti_usb_phy_device usb_phy2_device = {
 779         .usb2_phy_power = (void *)USB2_PHY2_POWER,
 780         .index = 1,
 781 };
 782
 783 int usb_gadget_handle_interrupts(int index)
 784 {
 785         u32 status;
 786
 787         status = dwc3_omap_uboot_interrupt_status(index);
 788         if (status)
 789                 dwc3_uboot_handle_interrupt(index);
 790
 791         return 0;
 792 }
 793 #endif /* CONFIG_USB_DWC3 */
 794
 795 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 796 int board_usb_init(int index, enum usb_init_type init)
 797 {
 798         enable_usb_clocks(index);
 799 #ifdef CONFIG_USB_DWC3
 800         switch (index) {
 801         case 0:
 802                 if (init == USB_INIT_DEVICE) {
 803                         usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
 804                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 805                         dwc3_omap_uboot_init(&usb_otg_ss1_glue);
 806                         ti_usb_phy_uboot_init(&usb_phy1_device);
 807                         dwc3_uboot_init(&usb_otg_ss1);
 808                 }
 809                 break;
 810         case 1:
 811                 if (init == USB_INIT_DEVICE) {
 812                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 813                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 814                         ti_usb_phy_uboot_init(&usb_phy2_device);
 815                         dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 816                         dwc3_uboot_init(&usb_otg_ss2);
 817                 }
 818                 break;
 819         default:
 820                 printf("Invalid Controller Index\n");
 821         }
 822 #endif
 823
 824         return 0;
 825 }
 826
 827 int board_usb_cleanup(int index, enum usb_init_type init)
 828 {
 829 #ifdef CONFIG_USB_DWC3
 830         switch (index) {
 831         case 0:
 832         case 1:
 833                 if (init == USB_INIT_DEVICE) {
 834                         ti_usb_phy_uboot_exit(index);
 835                         dwc3_uboot_exit(index);
 836                         dwc3_omap_uboot_exit(index);
 837                 }
 838                 break;
 839         default:
 840                 printf("Invalid Controller Index\n");
 841         }
 842 #endif
 843         disable_usb_clocks(index);
 844
 845         return 0;
 846 }
 847 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
 848 #endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
 849
 850 #ifdef CONFIG_DRIVER_TI_CPSW
 851
 852 static void cpsw_control(int enabled)
 853 {
 854         /* Additional controls can be added here */
 855         return;
 856 }
 857
 858 static struct cpsw_slave_data cpsw_slaves[] = {
 859         {
 860                 .slave_reg_ofs  = 0x208,
 861                 .sliver_reg_ofs = 0xd80,
 862                 .phy_addr       = 16,
 863         },
 864         {
 865                 .slave_reg_ofs  = 0x308,
 866                 .sliver_reg_ofs = 0xdc0,
 867                 .phy_addr       = 1,
 868         },
 869 };
 870
 871 static struct cpsw_platform_data cpsw_data = {
 872         .mdio_base              = CPSW_MDIO_BASE,
 873         .cpsw_base              = CPSW_BASE,
 874         .mdio_div               = 0xff,
 875         .channels               = 8,
 876         .cpdma_reg_ofs          = 0x800,
 877         .slaves                 = 1,
 878         .slave_data             = cpsw_slaves,
 879         .ale_reg_ofs            = 0xd00,
 880         .ale_entries            = 1024,
 881         .host_port_reg_ofs      = 0x108,
 882         .hw_stats_reg_ofs       = 0x900,
 883         .bd_ram_ofs             = 0x2000,
 884         .mac_control            = (1 << 5),
 885         .control                = cpsw_control,
 886         .host_port_num          = 0,
 887         .version                = CPSW_CTRL_VERSION_2,
 888 };
 889
 890 int board_eth_init(bd_t *bis)
 891 {
 892         int rv;
 893         uint8_t mac_addr[6];
 894         uint32_t mac_hi, mac_lo;
 895
 896         /* try reading mac address from efuse */
 897         mac_lo = readl(&cdev->macid0l);
 898         mac_hi = readl(&cdev->macid0h);
 899         mac_addr[0] = mac_hi & 0xFF;
 900         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 901         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 902         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 903         mac_addr[4] = mac_lo & 0xFF;
 904         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 905
 906         if (!env_get("ethaddr")) {
 907                 puts("<ethaddr> not set. Validating first E-fuse MAC\n");
 908                 if (is_valid_ethaddr(mac_addr))
 909                         eth_env_set_enetaddr("ethaddr", mac_addr);
 910         }
 911
 912         mac_lo = readl(&cdev->macid1l);
 913         mac_hi = readl(&cdev->macid1h);
 914         mac_addr[0] = mac_hi & 0xFF;
 915         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 916         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 917         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 918         mac_addr[4] = mac_lo & 0xFF;
 919         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 920
 921         if (!env_get("eth1addr")) {
 922                 if (is_valid_ethaddr(mac_addr))
 923                         eth_env_set_enetaddr("eth1addr", mac_addr);
 924         }
 925
 926         if (board_is_eposevm()) {
 927                 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
 928                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
 929                 cpsw_slaves[0].phy_addr = 16;
 930         } else if (board_is_sk()) {
 931                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 932                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
 933                 cpsw_slaves[0].phy_addr = 4;
 934                 cpsw_slaves[1].phy_addr = 5;
 935         } else if (board_is_idk()) {
 936                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 937                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
 938                 cpsw_slaves[0].phy_addr = 0;
 939         } else {
 940                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 941                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
 942                 cpsw_slaves[0].phy_addr = 0;
 943         }
 944
 945         rv = cpsw_register(&cpsw_data);
 946         if (rv < 0)
 947                 printf("Error %d registering CPSW switch\n", rv);
 948
 949         return rv;
 950 }
 951 #endif
 952
 953 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 954 int ft_board_setup(void *blob, bd_t *bd)
 955 {
 956         ft_cpu_setup(blob, bd);
 957
 958         return 0;
 959 }
 960 #endif
 961
 962 #if defined(CONFIG_SPL_LOAD_FIT) || defined(CONFIG_DTB_RESELECT)
 963 int board_fit_config_name_match(const char *name)
 964 {
 965         bool eeprom_read = board_ti_was_eeprom_read();
 966
 967         if (!strcmp(name, "am4372-generic") && !eeprom_read)
 968                 return 0;
 969         else if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
 970                 return 0;
 971         else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
 972                 return 0;
 973         else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
 974                 return 0;
 975         else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
 976                 return 0;
 977         else
 978                 return -1;
 979 }
 980 #endif
 981
 982 #ifdef CONFIG_DTB_RESELECT
 983 int embedded_dtb_select(void)
 984 {
 985         do_board_detect();
 986         fdtdec_setup();
 987
 988         return 0;
 989 }
 990 #endif
 991
 992 #ifdef CONFIG_TI_SECURE_DEVICE
 993 void board_fit_image_post_process(void **p_image, size_t *p_size)
 994 {
 995         secure_boot_verify_image(p_image, p_size);
 996 }
 997
 998 void board_tee_image_process(ulong tee_image, size_t tee_size)
 999 {
1000         secure_tee_install((u32)tee_image);
1001 }
1002
1003 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
1004 #endif