board/ti/am335x/board.c

   1 /*
   2  * board.c
   3  *
   4  * Board functions for TI AM335X based boards
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <dm.h>
  13 #include <errno.h>
  14 #include <spl.h>
  15 #include <serial.h>
  16 #include <asm/arch/cpu.h>
  17 #include <asm/arch/hardware.h>
  18 #include <asm/arch/omap.h>
  19 #include <asm/arch/ddr_defs.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/clk_synthesizer.h>
  22 #include <asm/arch/gpio.h>
  23 #include <asm/arch/mmc_host_def.h>
  24 #include <asm/arch/sys_proto.h>
  25 #include <asm/arch/mem.h>
  26 #include <asm/io.h>
  27 #include <asm/emif.h>
  28 #include <asm/gpio.h>
  29 #include <asm/omap_sec_common.h>
  30 #include <asm/omap_mmc.h>
  31 #include <i2c.h>
  32 #include <miiphy.h>
  33 #include <cpsw.h>
  34 #include <power/tps65217.h>
  35 #include <power/tps65910.h>
  36 #include <environment.h>
  37 #include <watchdog.h>
  38 #include <environment.h>
  39 #include "../common/board_detect.h"
  40 #include "board.h"
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44 /* GPIO that controls power to DDR on EVM-SK */
  45 #define GPIO_TO_PIN(bank, gpio)         (32 * (bank) + (gpio))
  46 #define GPIO_DDR_VTT_EN         GPIO_TO_PIN(0, 7)
  47 #define ICE_GPIO_DDR_VTT_EN     GPIO_TO_PIN(0, 18)
  48 #define GPIO_PR1_MII_CTRL       GPIO_TO_PIN(3, 4)
  49 #define GPIO_MUX_MII_CTRL       GPIO_TO_PIN(3, 10)
  50 #define GPIO_FET_SWITCH_CTRL    GPIO_TO_PIN(0, 7)
  51 #define GPIO_PHY_RESET          GPIO_TO_PIN(2, 5)
  52 #define GPIO_ETH0_MODE          GPIO_TO_PIN(0, 11)
  53 #define GPIO_ETH1_MODE          GPIO_TO_PIN(1, 26)
  54
  55 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  56
  57 #define GPIO0_RISINGDETECT      (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
  58 #define GPIO1_RISINGDETECT      (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
  59
  60 #define GPIO0_IRQSTATUS1        (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
  61 #define GPIO1_IRQSTATUS1        (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
  62
  63 #define GPIO0_IRQSTATUSRAW      (AM33XX_GPIO0_BASE + 0x024)
  64 #define GPIO1_IRQSTATUSRAW      (AM33XX_GPIO1_BASE + 0x024)
  65
  66 /*
  67  * Read header information from EEPROM into global structure.
  68  */
  69 #ifdef CONFIG_TI_I2C_BOARD_DETECT
  70 void do_board_detect(void)
  71 {
  72         enable_i2c0_pin_mux();
  73         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  74
  75         if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR))
  76                 printf("ti_i2c_eeprom_init failed\n");
  77 }
  78 #endif
  79
  80 #ifndef CONFIG_DM_SERIAL
  81 struct serial_device *default_serial_console(void)
  82 {
  83         if (board_is_icev2())
  84                 return &eserial4_device;
  85         else
  86                 return &eserial1_device;
  87 }
  88 #endif
  89
  90 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  91 static const struct ddr_data ddr2_data = {
  92         .datardsratio0 = MT47H128M16RT25E_RD_DQS,
  93         .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
  94         .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
  95 };
  96
  97 static const struct cmd_control ddr2_cmd_ctrl_data = {
  98         .cmd0csratio = MT47H128M16RT25E_RATIO,
  99
 100         .cmd1csratio = MT47H128M16RT25E_RATIO,
 101
 102         .cmd2csratio = MT47H128M16RT25E_RATIO,
 103 };
 104
 105 static const struct emif_regs ddr2_emif_reg_data = {
 106         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
 107         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
 108         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
 109         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
 110         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
 111         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
 112 };
 113
 114 static const struct emif_regs ddr2_evm_emif_reg_data = {
 115         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
 116         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
 117         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
 118         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
 119         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
 120         .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
 121         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
 122 };
 123
 124 static const struct ddr_data ddr3_data = {
 125         .datardsratio0 = MT41J128MJT125_RD_DQS,
 126         .datawdsratio0 = MT41J128MJT125_WR_DQS,
 127         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
 128         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
 129 };
 130
 131 static const struct ddr_data ddr3_beagleblack_data = {
 132         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
 133         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
 134         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
 135         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
 136 };
 137
 138 static const struct ddr_data ddr3_evm_data = {
 139         .datardsratio0 = MT41J512M8RH125_RD_DQS,
 140         .datawdsratio0 = MT41J512M8RH125_WR_DQS,
 141         .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
 142         .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
 143 };
 144
 145 static const struct ddr_data ddr3_icev2_data = {
 146         .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
 147         .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
 148         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
 149         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
 150 };
 151
 152 static const struct cmd_control ddr3_cmd_ctrl_data = {
 153         .cmd0csratio = MT41J128MJT125_RATIO,
 154         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
 155
 156         .cmd1csratio = MT41J128MJT125_RATIO,
 157         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
 158
 159         .cmd2csratio = MT41J128MJT125_RATIO,
 160         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
 161 };
 162
 163 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
 164         .cmd0csratio = MT41K256M16HA125E_RATIO,
 165         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 166
 167         .cmd1csratio = MT41K256M16HA125E_RATIO,
 168         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 169
 170         .cmd2csratio = MT41K256M16HA125E_RATIO,
 171         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 172 };
 173
 174 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
 175         .cmd0csratio = MT41J512M8RH125_RATIO,
 176         .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 177
 178         .cmd1csratio = MT41J512M8RH125_RATIO,
 179         .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 180
 181         .cmd2csratio = MT41J512M8RH125_RATIO,
 182         .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 183 };
 184
 185 static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
 186         .cmd0csratio = MT41J128MJT125_RATIO_400MHz,
 187         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 188
 189         .cmd1csratio = MT41J128MJT125_RATIO_400MHz,
 190         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 191
 192         .cmd2csratio = MT41J128MJT125_RATIO_400MHz,
 193         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 194 };
 195
 196 static struct emif_regs ddr3_emif_reg_data = {
 197         .sdram_config = MT41J128MJT125_EMIF_SDCFG,
 198         .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
 199         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
 200         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
 201         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
 202         .zq_config = MT41J128MJT125_ZQ_CFG,
 203         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
 204                                 PHY_EN_DYN_PWRDN,
 205 };
 206
 207 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
 208         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
 209         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
 210         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 211         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 212         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
 213         .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
 214         .zq_config = MT41K256M16HA125E_ZQ_CFG,
 215         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 216 };
 217
 218 static struct emif_regs ddr3_evm_emif_reg_data = {
 219         .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
 220         .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
 221         .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
 222         .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
 223         .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
 224         .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
 225         .zq_config = MT41J512M8RH125_ZQ_CFG,
 226         .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
 227                                 PHY_EN_DYN_PWRDN,
 228 };
 229
 230 static struct emif_regs ddr3_icev2_emif_reg_data = {
 231         .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
 232         .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
 233         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
 234         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
 235         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
 236         .zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
 237         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
 238                                 PHY_EN_DYN_PWRDN,
 239 };
 240
 241 #ifdef CONFIG_SPL_OS_BOOT
 242 int spl_start_uboot(void)
 243 {
 244         /* break into full u-boot on 'c' */
 245         if (serial_tstc() && serial_getc() == 'c')
 246                 return 1;
 247
 248 #ifdef CONFIG_SPL_ENV_SUPPORT
 249         env_init();
 250         env_relocate_spec();
 251         if (getenv_yesno("boot_os") != 1)
 252                 return 1;
 253 #endif
 254
 255         return 0;
 256 }
 257 #endif
 258
 259 const struct dpll_params *get_dpll_ddr_params(void)
 260 {
 261         int ind = get_sys_clk_index();
 262
 263         if (board_is_evm_sk())
 264                 return &dpll_ddr3_303MHz[ind];
 265         else if (board_is_bone_lt() || board_is_icev2())
 266                 return &dpll_ddr3_400MHz[ind];
 267         else if (board_is_evm_15_or_later())
 268                 return &dpll_ddr3_303MHz[ind];
 269         else
 270                 return &dpll_ddr2_266MHz[ind];
 271 }
 272
 273 static u8 bone_not_connected_to_ac_power(void)
 274 {
 275         if (board_is_bone()) {
 276                 uchar pmic_status_reg;
 277                 if (tps65217_reg_read(TPS65217_STATUS,
 278                                       &pmic_status_reg))
 279                         return 1;
 280                 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
 281                         puts("No AC power, switching to default OPP\n");
 282                         return 1;
 283                 }
 284         }
 285         return 0;
 286 }
 287
 288 const struct dpll_params *get_dpll_mpu_params(void)
 289 {
 290         int ind = get_sys_clk_index();
 291         int freq = am335x_get_efuse_mpu_max_freq(cdev);
 292
 293         if (bone_not_connected_to_ac_power())
 294                 freq = MPUPLL_M_600;
 295
 296         if (board_is_bone_lt())
 297                 freq = MPUPLL_M_1000;
 298
 299         switch (freq) {
 300         case MPUPLL_M_1000:
 301                 return &dpll_mpu_opp[ind][5];
 302         case MPUPLL_M_800:
 303                 return &dpll_mpu_opp[ind][4];
 304         case MPUPLL_M_720:
 305                 return &dpll_mpu_opp[ind][3];
 306         case MPUPLL_M_600:
 307                 return &dpll_mpu_opp[ind][2];
 308         case MPUPLL_M_500:
 309                 return &dpll_mpu_opp100;
 310         case MPUPLL_M_300:
 311                 return &dpll_mpu_opp[ind][0];
 312         }
 313
 314         return &dpll_mpu_opp[ind][0];
 315 }
 316
 317 static void scale_vcores_bone(int freq)
 318 {
 319         int usb_cur_lim, mpu_vdd;
 320
 321         /*
 322          * Only perform PMIC configurations if board rev > A1
 323          * on Beaglebone White
 324          */
 325         if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
 326                 return;
 327
 328         if (i2c_probe(TPS65217_CHIP_PM))
 329                 return;
 330
 331         /*
 332          * On Beaglebone White we need to ensure we have AC power
 333          * before increasing the frequency.
 334          */
 335         if (bone_not_connected_to_ac_power())
 336                 freq = MPUPLL_M_600;
 337
 338         /*
 339          * Override what we have detected since we know if we have
 340          * a Beaglebone Black it supports 1GHz.
 341          */
 342         if (board_is_bone_lt())
 343                 freq = MPUPLL_M_1000;
 344
 345         if (freq == MPUPLL_M_1000) {
 346                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
 347                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
 348         } else {
 349                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 350                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
 351         }
 352
 353         switch (freq) {
 354         case MPUPLL_M_1000:
 355                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
 356                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
 357                 break;
 358         case MPUPLL_M_800:
 359                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
 360                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
 361                 break;
 362         case MPUPLL_M_720:
 363                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
 364                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
 365                 break;
 366         case MPUPLL_M_600:
 367         case MPUPLL_M_500:
 368         case MPUPLL_M_300:
 369                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
 370                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 371                 break;
 372         }
 373
 374         if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
 375                                TPS65217_POWER_PATH,
 376                                usb_cur_lim,
 377                                TPS65217_USB_INPUT_CUR_LIMIT_MASK))
 378                 puts("tps65217_reg_write failure\n");
 379
 380         /* Set DCDC3 (CORE) voltage to 1.10V */
 381         if (tps65217_voltage_update(TPS65217_DEFDCDC3,
 382                                     TPS65217_DCDC_VOLT_SEL_1100MV)) {
 383                 puts("tps65217_voltage_update failure\n");
 384                 return;
 385         }
 386
 387         /* Set DCDC2 (MPU) voltage */
 388         if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
 389                 puts("tps65217_voltage_update failure\n");
 390                 return;
 391         }
 392
 393         /*
 394          * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
 395          * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
 396          */
 397         if (board_is_bone()) {
 398                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 399                                        TPS65217_DEFLS1,
 400                                        TPS65217_LDO_VOLTAGE_OUT_3_3,
 401                                        TPS65217_LDO_MASK))
 402                         puts("tps65217_reg_write failure\n");
 403         } else {
 404                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 405                                        TPS65217_DEFLS1,
 406                                        TPS65217_LDO_VOLTAGE_OUT_1_8,
 407                                        TPS65217_LDO_MASK))
 408                         puts("tps65217_reg_write failure\n");
 409         }
 410
 411         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 412                                TPS65217_DEFLS2,
 413                                TPS65217_LDO_VOLTAGE_OUT_3_3,
 414                                TPS65217_LDO_MASK))
 415                 puts("tps65217_reg_write failure\n");
 416 }
 417
 418 void scale_vcores_generic(int freq)
 419 {
 420         int sil_rev, mpu_vdd;
 421
 422         /*
 423          * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
 424          * MPU frequencies we support we use a CORE voltage of
 425          * 1.10V.  For MPU voltage we need to switch based on
 426          * the frequency we are running at.
 427          */
 428         if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
 429                 return;
 430
 431         /*
 432          * Depending on MPU clock and PG we will need a different
 433          * VDD to drive at that speed.
 434          */
 435         sil_rev = readl(&cdev->deviceid) >> 28;
 436         mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
 437
 438         /* Tell the TPS65910 to use i2c */
 439         tps65910_set_i2c_control();
 440
 441         /* First update MPU voltage. */
 442         if (tps65910_voltage_update(MPU, mpu_vdd))
 443                 return;
 444
 445         /* Second, update the CORE voltage. */
 446         if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
 447                 return;
 448
 449 }
 450
 451 void gpi2c_init(void)
 452 {
 453         /* When needed to be invoked prior to BSS initialization */
 454         static bool first_time = true;
 455
 456         if (first_time) {
 457                 enable_i2c0_pin_mux();
 458                 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
 459                          CONFIG_SYS_OMAP24_I2C_SLAVE);
 460                 first_time = false;
 461         }
 462 }
 463
 464 void scale_vcores(void)
 465 {
 466         int freq;
 467
 468         gpi2c_init();
 469         freq = am335x_get_efuse_mpu_max_freq(cdev);
 470
 471         if (board_is_bone())
 472                 scale_vcores_bone(freq);
 473         else
 474                 scale_vcores_generic(freq);
 475 }
 476
 477 void set_uart_mux_conf(void)
 478 {
 479 #if CONFIG_CONS_INDEX == 1
 480         enable_uart0_pin_mux();
 481 #elif CONFIG_CONS_INDEX == 2
 482         enable_uart1_pin_mux();
 483 #elif CONFIG_CONS_INDEX == 3
 484         enable_uart2_pin_mux();
 485 #elif CONFIG_CONS_INDEX == 4
 486         enable_uart3_pin_mux();
 487 #elif CONFIG_CONS_INDEX == 5
 488         enable_uart4_pin_mux();
 489 #elif CONFIG_CONS_INDEX == 6
 490         enable_uart5_pin_mux();
 491 #endif
 492 }
 493
 494 void set_mux_conf_regs(void)
 495 {
 496         enable_board_pin_mux();
 497 }
 498
 499 const struct ctrl_ioregs ioregs_evmsk = {
 500         .cm0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 501         .cm1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 502         .cm2ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 503         .dt0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 504         .dt1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 505 };
 506
 507 const struct ctrl_ioregs ioregs_bonelt = {
 508         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 509         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 510         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 511         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 512         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 513 };
 514
 515 const struct ctrl_ioregs ioregs_evm15 = {
 516         .cm0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 517         .cm1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 518         .cm2ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 519         .dt0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 520         .dt1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 521 };
 522
 523 const struct ctrl_ioregs ioregs = {
 524         .cm0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 525         .cm1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 526         .cm2ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 527         .dt0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 528         .dt1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 529 };
 530
 531 void sdram_init(void)
 532 {
 533         if (board_is_evm_sk()) {
 534                 /*
 535                  * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
 536                  * This is safe enough to do on older revs.
 537                  */
 538                 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 539                 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 540         }
 541
 542         if (board_is_icev2()) {
 543                 gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
 544                 gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
 545         }
 546
 547         if (board_is_evm_sk())
 548                 config_ddr(303, &ioregs_evmsk, &ddr3_data,
 549                            &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 550         else if (board_is_bone_lt())
 551                 config_ddr(400, &ioregs_bonelt,
 552                            &ddr3_beagleblack_data,
 553                            &ddr3_beagleblack_cmd_ctrl_data,
 554                            &ddr3_beagleblack_emif_reg_data, 0);
 555         else if (board_is_evm_15_or_later())
 556                 config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
 557                            &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
 558         else if (board_is_icev2())
 559                 config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
 560                            &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
 561                            0);
 562         else if (board_is_gp_evm())
 563                 config_ddr(266, &ioregs, &ddr2_data,
 564                            &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
 565         else
 566                 config_ddr(266, &ioregs, &ddr2_data,
 567                            &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
 568 }
 569 #endif
 570
 571 #if !defined(CONFIG_SPL_BUILD) || \
 572         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 573 static void request_and_set_gpio(int gpio, char *name, int val)
 574 {
 575         int ret;
 576
 577         ret = gpio_request(gpio, name);
 578         if (ret < 0) {
 579                 printf("%s: Unable to request %s\n", __func__, name);
 580                 return;
 581         }
 582
 583         ret = gpio_direction_output(gpio, 0);
 584         if (ret < 0) {
 585                 printf("%s: Unable to set %s  as output\n", __func__, name);
 586                 goto err_free_gpio;
 587         }
 588
 589         gpio_set_value(gpio, val);
 590
 591         return;
 592
 593 err_free_gpio:
 594         gpio_free(gpio);
 595 }
 596
 597 #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1);
 598 #define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0);
 599
 600 /**
 601  * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
 602  * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
 603  * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
 604  * give 50MHz output for Eth0 and 1.
 605  */
 606 static struct clk_synth cdce913_data = {
 607         .id = 0x81,
 608         .capacitor = 0x90,
 609         .mux = 0x6d,
 610         .pdiv2 = 0x2,
 611         .pdiv3 = 0x2,
 612 };
 613 #endif
 614
 615 /*
 616  * Basic board specific setup.  Pinmux has been handled already.
 617  */
 618 int board_init(void)
 619 {
 620 #if defined(CONFIG_HW_WATCHDOG)
 621         hw_watchdog_init();
 622 #endif
 623
 624         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 625 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
 626         gpmc_init();
 627 #endif
 628
 629 #if !defined(CONFIG_SPL_BUILD) || \
 630         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 631         if (board_is_icev2()) {
 632                 int rv;
 633                 u32 reg;
 634
 635                 REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
 636                 /* Make J19 status available on GPIO1_26 */
 637                 REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL);
 638
 639                 REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
 640                 /*
 641                  * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
 642                  * jumpers near the port. Read the jumper value and set
 643                  * the pinmux, external mux and PHY clock accordingly.
 644                  * As jumper line is overridden by PHY RX_DV pin immediately
 645                  * after bootstrap (power-up/reset), we need to sample
 646                  * it during PHY reset using GPIO rising edge detection.
 647                  */
 648                 REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
 649                 /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
 650                 reg = readl(GPIO0_RISINGDETECT) | BIT(11);
 651                 writel(reg, GPIO0_RISINGDETECT);
 652                 reg = readl(GPIO1_RISINGDETECT) | BIT(26);
 653                 writel(reg, GPIO1_RISINGDETECT);
 654                 /* Reset PHYs to capture the Jumper setting */
 655                 gpio_set_value(GPIO_PHY_RESET, 0);
 656                 udelay(2);      /* PHY datasheet states 1uS min. */
 657                 gpio_set_value(GPIO_PHY_RESET, 1);
 658
 659                 reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11);
 660                 if (reg) {
 661                         writel(reg, GPIO0_IRQSTATUS1); /* clear irq */
 662                         /* RMII mode */
 663                         printf("ETH0, CPSW\n");
 664                 } else {
 665                         /* MII mode */
 666                         printf("ETH0, PRU\n");
 667                         cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */
 668                 }
 669
 670                 reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26);
 671                 if (reg) {
 672                         writel(reg, GPIO1_IRQSTATUS1); /* clear irq */
 673                         /* RMII mode */
 674                         printf("ETH1, CPSW\n");
 675                         gpio_set_value(GPIO_MUX_MII_CTRL, 1);
 676                 } else {
 677                         /* MII mode */
 678                         printf("ETH1, PRU\n");
 679                         cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */
 680                 }
 681
 682                 /* disable rising edge IRQs */
 683                 reg = readl(GPIO0_RISINGDETECT) & ~BIT(11);
 684                 writel(reg, GPIO0_RISINGDETECT);
 685                 reg = readl(GPIO1_RISINGDETECT) & ~BIT(26);
 686                 writel(reg, GPIO1_RISINGDETECT);
 687
 688                 rv = setup_clock_synthesizer(&cdce913_data);
 689                 if (rv) {
 690                         printf("Clock synthesizer setup failed %d\n", rv);
 691                         return rv;
 692                 }
 693
 694                 /* reset PHYs */
 695                 gpio_set_value(GPIO_PHY_RESET, 0);
 696                 udelay(2);      /* PHY datasheet states 1uS min. */
 697                 gpio_set_value(GPIO_PHY_RESET, 1);
 698         }
 699 #endif
 700
 701         return 0;
 702 }
 703
 704 #ifdef CONFIG_BOARD_LATE_INIT
 705 int board_late_init(void)
 706 {
 707 #if !defined(CONFIG_SPL_BUILD)
 708         uint8_t mac_addr[6];
 709         uint32_t mac_hi, mac_lo;
 710 #endif
 711
 712 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 713         char *name = NULL;
 714
 715         if (board_is_bone_lt()) {
 716                 /* BeagleBoard.org BeagleBone Black Wireless: */
 717                 if (!strncmp(board_ti_get_rev(), "BWA", 3)) {
 718                         name = "BBBW";
 719                 }
 720                 /* SeeedStudio BeagleBone Green Wireless */
 721                 if (!strncmp(board_ti_get_rev(), "GW1", 3)) {
 722                         name = "BBGW";
 723                 }
 724                 /* BeagleBoard.org BeagleBone Blue */
 725                 if (!strncmp(board_ti_get_rev(), "BLA", 3)) {
 726                         name = "BBBL";
 727                 }
 728         }
 729
 730         if (board_is_bbg1())
 731                 name = "BBG1";
 732         set_board_info_env(name);
 733
 734         /*
 735          * Default FIT boot on HS devices. Non FIT images are not allowed
 736          * on HS devices.
 737          */
 738         if (get_device_type() == HS_DEVICE)
 739                 setenv("boot_fit", "1");
 740 #endif
 741
 742 #if !defined(CONFIG_SPL_BUILD)
 743         /* try reading mac address from efuse */
 744         mac_lo = readl(&cdev->macid0l);
 745         mac_hi = readl(&cdev->macid0h);
 746         mac_addr[0] = mac_hi & 0xFF;
 747         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 748         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 749         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 750         mac_addr[4] = mac_lo & 0xFF;
 751         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 752
 753         if (!getenv("ethaddr")) {
 754                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 755
 756                 if (is_valid_ethaddr(mac_addr))
 757                         eth_setenv_enetaddr("ethaddr", mac_addr);
 758         }
 759
 760         mac_lo = readl(&cdev->macid1l);
 761         mac_hi = readl(&cdev->macid1h);
 762         mac_addr[0] = mac_hi & 0xFF;
 763         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 764         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 765         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 766         mac_addr[4] = mac_lo & 0xFF;
 767         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 768
 769         if (!getenv("eth1addr")) {
 770                 if (is_valid_ethaddr(mac_addr))
 771                         eth_setenv_enetaddr("eth1addr", mac_addr);
 772         }
 773 #endif
 774
 775         return 0;
 776 }
 777 #endif
 778
 779 #ifndef CONFIG_DM_ETH
 780
 781 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 782         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 783 static void cpsw_control(int enabled)
 784 {
 785         /* VTP can be added here */
 786
 787         return;
 788 }
 789
 790 static struct cpsw_slave_data cpsw_slaves[] = {
 791         {
 792                 .slave_reg_ofs  = 0x208,
 793                 .sliver_reg_ofs = 0xd80,
 794                 .phy_addr       = 0,
 795         },
 796         {
 797                 .slave_reg_ofs  = 0x308,
 798                 .sliver_reg_ofs = 0xdc0,
 799                 .phy_addr       = 1,
 800         },
 801 };
 802
 803 static struct cpsw_platform_data cpsw_data = {
 804         .mdio_base              = CPSW_MDIO_BASE,
 805         .cpsw_base              = CPSW_BASE,
 806         .mdio_div               = 0xff,
 807         .channels               = 8,
 808         .cpdma_reg_ofs          = 0x800,
 809         .slaves                 = 1,
 810         .slave_data             = cpsw_slaves,
 811         .ale_reg_ofs            = 0xd00,
 812         .ale_entries            = 1024,
 813         .host_port_reg_ofs      = 0x108,
 814         .hw_stats_reg_ofs       = 0x900,
 815         .bd_ram_ofs             = 0x2000,
 816         .mac_control            = (1 << 5),
 817         .control                = cpsw_control,
 818         .host_port_num          = 0,
 819         .version                = CPSW_CTRL_VERSION_2,
 820 };
 821 #endif
 822
 823 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\
 824         defined(CONFIG_SPL_BUILD)) || \
 825         ((defined(CONFIG_DRIVER_TI_CPSW) || \
 826           defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
 827          !defined(CONFIG_SPL_BUILD))
 828
 829 /*
 830  * This function will:
 831  * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
 832  * in the environment
 833  * Perform fixups to the PHY present on certain boards.  We only need this
 834  * function in:
 835  * - SPL with either CPSW or USB ethernet support
 836  * - Full U-Boot, with either CPSW or USB ethernet
 837  * Build in only these cases to avoid warnings about unused variables
 838  * when we build an SPL that has neither option but full U-Boot will.
 839  */
 840 int board_eth_init(bd_t *bis)
 841 {
 842         int rv, n = 0;
 843 #if defined(CONFIG_USB_ETHER) && \
 844         (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
 845         uint8_t mac_addr[6];
 846         uint32_t mac_hi, mac_lo;
 847
 848         /*
 849          * use efuse mac address for USB ethernet as we know that
 850          * both CPSW and USB ethernet will never be active at the same time
 851          */
 852         mac_lo = readl(&cdev->macid0l);
 853         mac_hi = readl(&cdev->macid0h);
 854         mac_addr[0] = mac_hi & 0xFF;
 855         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 856         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 857         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 858         mac_addr[4] = mac_lo & 0xFF;
 859         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 860 #endif
 861
 862
 863 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 864         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 865
 866 #ifdef CONFIG_DRIVER_TI_CPSW
 867         if (board_is_bone() || board_is_bone_lt() ||
 868             board_is_idk()) {
 869                 writel(MII_MODE_ENABLE, &cdev->miisel);
 870                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 871                                 PHY_INTERFACE_MODE_MII;
 872         } else if (board_is_icev2()) {
 873                 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
 874                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
 875                 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
 876                 cpsw_slaves[0].phy_addr = 1;
 877                 cpsw_slaves[1].phy_addr = 3;
 878         } else {
 879                 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
 880                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 881                                 PHY_INTERFACE_MODE_RGMII;
 882         }
 883
 884         rv = cpsw_register(&cpsw_data);
 885         if (rv < 0)
 886                 printf("Error %d registering CPSW switch\n", rv);
 887         else
 888                 n += rv;
 889 #endif
 890
 891         /*
 892          *
 893          * CPSW RGMII Internal Delay Mode is not supported in all PVT
 894          * operating points.  So we must set the TX clock delay feature
 895          * in the AR8051 PHY.  Since we only support a single ethernet
 896          * device in U-Boot, we only do this for the first instance.
 897          */
 898 #define AR8051_PHY_DEBUG_ADDR_REG       0x1d
 899 #define AR8051_PHY_DEBUG_DATA_REG       0x1e
 900 #define AR8051_DEBUG_RGMII_CLK_DLY_REG  0x5
 901 #define AR8051_RGMII_TX_CLK_DLY         0x100
 902
 903         if (board_is_evm_sk() || board_is_gp_evm()) {
 904                 const char *devname;
 905                 devname = miiphy_get_current_dev();
 906
 907                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
 908                                 AR8051_DEBUG_RGMII_CLK_DLY_REG);
 909                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
 910                                 AR8051_RGMII_TX_CLK_DLY);
 911         }
 912 #endif
 913 #if defined(CONFIG_USB_ETHER) && \
 914         (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
 915         if (is_valid_ethaddr(mac_addr))
 916                 eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
 917
 918         rv = usb_eth_initialize(bis);
 919         if (rv < 0)
 920                 printf("Error %d registering USB_ETHER\n", rv);
 921         else
 922                 n += rv;
 923 #endif
 924         return n;
 925 }
 926 #endif
 927
 928 #endif /* CONFIG_DM_ETH */
 929
 930 #ifdef CONFIG_SPL_LOAD_FIT
 931 int board_fit_config_name_match(const char *name)
 932 {
 933         if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
 934                 return 0;
 935         else if (board_is_bone() && !strcmp(name, "am335x-bone"))
 936                 return 0;
 937         else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
 938                 return 0;
 939         else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
 940                 return 0;
 941         else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
 942                 return 0;
 943         else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
 944                 return 0;
 945         else
 946                 return -1;
 947 }
 948 #endif
 949
 950 #ifdef CONFIG_TI_SECURE_DEVICE
 951 void board_fit_image_post_process(void **p_image, size_t *p_size)
 952 {
 953         secure_boot_verify_image(p_image, p_size);
 954 }
 955 #endif
 956
 957 #if !CONFIG_IS_ENABLED(OF_CONTROL)
 958 static const struct omap_hsmmc_plat am335x_mmc0_platdata = {
 959         .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
 960         .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
 961         .cfg.f_min = 400000,
 962         .cfg.f_max = 52000000,
 963         .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
 964         .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
 965 };
 966
 967 U_BOOT_DEVICE(am335x_mmc0) = {
 968         .name = "omap_hsmmc",
 969         .platdata = &am335x_mmc0_platdata,
 970 };
 971
 972 static const struct omap_hsmmc_plat am335x_mmc1_platdata = {
 973         .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
 974         .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
 975         .cfg.f_min = 400000,
 976         .cfg.f_max = 52000000,
 977         .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
 978         .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
 979 };
 980
 981 U_BOOT_DEVICE(am335x_mmc1) = {
 982         .name = "omap_hsmmc",
 983         .platdata = &am335x_mmc1_platdata,
 984 };
 985 #endif