board/ti/am335x/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Board functions for TI AM335X based boards
   6  *
   7  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <env.h>
  13 #include <errno.h>
  14 #include <image.h>
  15 #include <init.h>
  16 #include <malloc.h>
  17 #include <net.h>
  18 #include <spl.h>
  19 #include <serial.h>
  20 #include <asm/arch/cpu.h>
  21 #include <asm/arch/hardware.h>
  22 #include <asm/arch/omap.h>
  23 #include <asm/arch/ddr_defs.h>
  24 #include <asm/arch/clock.h>
  25 #include <asm/arch/clk_synthesizer.h>
  26 #include <asm/arch/gpio.h>
  27 #include <asm/arch/mmc_host_def.h>
  28 #include <asm/arch/sys_proto.h>
  29 #include <asm/arch/mem.h>
  30 #include <asm/io.h>
  31 #include <asm/emif.h>
  32 #include <asm/gpio.h>
  33 #include <asm/omap_common.h>
  34 #include <asm/omap_sec_common.h>
  35 #include <asm/omap_mmc.h>
  36 #include <i2c.h>
  37 #include <miiphy.h>
  38 #include <cpsw.h>
  39 #include <linux/delay.h>
  40 #include <power/tps65217.h>
  41 #include <power/tps65910.h>
  42 #include <env_internal.h>
  43 #include <watchdog.h>
  44 #include "../common/board_detect.h"
  45 #include "board.h"
  46
  47 DECLARE_GLOBAL_DATA_PTR;
  48
  49 /* GPIO that controls power to DDR on EVM-SK */
  50 #define GPIO_TO_PIN(bank, gpio)         (32 * (bank) + (gpio))
  51 #define GPIO_DDR_VTT_EN         GPIO_TO_PIN(0, 7)
  52 #define ICE_GPIO_DDR_VTT_EN     GPIO_TO_PIN(0, 18)
  53 #define GPIO_PR1_MII_CTRL       GPIO_TO_PIN(3, 4)
  54 #define GPIO_MUX_MII_CTRL       GPIO_TO_PIN(3, 10)
  55 #define GPIO_FET_SWITCH_CTRL    GPIO_TO_PIN(0, 7)
  56 #define GPIO_PHY_RESET          GPIO_TO_PIN(2, 5)
  57 #define GPIO_ETH0_MODE          GPIO_TO_PIN(0, 11)
  58 #define GPIO_ETH1_MODE          GPIO_TO_PIN(1, 26)
  59
  60 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  61
  62 #define GPIO0_RISINGDETECT      (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
  63 #define GPIO1_RISINGDETECT      (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
  64
  65 #define GPIO0_IRQSTATUS1        (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
  66 #define GPIO1_IRQSTATUS1        (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
  67
  68 #define GPIO0_IRQSTATUSRAW      (AM33XX_GPIO0_BASE + 0x024)
  69 #define GPIO1_IRQSTATUSRAW      (AM33XX_GPIO1_BASE + 0x024)
  70
  71 /*
  72  * Read header information from EEPROM into global structure.
  73  */
  74 #ifdef CONFIG_TI_I2C_BOARD_DETECT
  75 void do_board_detect(void)
  76 {
  77         enable_i2c0_pin_mux();
  78 #ifndef CONFIG_DM_I2C
  79         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  80 #endif
  81         if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  82                                  CONFIG_EEPROM_CHIP_ADDRESS))
  83                 printf("ti_i2c_eeprom_init failed\n");
  84 }
  85 #endif
  86
  87 #ifndef CONFIG_DM_SERIAL
  88 struct serial_device *default_serial_console(void)
  89 {
  90         if (board_is_icev2())
  91                 return &eserial4_device;
  92         else
  93                 return &eserial1_device;
  94 }
  95 #endif
  96
  97 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  98 static const struct ddr_data ddr2_data = {
  99         .datardsratio0 = MT47H128M16RT25E_RD_DQS,
 100         .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
 101         .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
 102 };
 103
 104 static const struct cmd_control ddr2_cmd_ctrl_data = {
 105         .cmd0csratio = MT47H128M16RT25E_RATIO,
 106
 107         .cmd1csratio = MT47H128M16RT25E_RATIO,
 108
 109         .cmd2csratio = MT47H128M16RT25E_RATIO,
 110 };
 111
 112 static const struct emif_regs ddr2_emif_reg_data = {
 113         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
 114         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
 115         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
 116         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
 117         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
 118         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
 119 };
 120
 121 static const struct emif_regs ddr2_evm_emif_reg_data = {
 122         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
 123         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
 124         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
 125         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
 126         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
 127         .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
 128         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
 129 };
 130
 131 static const struct ddr_data ddr3_data = {
 132         .datardsratio0 = MT41J128MJT125_RD_DQS,
 133         .datawdsratio0 = MT41J128MJT125_WR_DQS,
 134         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
 135         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
 136 };
 137
 138 static const struct ddr_data ddr3_beagleblack_data = {
 139         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
 140         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
 141         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
 142         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
 143 };
 144
 145 static const struct ddr_data ddr3_evm_data = {
 146         .datardsratio0 = MT41J512M8RH125_RD_DQS,
 147         .datawdsratio0 = MT41J512M8RH125_WR_DQS,
 148         .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
 149         .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
 150 };
 151
 152 static const struct ddr_data ddr3_icev2_data = {
 153         .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
 154         .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
 155         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
 156         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
 157 };
 158
 159 static const struct cmd_control ddr3_cmd_ctrl_data = {
 160         .cmd0csratio = MT41J128MJT125_RATIO,
 161         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
 162
 163         .cmd1csratio = MT41J128MJT125_RATIO,
 164         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
 165
 166         .cmd2csratio = MT41J128MJT125_RATIO,
 167         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
 168 };
 169
 170 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
 171         .cmd0csratio = MT41K256M16HA125E_RATIO,
 172         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 173
 174         .cmd1csratio = MT41K256M16HA125E_RATIO,
 175         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 176
 177         .cmd2csratio = MT41K256M16HA125E_RATIO,
 178         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 179 };
 180
 181 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
 182         .cmd0csratio = MT41J512M8RH125_RATIO,
 183         .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 184
 185         .cmd1csratio = MT41J512M8RH125_RATIO,
 186         .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 187
 188         .cmd2csratio = MT41J512M8RH125_RATIO,
 189         .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 190 };
 191
 192 static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
 193         .cmd0csratio = MT41J128MJT125_RATIO_400MHz,
 194         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 195
 196         .cmd1csratio = MT41J128MJT125_RATIO_400MHz,
 197         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 198
 199         .cmd2csratio = MT41J128MJT125_RATIO_400MHz,
 200         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 201 };
 202
 203 static struct emif_regs ddr3_emif_reg_data = {
 204         .sdram_config = MT41J128MJT125_EMIF_SDCFG,
 205         .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
 206         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
 207         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
 208         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
 209         .zq_config = MT41J128MJT125_ZQ_CFG,
 210         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
 211                                 PHY_EN_DYN_PWRDN,
 212 };
 213
 214 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
 215         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
 216         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
 217         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 218         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 219         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
 220         .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
 221         .zq_config = MT41K256M16HA125E_ZQ_CFG,
 222         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 223 };
 224
 225 static struct emif_regs ddr3_evm_emif_reg_data = {
 226         .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
 227         .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
 228         .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
 229         .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
 230         .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
 231         .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
 232         .zq_config = MT41J512M8RH125_ZQ_CFG,
 233         .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
 234                                 PHY_EN_DYN_PWRDN,
 235 };
 236
 237 static struct emif_regs ddr3_icev2_emif_reg_data = {
 238         .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
 239         .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
 240         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
 241         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
 242         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
 243         .zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
 244         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
 245                                 PHY_EN_DYN_PWRDN,
 246 };
 247
 248 #ifdef CONFIG_SPL_OS_BOOT
 249 int spl_start_uboot(void)
 250 {
 251 #ifdef CONFIG_SPL_SERIAL_SUPPORT
 252         /* break into full u-boot on 'c' */
 253         if (serial_tstc() && serial_getc() == 'c')
 254                 return 1;
 255 #endif
 256
 257 #ifdef CONFIG_SPL_ENV_SUPPORT
 258         env_init();
 259         env_load();
 260         if (env_get_yesno("boot_os") != 1)
 261                 return 1;
 262 #endif
 263
 264         return 0;
 265 }
 266 #endif
 267
 268 const struct dpll_params *get_dpll_ddr_params(void)
 269 {
 270         int ind = get_sys_clk_index();
 271
 272         if (board_is_evm_sk())
 273                 return &dpll_ddr3_303MHz[ind];
 274         else if (board_is_pb() || board_is_bone_lt() || board_is_icev2())
 275                 return &dpll_ddr3_400MHz[ind];
 276         else if (board_is_evm_15_or_later())
 277                 return &dpll_ddr3_303MHz[ind];
 278         else
 279                 return &dpll_ddr2_266MHz[ind];
 280 }
 281
 282 static u8 bone_not_connected_to_ac_power(void)
 283 {
 284         if (board_is_bone()) {
 285                 uchar pmic_status_reg;
 286                 if (tps65217_reg_read(TPS65217_STATUS,
 287                                       &pmic_status_reg))
 288                         return 1;
 289                 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
 290                         puts("No AC power, switching to default OPP\n");
 291                         return 1;
 292                 }
 293         }
 294         return 0;
 295 }
 296
 297 const struct dpll_params *get_dpll_mpu_params(void)
 298 {
 299         int ind = get_sys_clk_index();
 300         int freq = am335x_get_efuse_mpu_max_freq(cdev);
 301
 302         if (bone_not_connected_to_ac_power())
 303                 freq = MPUPLL_M_600;
 304
 305         if (board_is_pb() || board_is_bone_lt())
 306                 freq = MPUPLL_M_1000;
 307
 308         switch (freq) {
 309         case MPUPLL_M_1000:
 310                 return &dpll_mpu_opp[ind][5];
 311         case MPUPLL_M_800:
 312                 return &dpll_mpu_opp[ind][4];
 313         case MPUPLL_M_720:
 314                 return &dpll_mpu_opp[ind][3];
 315         case MPUPLL_M_600:
 316                 return &dpll_mpu_opp[ind][2];
 317         case MPUPLL_M_500:
 318                 return &dpll_mpu_opp100;
 319         case MPUPLL_M_300:
 320                 return &dpll_mpu_opp[ind][0];
 321         }
 322
 323         return &dpll_mpu_opp[ind][0];
 324 }
 325
 326 static void scale_vcores_bone(int freq)
 327 {
 328         int usb_cur_lim, mpu_vdd;
 329
 330         /*
 331          * Only perform PMIC configurations if board rev > A1
 332          * on Beaglebone White
 333          */
 334         if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
 335                 return;
 336
 337 #ifndef CONFIG_DM_I2C
 338         if (i2c_probe(TPS65217_CHIP_PM))
 339                 return;
 340 #else
 341         if (power_tps65217_init(0))
 342                 return;
 343 #endif
 344
 345
 346         /*
 347          * On Beaglebone White we need to ensure we have AC power
 348          * before increasing the frequency.
 349          */
 350         if (bone_not_connected_to_ac_power())
 351                 freq = MPUPLL_M_600;
 352
 353         /*
 354          * Override what we have detected since we know if we have
 355          * a Beaglebone Black it supports 1GHz.
 356          */
 357         if (board_is_pb() || board_is_bone_lt())
 358                 freq = MPUPLL_M_1000;
 359
 360         switch (freq) {
 361         case MPUPLL_M_1000:
 362                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
 363                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
 364                 break;
 365         case MPUPLL_M_800:
 366                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
 367                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 368                 break;
 369         case MPUPLL_M_720:
 370                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
 371                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 372                 break;
 373         case MPUPLL_M_600:
 374         case MPUPLL_M_500:
 375         case MPUPLL_M_300:
 376         default:
 377                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
 378                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 379                 break;
 380         }
 381
 382         if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
 383                                TPS65217_POWER_PATH,
 384                                usb_cur_lim,
 385                                TPS65217_USB_INPUT_CUR_LIMIT_MASK))
 386                 puts("tps65217_reg_write failure\n");
 387
 388         /* Set DCDC3 (CORE) voltage to 1.10V */
 389         if (tps65217_voltage_update(TPS65217_DEFDCDC3,
 390                                     TPS65217_DCDC_VOLT_SEL_1100MV)) {
 391                 puts("tps65217_voltage_update failure\n");
 392                 return;
 393         }
 394
 395         /* Set DCDC2 (MPU) voltage */
 396         if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
 397                 puts("tps65217_voltage_update failure\n");
 398                 return;
 399         }
 400
 401         /*
 402          * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
 403          * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
 404          */
 405         if (board_is_bone()) {
 406                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 407                                        TPS65217_DEFLS1,
 408                                        TPS65217_LDO_VOLTAGE_OUT_3_3,
 409                                        TPS65217_LDO_MASK))
 410                         puts("tps65217_reg_write failure\n");
 411         } else {
 412                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 413                                        TPS65217_DEFLS1,
 414                                        TPS65217_LDO_VOLTAGE_OUT_1_8,
 415                                        TPS65217_LDO_MASK))
 416                         puts("tps65217_reg_write failure\n");
 417         }
 418
 419         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 420                                TPS65217_DEFLS2,
 421                                TPS65217_LDO_VOLTAGE_OUT_3_3,
 422                                TPS65217_LDO_MASK))
 423                 puts("tps65217_reg_write failure\n");
 424 }
 425
 426 void scale_vcores_generic(int freq)
 427 {
 428         int sil_rev, mpu_vdd;
 429
 430         /*
 431          * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
 432          * MPU frequencies we support we use a CORE voltage of
 433          * 1.10V.  For MPU voltage we need to switch based on
 434          * the frequency we are running at.
 435          */
 436 #ifndef CONFIG_DM_I2C
 437         if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
 438                 return;
 439 #else
 440         if (power_tps65910_init(0))
 441                 return;
 442 #endif
 443         /*
 444          * Depending on MPU clock and PG we will need a different
 445          * VDD to drive at that speed.
 446          */
 447         sil_rev = readl(&cdev->deviceid) >> 28;
 448         mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
 449
 450         /* Tell the TPS65910 to use i2c */
 451         tps65910_set_i2c_control();
 452
 453         /* First update MPU voltage. */
 454         if (tps65910_voltage_update(MPU, mpu_vdd))
 455                 return;
 456
 457         /* Second, update the CORE voltage. */
 458         if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
 459                 return;
 460
 461 }
 462
 463 void gpi2c_init(void)
 464 {
 465         /* When needed to be invoked prior to BSS initialization */
 466         static bool first_time = true;
 467
 468         if (first_time) {
 469                 enable_i2c0_pin_mux();
 470 #ifndef CONFIG_DM_I2C
 471                 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
 472                          CONFIG_SYS_OMAP24_I2C_SLAVE);
 473 #endif
 474                 first_time = false;
 475         }
 476 }
 477
 478 void scale_vcores(void)
 479 {
 480         int freq;
 481
 482         gpi2c_init();
 483         freq = am335x_get_efuse_mpu_max_freq(cdev);
 484
 485         if (board_is_beaglebonex())
 486                 scale_vcores_bone(freq);
 487         else
 488                 scale_vcores_generic(freq);
 489 }
 490
 491 void set_uart_mux_conf(void)
 492 {
 493 #if CONFIG_CONS_INDEX == 1
 494         enable_uart0_pin_mux();
 495 #elif CONFIG_CONS_INDEX == 2
 496         enable_uart1_pin_mux();
 497 #elif CONFIG_CONS_INDEX == 3
 498         enable_uart2_pin_mux();
 499 #elif CONFIG_CONS_INDEX == 4
 500         enable_uart3_pin_mux();
 501 #elif CONFIG_CONS_INDEX == 5
 502         enable_uart4_pin_mux();
 503 #elif CONFIG_CONS_INDEX == 6
 504         enable_uart5_pin_mux();
 505 #endif
 506 }
 507
 508 void set_mux_conf_regs(void)
 509 {
 510         enable_board_pin_mux();
 511 }
 512
 513 const struct ctrl_ioregs ioregs_evmsk = {
 514         .cm0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 515         .cm1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 516         .cm2ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 517         .dt0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 518         .dt1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 519 };
 520
 521 const struct ctrl_ioregs ioregs_bonelt = {
 522         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 523         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 524         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 525         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 526         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 527 };
 528
 529 const struct ctrl_ioregs ioregs_evm15 = {
 530         .cm0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 531         .cm1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 532         .cm2ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 533         .dt0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 534         .dt1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 535 };
 536
 537 const struct ctrl_ioregs ioregs = {
 538         .cm0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 539         .cm1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 540         .cm2ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 541         .dt0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 542         .dt1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 543 };
 544
 545 void sdram_init(void)
 546 {
 547         if (board_is_evm_sk()) {
 548                 /*
 549                  * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
 550                  * This is safe enough to do on older revs.
 551                  */
 552                 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 553                 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 554         }
 555
 556         if (board_is_icev2()) {
 557                 gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
 558                 gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
 559         }
 560
 561         if (board_is_evm_sk())
 562                 config_ddr(303, &ioregs_evmsk, &ddr3_data,
 563                            &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 564         else if (board_is_pb() || board_is_bone_lt())
 565                 config_ddr(400, &ioregs_bonelt,
 566                            &ddr3_beagleblack_data,
 567                            &ddr3_beagleblack_cmd_ctrl_data,
 568                            &ddr3_beagleblack_emif_reg_data, 0);
 569         else if (board_is_evm_15_or_later())
 570                 config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
 571                            &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
 572         else if (board_is_icev2())
 573                 config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
 574                            &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
 575                            0);
 576         else if (board_is_gp_evm())
 577                 config_ddr(266, &ioregs, &ddr2_data,
 578                            &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
 579         else
 580                 config_ddr(266, &ioregs, &ddr2_data,
 581                            &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
 582 }
 583 #endif
 584
 585 #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
 586         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
 587 static void request_and_set_gpio(int gpio, char *name, int val)
 588 {
 589         int ret;
 590
 591         ret = gpio_request(gpio, name);
 592         if (ret < 0) {
 593                 printf("%s: Unable to request %s\n", __func__, name);
 594                 return;
 595         }
 596
 597         ret = gpio_direction_output(gpio, 0);
 598         if (ret < 0) {
 599                 printf("%s: Unable to set %s  as output\n", __func__, name);
 600                 goto err_free_gpio;
 601         }
 602
 603         gpio_set_value(gpio, val);
 604
 605         return;
 606
 607 err_free_gpio:
 608         gpio_free(gpio);
 609 }
 610
 611 #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1);
 612 #define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0);
 613
 614 /**
 615  * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
 616  * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
 617  * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
 618  * give 50MHz output for Eth0 and 1.
 619  */
 620 static struct clk_synth cdce913_data = {
 621         .id = 0x81,
 622         .capacitor = 0x90,
 623         .mux = 0x6d,
 624         .pdiv2 = 0x2,
 625         .pdiv3 = 0x2,
 626 };
 627 #endif
 628
 629 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_CONTROL) && \
 630         defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW)
 631
 632 #define MAX_CPSW_SLAVES 2
 633
 634 /* At the moment, we do not want to stop booting for any failures here */
 635 int ft_board_setup(void *fdt, bd_t *bd)
 636 {
 637         const char *slave_path, *enet_name;
 638         int enetnode, slavenode, phynode;
 639         struct udevice *ethdev;
 640         char alias[16];
 641         u32 phy_id[2];
 642         int phy_addr;
 643         int i, ret;
 644
 645         /* phy address fixup needed only on beagle bone family */
 646         if (!board_is_beaglebonex())
 647                 goto done;
 648
 649         for (i = 0; i < MAX_CPSW_SLAVES; i++) {
 650                 sprintf(alias, "ethernet%d", i);
 651
 652                 slave_path = fdt_get_alias(fdt, alias);
 653                 if (!slave_path)
 654                         continue;
 655
 656                 slavenode = fdt_path_offset(fdt, slave_path);
 657                 if (slavenode < 0)
 658                         continue;
 659
 660                 enetnode = fdt_parent_offset(fdt, slavenode);
 661                 enet_name = fdt_get_name(fdt, enetnode, NULL);
 662
 663                 ethdev = eth_get_dev_by_name(enet_name);
 664                 if (!ethdev)
 665                         continue;
 666
 667                 phy_addr = cpsw_get_slave_phy_addr(ethdev, i);
 668
 669                 /* check for phy_id as well as phy-handle properties */
 670                 ret = fdtdec_get_int_array_count(fdt, slavenode, "phy_id",
 671                                                  phy_id, 2);
 672                 if (ret == 2) {
 673                         if (phy_id[1] != phy_addr) {
 674                                 printf("fixing up phy_id for %s, old: %d, new: %d\n",
 675                                        alias, phy_id[1], phy_addr);
 676
 677                                 phy_id[0] = cpu_to_fdt32(phy_id[0]);
 678                                 phy_id[1] = cpu_to_fdt32(phy_addr);
 679                                 do_fixup_by_path(fdt, slave_path, "phy_id",
 680                                                  phy_id, sizeof(phy_id), 0);
 681                         }
 682                 } else {
 683                         phynode = fdtdec_lookup_phandle(fdt, slavenode,
 684                                                         "phy-handle");
 685                         if (phynode < 0)
 686                                 continue;
 687
 688                         ret = fdtdec_get_int(fdt, phynode, "reg", -ENOENT);
 689                         if (ret < 0)
 690                                 continue;
 691
 692                         if (ret != phy_addr) {
 693                                 printf("fixing up phy-handle for %s, old: %d, new: %d\n",
 694                                        alias, ret, phy_addr);
 695
 696                                 fdt_setprop_u32(fdt, phynode, "reg",
 697                                                 cpu_to_fdt32(phy_addr));
 698                         }
 699                 }
 700         }
 701
 702 done:
 703         return 0;
 704 }
 705 #endif
 706
 707 /*
 708  * Basic board specific setup.  Pinmux has been handled already.
 709  */
 710 int board_init(void)
 711 {
 712 #if defined(CONFIG_HW_WATCHDOG)
 713         hw_watchdog_init();
 714 #endif
 715
 716         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 717 #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
 718         gpmc_init();
 719 #endif
 720
 721 #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
 722         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
 723         if (board_is_icev2()) {
 724                 int rv;
 725                 u32 reg;
 726
 727                 REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
 728                 /* Make J19 status available on GPIO1_26 */
 729                 REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL);
 730
 731                 REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
 732                 /*
 733                  * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
 734                  * jumpers near the port. Read the jumper value and set
 735                  * the pinmux, external mux and PHY clock accordingly.
 736                  * As jumper line is overridden by PHY RX_DV pin immediately
 737                  * after bootstrap (power-up/reset), we need to sample
 738                  * it during PHY reset using GPIO rising edge detection.
 739                  */
 740                 REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
 741                 /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
 742                 reg = readl(GPIO0_RISINGDETECT) | BIT(11);
 743                 writel(reg, GPIO0_RISINGDETECT);
 744                 reg = readl(GPIO1_RISINGDETECT) | BIT(26);
 745                 writel(reg, GPIO1_RISINGDETECT);
 746                 /* Reset PHYs to capture the Jumper setting */
 747                 gpio_set_value(GPIO_PHY_RESET, 0);
 748                 udelay(2);      /* PHY datasheet states 1uS min. */
 749                 gpio_set_value(GPIO_PHY_RESET, 1);
 750
 751                 reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11);
 752                 if (reg) {
 753                         writel(reg, GPIO0_IRQSTATUS1); /* clear irq */
 754                         /* RMII mode */
 755                         printf("ETH0, CPSW\n");
 756                 } else {
 757                         /* MII mode */
 758                         printf("ETH0, PRU\n");
 759                         cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */
 760                 }
 761
 762                 reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26);
 763                 if (reg) {
 764                         writel(reg, GPIO1_IRQSTATUS1); /* clear irq */
 765                         /* RMII mode */
 766                         printf("ETH1, CPSW\n");
 767                         gpio_set_value(GPIO_MUX_MII_CTRL, 1);
 768                 } else {
 769                         /* MII mode */
 770                         printf("ETH1, PRU\n");
 771                         cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */
 772                 }
 773
 774                 /* disable rising edge IRQs */
 775                 reg = readl(GPIO0_RISINGDETECT) & ~BIT(11);
 776                 writel(reg, GPIO0_RISINGDETECT);
 777                 reg = readl(GPIO1_RISINGDETECT) & ~BIT(26);
 778                 writel(reg, GPIO1_RISINGDETECT);
 779
 780                 rv = setup_clock_synthesizer(&cdce913_data);
 781                 if (rv) {
 782                         printf("Clock synthesizer setup failed %d\n", rv);
 783                         return rv;
 784                 }
 785
 786                 /* reset PHYs */
 787                 gpio_set_value(GPIO_PHY_RESET, 0);
 788                 udelay(2);      /* PHY datasheet states 1uS min. */
 789                 gpio_set_value(GPIO_PHY_RESET, 1);
 790         }
 791 #endif
 792
 793         return 0;
 794 }
 795
 796 #ifdef CONFIG_BOARD_LATE_INIT
 797 int board_late_init(void)
 798 {
 799         struct udevice *dev;
 800 #if !defined(CONFIG_SPL_BUILD)
 801         uint8_t mac_addr[6];
 802         uint32_t mac_hi, mac_lo;
 803 #endif
 804
 805 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 806         char *name = NULL;
 807
 808         if (board_is_bone_lt()) {
 809                 /* BeagleBoard.org BeagleBone Black Wireless: */
 810                 if (!strncmp(board_ti_get_rev(), "BWA", 3)) {
 811                         name = "BBBW";
 812                 }
 813                 /* SeeedStudio BeagleBone Green Wireless */
 814                 if (!strncmp(board_ti_get_rev(), "GW1", 3)) {
 815                         name = "BBGW";
 816                 }
 817                 /* BeagleBoard.org BeagleBone Blue */
 818                 if (!strncmp(board_ti_get_rev(), "BLA", 3)) {
 819                         name = "BBBL";
 820                 }
 821         }
 822
 823         if (board_is_bbg1())
 824                 name = "BBG1";
 825         if (board_is_bben())
 826                 name = "BBEN";
 827         set_board_info_env(name);
 828
 829         /*
 830          * Default FIT boot on HS devices. Non FIT images are not allowed
 831          * on HS devices.
 832          */
 833         if (get_device_type() == HS_DEVICE)
 834                 env_set("boot_fit", "1");
 835 #endif
 836
 837 #if !defined(CONFIG_SPL_BUILD)
 838         /* try reading mac address from efuse */
 839         mac_lo = readl(&cdev->macid0l);
 840         mac_hi = readl(&cdev->macid0h);
 841         mac_addr[0] = mac_hi & 0xFF;
 842         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 843         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 844         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 845         mac_addr[4] = mac_lo & 0xFF;
 846         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 847
 848         if (!env_get("ethaddr")) {
 849                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 850
 851                 if (is_valid_ethaddr(mac_addr))
 852                         eth_env_set_enetaddr("ethaddr", mac_addr);
 853         }
 854
 855         mac_lo = readl(&cdev->macid1l);
 856         mac_hi = readl(&cdev->macid1h);
 857         mac_addr[0] = mac_hi & 0xFF;
 858         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 859         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 860         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 861         mac_addr[4] = mac_lo & 0xFF;
 862         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 863
 864         if (!env_get("eth1addr")) {
 865                 if (is_valid_ethaddr(mac_addr))
 866                         eth_env_set_enetaddr("eth1addr", mac_addr);
 867         }
 868 #endif
 869
 870         if (!env_get("serial#")) {
 871                 char *board_serial = env_get("board_serial");
 872                 char *ethaddr = env_get("ethaddr");
 873
 874                 if (!board_serial || !strncmp(board_serial, "unknown", 7))
 875                         env_set("serial#", ethaddr);
 876                 else
 877                         env_set("serial#", board_serial);
 878         }
 879
 880         /* Just probe the potentially supported cdce913 device */
 881         uclass_get_device(UCLASS_CLK, 0, &dev);
 882
 883         return 0;
 884 }
 885 #endif
 886
 887 /* CPSW platdata */
 888 #if !CONFIG_IS_ENABLED(OF_CONTROL)
 889 struct cpsw_slave_data slave_data[] = {
 890         {
 891                 .slave_reg_ofs  = CPSW_SLAVE0_OFFSET,
 892                 .sliver_reg_ofs = CPSW_SLIVER0_OFFSET,
 893                 .phy_addr       = 0,
 894         },
 895         {
 896                 .slave_reg_ofs  = CPSW_SLAVE1_OFFSET,
 897                 .sliver_reg_ofs = CPSW_SLIVER1_OFFSET,
 898                 .phy_addr       = 1,
 899         },
 900 };
 901
 902 struct cpsw_platform_data am335_eth_data = {
 903         .cpsw_base              = CPSW_BASE,
 904         .version                = CPSW_CTRL_VERSION_2,
 905         .bd_ram_ofs             = CPSW_BD_OFFSET,
 906         .ale_reg_ofs            = CPSW_ALE_OFFSET,
 907         .cpdma_reg_ofs          = CPSW_CPDMA_OFFSET,
 908         .mdio_div               = CPSW_MDIO_DIV,
 909         .host_port_reg_ofs      = CPSW_HOST_PORT_OFFSET,
 910         .channels               = 8,
 911         .slaves                 = 2,
 912         .slave_data             = slave_data,
 913         .ale_entries            = 1024,
 914         .bd_ram_ofs             = 0x2000,
 915         .mac_control            = 0x20,
 916         .active_slave           = 0,
 917         .mdio_base              = 0x4a101000,
 918         .gmii_sel               = 0x44e10650,
 919         .phy_sel_compat         = "ti,am3352-cpsw-phy-sel",
 920         .syscon_addr            = 0x44e10630,
 921         .macid_sel_compat       = "cpsw,am33xx",
 922 };
 923
 924 struct eth_pdata cpsw_pdata = {
 925         .iobase = 0x4a100000,
 926         .phy_interface = 0,
 927         .priv_pdata = &am335_eth_data,
 928 };
 929
 930 U_BOOT_DEVICE(am335x_eth) = {
 931         .name = "eth_cpsw",
 932         .platdata = &cpsw_pdata,
 933 };
 934 #endif
 935
 936 #ifdef CONFIG_SPL_LOAD_FIT
 937 int board_fit_config_name_match(const char *name)
 938 {
 939         if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
 940                 return 0;
 941         else if (board_is_bone() && !strcmp(name, "am335x-bone"))
 942                 return 0;
 943         else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
 944                 return 0;
 945         else if (board_is_pb() && !strcmp(name, "am335x-pocketbeagle"))
 946                 return 0;
 947         else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
 948                 return 0;
 949         else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
 950                 return 0;
 951         else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
 952                 return 0;
 953         else
 954                 return -1;
 955 }
 956 #endif
 957
 958 #ifdef CONFIG_TI_SECURE_DEVICE
 959 void board_fit_image_post_process(void **p_image, size_t *p_size)
 960 {
 961         secure_boot_verify_image(p_image, p_size);
 962 }
 963 #endif
 964
 965 #if !CONFIG_IS_ENABLED(OF_CONTROL)
 966 static const struct omap_hsmmc_plat am335x_mmc0_platdata = {
 967         .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
 968         .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
 969         .cfg.f_min = 400000,
 970         .cfg.f_max = 52000000,
 971         .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
 972         .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
 973 };
 974
 975 U_BOOT_DEVICE(am335x_mmc0) = {
 976         .name = "omap_hsmmc",
 977         .platdata = &am335x_mmc0_platdata,
 978 };
 979
 980 static const struct omap_hsmmc_plat am335x_mmc1_platdata = {
 981         .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
 982         .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
 983         .cfg.f_min = 400000,
 984         .cfg.f_max = 52000000,
 985         .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
 986         .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
 987 };
 988
 989 U_BOOT_DEVICE(am335x_mmc1) = {
 990         .name = "omap_hsmmc",
 991         .platdata = &am335x_mmc1_platdata,
 992 };
 993 #endif