1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2019 Stefan Roese <sr@denx.de>
13 #if !defined(CONFIG_SPL_BUILD)
14 #include <bootcount.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/soc.h>
20 #include <linux/delay.h>
21 #include <linux/mbus.h>
25 #include <u-boot/crc.h>
26 #include "theadorable.h"
28 #include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
29 #include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
31 DECLARE_GLOBAL_DATA_PTR;
33 #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
34 #define PHY_CHANNEL_RX_CTRL0_REG(port, chan) \
35 (MV_USB_PHY_BASE + ((port) << 12) + ((chan) << 6) + 0x8)
37 #define THEADORABLE_GPP_OUT_ENA_LOW 0x00336780
38 #define THEADORABLE_GPP_OUT_ENA_MID 0x00003cf0
39 #define THEADORABLE_GPP_OUT_ENA_HIGH (~(0x0))
41 #define THEADORABLE_GPP_OUT_VAL_LOW 0x2c0c983f
42 #define THEADORABLE_GPP_OUT_VAL_MID 0x0007000c
43 #define THEADORABLE_GPP_OUT_VAL_HIGH 0x00000000
45 #define GPIO_USB0_PWR_ON 18
46 #define GPIO_USB1_PWR_ON 19
48 #define PEX_SWITCH_NOT_FOUNT_LIMIT 3
51 #define STM_I2C_ADDR 0x27
52 #define REBOOT_DELAY 1000 /* reboot-delay in ms */
53 #define ABORT_TIMEOUT 3000 /* 3 seconds reboot abort timeout */
55 /* DDR3 static configuration */
56 static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = {
57 {0x00001400, 0x7301ca28}, /* DDR SDRAM Configuration Register */
58 {0x00001404, 0x30000800}, /* Dunit Control Low Register */
59 {0x00001408, 0x44149887}, /* DDR SDRAM Timing (Low) Register */
60 {0x0000140C, 0x38d93fc7}, /* DDR SDRAM Timing (High) Register */
61 {0x00001410, 0x1b100001}, /* DDR SDRAM Address Control Register */
62 {0x00001424, 0x0000f3ff}, /* Dunit Control High Register */
63 {0x00001428, 0x000f8830}, /* ODT Timing (Low) Register */
64 {0x0000142C, 0x014c50f4}, /* DDR3 Timing Register */
65 {0x0000147C, 0x0000c671}, /* ODT Timing (High) Register */
67 {0x00001494, 0x00010000}, /* DDR SDRAM ODT Control (Low) Reg */
68 {0x0000149C, 0x00000001}, /* DDR Dunit ODT Control Register */
69 {0x000014A0, 0x00000001}, /* DRAM FIFO Control Register */
70 {0x000014A8, 0x00000101}, /* AXI Control Register */
73 * DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the
76 {0x000200e8, 0x3fff0e01},
77 {0x00020184, 0x3fffffe0}, /* Close fast path Window to - 2G */
79 {0x0001504, 0x7fffffe1}, /* CS0 Size */
80 {0x000150C, 0x00000000}, /* CS1 Size */
81 {0x0001514, 0x00000000}, /* CS2 Size */
82 {0x000151C, 0x00000000}, /* CS3 Size */
84 {0x00020220, 0x00000007}, /* Reserved */
86 {0x00001538, 0x00000009}, /* Read Data Sample Delays Register */
87 {0x0000153C, 0x00000009}, /* Read Data Ready Delay Register */
89 {0x000015D0, 0x00000650}, /* MR0 */
90 {0x000015D4, 0x00000044}, /* MR1 */
91 {0x000015D8, 0x00000010}, /* MR2 */
92 {0x000015DC, 0x00000000}, /* MR3 */
93 {0x000015E0, 0x00000001},
94 {0x000015E4, 0x00203c18}, /* ZQDS Configuration Register */
95 {0x000015EC, 0xf800a225}, /* DDR PHY */
97 /* Recommended Settings from Marvell for 4 x 16 bit devices: */
98 {0x000014C0, 0x192424c9}, /* DRAM addr and Ctrl Driving Strenght*/
99 {0x000014C4, 0x0aaa24c9}, /* DRAM Data and DQS Driving Strenght */
104 static MV_DRAM_MODES board_ddr_modes[MV_DDR3_MODES_NUMBER] = {
105 {"theadorable_1333-667", 0x3, 0x5, 0x0, A0, ddr3_theadorable, NULL},
108 extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
111 * Lane0 - PCIE0.0 X1 (to WIFI Module)
114 * Lane7 - SGMII0 (to Ethernet Phy)
115 * Lane8-11 - PCIE2.0 X4 (to PEX Switch)
116 * all other lanes are disabled
118 MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = {
119 { MV_PEX_ROOT_COMPLEX, 0x22200001, 0x00001111,
120 { PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4,
122 0x0060, serdes_change_m_phy
127 * Define a board-specific detection pulse-width array for the SerDes PCIe
128 * interfaces. If not defined in the board code, the default of currently 2
129 * is used. Values from 0...3 are possible (2 bits).
131 u8 serdes_pex_pulse_width[4] = { 0, 2, 2, 2 };
133 MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
135 /* Only one mode supported for this board */
136 return &board_ddr_modes[0];
139 MV_BIN_SERDES_CFG *board_serdes_cfg_get(void)
141 return &theadorable_serdes_cfg[0];
144 u8 board_sat_r_get(u8 dev_num, u8 reg)
146 /* Bit x enables PCI 2.0 link capabilities instead of PCI 1.x */
147 return 0xe; /* PEX port 0 is PCIe Gen1, PEX port 1..3 PCIe Gen2 */
150 int board_early_init_f(void)
153 writel(0x00000000, MVEBU_MPP_BASE + 0x00);
154 writel(0x03300000, MVEBU_MPP_BASE + 0x04);
155 writel(0x00000033, MVEBU_MPP_BASE + 0x08);
156 writel(0x00000000, MVEBU_MPP_BASE + 0x0c);
157 writel(0x11110000, MVEBU_MPP_BASE + 0x10);
158 writel(0x00221100, MVEBU_MPP_BASE + 0x14);
159 writel(0x00000000, MVEBU_MPP_BASE + 0x18);
160 writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
161 writel(0x00000000, MVEBU_MPP_BASE + 0x20);
164 writel(THEADORABLE_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
165 writel(THEADORABLE_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
166 writel(THEADORABLE_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
167 writel(THEADORABLE_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
168 writel(THEADORABLE_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
169 writel(THEADORABLE_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
178 /* adress of boot parameters */
179 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
182 * Map SPI devices via MBUS so that they can be accessed via
183 * the SPI direct access mode
185 mbus_dt_setup_win(&mbus_state, SPI_BUS0_DEV1_BASE, SPI_BUS0_DEV1_SIZE,
186 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI0_CS1);
187 mbus_dt_setup_win(&mbus_state, SPI_BUS1_DEV2_BASE, SPI_BUS0_DEV1_SIZE,
188 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI1_CS2);
191 * Set RX Channel Control 0 Register:
192 * Tests have shown, that setting the LPF_COEF from 0 (1/8)
193 * to 3 (1/1) results in a more stable USB connection.
195 setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 1), 0xc);
196 setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 2), 0xc);
197 setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 3), 0xc);
199 /* Toggle USB power */
200 ret = gpio_request(GPIO_USB0_PWR_ON, "USB0_PWR_ON");
203 gpio_direction_output(GPIO_USB0_PWR_ON, 0);
204 ret = gpio_request(GPIO_USB1_PWR_ON, "USB1_PWR_ON");
207 gpio_direction_output(GPIO_USB1_PWR_ON, 0);
209 gpio_set_value(GPIO_USB0_PWR_ON, 1);
210 gpio_set_value(GPIO_USB1_PWR_ON, 1);
223 int board_eth_init(bd_t *bis)
225 cpu_eth_init(bis); /* Built in controller(s) come first */
226 return pci_eth_init(bis);
230 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_LATE_INIT)
231 int board_late_init(void)
237 * Check if the PEX switch is detected (somtimes its not available
238 * on the PCIe bus). In this case, try to recover by issuing a
239 * soft-reset or even a power-cycle, depending on the bootcounter
242 bdf = pci_find_device(PCI_VENDOR_ID_PLX, 0x8619, 0);
244 unsigned long start_time = get_timer(0);
248 /* PEX switch not found! */
249 bootcount = bootcount_load();
250 printf("Failed to find PLX PEX-switch (bootcount=%ld)\n",
254 * The user can exit this boot-loop in the error case by
255 * hitting Ctrl-C. So wait some time for this key here.
257 printf("Continue booting with Ctrl-C, otherwise rebooting\n");
259 /* Handle control-c and timeouts */
261 printf("PEX error boot-loop aborted!\n");
264 } while (get_timer(start_time) < ABORT_TIMEOUT);
268 * At this stage the bootcounter has not been incremented
269 * yet. We need to do this manually here to get an actually
270 * working bootcounter in this error case.
274 if (bootcount > PEX_SWITCH_NOT_FOUNT_LIMIT) {
275 printf("Issuing power-switch via uC!\n");
277 printf("Issuing power-switch via uC!\n");
278 i2c_set_bus_num(STM_I2C_BUS);
279 i2c_buf[0] = STM_I2C_ADDR << 1;
280 i2c_buf[1] = 0xc5; /* cmd */
281 i2c_buf[2] = 0x01; /* enable */
282 /* Delay before reboot */
283 i2c_buf[3] = REBOOT_DELAY & 0x00ff;
284 i2c_buf[4] = (REBOOT_DELAY & 0xff00) >> 8;
285 /* Delay before shutdown */
288 i2c_buf[7] = crc8(0x72, &i2c_buf[0], 7);
290 ret = i2c_write(STM_I2C_ADDR, 0, 0, &i2c_buf[1], 7);
292 printf("I2C write error (ret=%d)\n", ret);
293 printf("Issuing soft-reset...\n");
294 /* default handling: SOFT reset */
295 do_reset(NULL, 0, 0, NULL);
298 /* Wait for power-cycle to occur... */
299 printf("Waiting for power-cycle via uC...\n");
303 printf("Issuing soft-reset...\n");
304 /* default handling: SOFT reset */
305 do_reset(NULL, 0, 0, NULL);
313 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_PCI)
314 int do_pcie_test(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
320 return cmd_usage(cmdtp);
322 ven_id = simple_strtoul(argv[1], NULL, 16);
323 dev_id = simple_strtoul(argv[2], NULL, 16);
325 printf("Checking for PCIe device: VendorID 0x%04x, DeviceId 0x%04x\n",
329 * Check if the PCIe device is detected (somtimes its not available
332 bdf = pci_find_device(ven_id, dev_id, 0);
334 /* PCIe device not found! */
335 printf("Failed to find PCIe device\n");
337 /* PCIe device found! */
338 printf("PCIe device found, resetting board...\n");
340 /* default handling: SOFT reset */
341 do_reset(NULL, 0, 0, NULL);
348 pcie, 3, 0, do_pcie_test,
349 "Test for presence of a PCIe device",
350 "<VendorID> <DeviceID>"