board/technologic/ts4800/ts4800.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2015 Savoir-faire Linux Inc.
   4  *
   5  * Derived from MX51EVK code by
   6  *   Freescale Semiconductor, Inc.
   7  */
   8
   9 #include <common.h>
  10 #include <init.h>
  11 #include <log.h>
  12 #include <net.h>
  13 #include <asm/io.h>
  14 #include <asm/gpio.h>
  15 #include <asm/arch/imx-regs.h>
  16 #include <asm/arch/iomux-mx51.h>
  17 #include <env.h>
  18 #include <linux/delay.h>
  19 #include <linux/errno.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/arch/crm_regs.h>
  22 #include <asm/arch/clock.h>
  23 #include <asm/mach-imx/mx5_video.h>
  24 #include <mmc.h>
  25 #include <input.h>
  26 #include <fsl_esdhc_imx.h>
  27 #include <mc13892.h>
  28
  29 #include <malloc.h>
  30 #include <netdev.h>
  31 #include <phy.h>
  32 #include "ts4800.h"
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 #ifdef CONFIG_FSL_ESDHC_IMX
  37 struct fsl_esdhc_cfg esdhc_cfg[2] = {
  38         {MMC_SDHC1_BASE_ADDR},
  39         {MMC_SDHC2_BASE_ADDR},
  40 };
  41 #endif
  42
  43 int dram_init(void)
  44 {
  45         /* dram_init must store complete ramsize in gd->ram_size */
  46         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  47                                 PHYS_SDRAM_1_SIZE);
  48         return 0;
  49 }
  50
  51 u32 get_board_rev(void)
  52 {
  53         u32 rev = get_cpu_rev();
  54         if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
  55                 rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
  56         return rev;
  57 }
  58
  59 #define UART_PAD_CTRL   (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH)
  60
  61 static void setup_iomux_uart(void)
  62 {
  63         static const iomux_v3_cfg_t uart_pads[] = {
  64                 MX51_PAD_UART1_RXD__UART1_RXD,
  65                 MX51_PAD_UART1_TXD__UART1_TXD,
  66                 NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL),
  67                 NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL),
  68         };
  69
  70         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  71 }
  72
  73 static void setup_iomux_fec(void)
  74 {
  75         static const iomux_v3_cfg_t fec_pads[] = {
  76                 NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO,
  77                                 PAD_CTL_HYS |
  78                                 PAD_CTL_PUS_22K_UP |
  79                                 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
  80                 MX51_PAD_EIM_EB3__FEC_RDATA1,
  81                 NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, PAD_CTL_HYS),
  82                 MX51_PAD_EIM_CS3__FEC_RDATA3,
  83                 MX51_PAD_NANDF_CS2__FEC_TX_ER,
  84                 MX51_PAD_EIM_CS5__FEC_CRS,
  85                 MX51_PAD_EIM_CS4__FEC_RX_ER,
  86                 /* PAD used on TS4800 */
  87                 MX51_PAD_DI2_PIN2__FEC_MDC,
  88                 MX51_PAD_DISP2_DAT14__FEC_RDAT0,
  89                 MX51_PAD_DISP2_DAT10__FEC_COL,
  90                 MX51_PAD_DISP2_DAT11__FEC_RXCLK,
  91                 MX51_PAD_DISP2_DAT15__FEC_TDAT0,
  92                 MX51_PAD_DISP2_DAT6__FEC_TDAT1,
  93                 MX51_PAD_DISP2_DAT7__FEC_TDAT2,
  94                 MX51_PAD_DISP2_DAT8__FEC_TDAT3,
  95                 MX51_PAD_DISP2_DAT9__FEC_TX_EN,
  96                 MX51_PAD_DISP2_DAT13__FEC_TX_CLK,
  97                 MX51_PAD_DISP2_DAT12__FEC_RX_DV,
  98         };
  99
 100         imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 101 }
 102
 103 #ifdef CONFIG_FSL_ESDHC_IMX
 104 int board_mmc_getcd(struct mmc *mmc)
 105 {
 106         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 107         int ret;
 108
 109         imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0,
 110                                                 NO_PAD_CTRL));
 111         gpio_direction_input(IMX_GPIO_NR(1, 0));
 112         imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
 113                                                 NO_PAD_CTRL));
 114         gpio_direction_input(IMX_GPIO_NR(1, 6));
 115
 116         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 117                 ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
 118         else
 119                 ret = !gpio_get_value(IMX_GPIO_NR(1, 6));
 120
 121         return ret;
 122 }
 123
 124 int board_mmc_init(bd_t *bis)
 125 {
 126         static const iomux_v3_cfg_t sd1_pads[] = {
 127                 NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
 128                         PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 129                 NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
 130                         PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 131                 NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
 132                         PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 133                 NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
 134                         PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 135                 NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
 136                         PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
 137                 NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
 138                         PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
 139                 NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
 140                 NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
 141         };
 142
 143         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 144
 145         imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
 146
 147         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 148 }
 149 #endif
 150
 151 int board_early_init_f(void)
 152 {
 153         setup_iomux_uart();
 154         setup_iomux_fec();
 155
 156         return 0;
 157 }
 158
 159 int board_init(void)
 160 {
 161         /* address of boot parameters */
 162         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 163
 164         return 0;
 165 }
 166
 167 /*
 168  * Read the MAC address from FEC's registers PALR PAUR.
 169  * User is supposed to configure these registers when MAC address is known
 170  * from another source (fuse), but on TS4800, MAC address is not fused and
 171  * the bootrom configure these registers on startup.
 172  */
 173 static int fec_get_mac_from_register(uint32_t base_addr)
 174 {
 175         unsigned char ethaddr[6];
 176         u32 reg_mac[2];
 177         int i;
 178
 179         reg_mac[0] = in_be32(base_addr + 0xE4);
 180         reg_mac[1] = in_be32(base_addr + 0xE8);
 181
 182         for(i = 0; i < 6; i++)
 183                 ethaddr[i] = (reg_mac[i / 4] >> ((i % 4) * 8)) & 0xFF;
 184
 185         if (is_valid_ethaddr(ethaddr)) {
 186                 eth_env_set_enetaddr("ethaddr", ethaddr);
 187                 return 0;
 188         }
 189
 190         return -1;
 191 }
 192
 193 #define TS4800_GPIO_FEC_PHY_RES         IMX_GPIO_NR(2, 14)
 194 int board_eth_init(bd_t *bd)
 195 {
 196         int dev_id = -1;
 197         int phy_id = 0xFF;
 198         uint32_t addr = IMX_FEC_BASE;
 199
 200         uint32_t base_mii;
 201         struct mii_dev *bus = NULL;
 202         struct phy_device *phydev = NULL;
 203         int ret;
 204
 205         /* reset FEC phy */
 206         imx_iomux_v3_setup_pad(MX51_PAD_EIM_A20__GPIO2_14);
 207         gpio_direction_output(TS4800_GPIO_FEC_PHY_RES, 0);
 208         mdelay(1);
 209         gpio_set_value(TS4800_GPIO_FEC_PHY_RES, 1);
 210         mdelay(1);
 211
 212         base_mii = addr;
 213         debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
 214         bus = fec_get_miibus(base_mii, dev_id);
 215         if (!bus)
 216                 return -ENOMEM;
 217
 218         phydev = phy_find_by_mask(bus, phy_id, PHY_INTERFACE_MODE_MII);
 219         if (!phydev) {
 220                 free(bus);
 221                 return -ENOMEM;
 222         }
 223
 224         if (fec_get_mac_from_register(addr))
 225                 printf("eth_init: failed to get MAC address\n");
 226
 227         ret = fec_probe(bd, dev_id, addr, bus, phydev);
 228         if (ret) {
 229                 free(phydev);
 230                 free(bus);
 231         }
 232
 233         return ret;
 234 }
 235
 236 /*
 237  * Do not overwrite the console
 238  * Use always serial for U-Boot console
 239  */
 240 int overwrite_console(void)
 241 {
 242         return 1;
 243 }
 244
 245 int checkboard(void)
 246 {
 247         puts("Board: TS4800\n");
 248
 249         return 0;
 250 }
 251
 252 void hw_watchdog_reset(void)
 253 {
 254         struct ts4800_wtd_regs *wtd = (struct ts4800_wtd_regs *) (TS4800_SYSCON_BASE + 0xE);
 255         /* feed the watchdog for another 10s */
 256         writew(0x2, &wtd->feed);
 257 }
 258
 259 void hw_watchdog_init(void)
 260 {
 261         return;
 262 }