1 // SPDX-License-Identifier: GPL-2.0+
14 #include <asm/mach-imx/iomux-v3.h>
15 #include <asm-generic/gpio.h>
16 #include <fsl_esdhc_imx.h>
18 #include <asm/arch/imx8mq_pins.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/mach-imx/gpio.h>
21 #include <asm/mach-imx/mxc_i2c.h>
22 #include <asm/arch/clock.h>
23 #include <linux/delay.h>
25 #include <power/pmic.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
31 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
33 static iomux_v3_cfg_t const wdog_pads[] = {
34 IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
37 static iomux_v3_cfg_t const uart_pads[] = {
38 IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
39 IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
42 int board_early_init_f(void)
44 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
46 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
49 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
56 int ddr_size = readl(M4_BOOTROM_BASE_ADDR);
59 gd->ram_size = 0x100000000;
60 else if (ddr_size == 0x3)
61 gd->ram_size = 0xc0000000;
62 else if (ddr_size == 0x2)
63 gd->ram_size = 0x80000000;
64 else if (ddr_size == 0x1)
65 gd->ram_size = 0x40000000;
67 printf("Unknown DDR type!!!\n");
69 /* rom_pointer[1] contains the size of TEE occupies */
71 gd->ram_size -= rom_pointer[1];
77 #define FEC_RST_PAD IMX_GPIO_NR(1, 9)
78 #define FEC_PWR_PAD IMX_GPIO_NR(1, 0)
79 static iomux_v3_cfg_t const fec1_pads[] = {
81 IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
83 IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL),
86 static void setup_iomux_fec(void)
88 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
90 gpio_request(IMX_GPIO_NR(1, 0), "fec1_pwr");
91 gpio_direction_output(IMX_GPIO_NR(1, 0), 1);
94 gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
95 gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
97 gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
100 static int setup_fec(void)
102 struct iomuxc_gpr_base_regs *gpr =
103 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
107 /* Use 125M anatop REF_CLK1 for ENET1, not from external */
108 clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
109 return set_clk_enet(ENET_125MHZ);
112 int board_phy_config(struct phy_device *phydev)
114 /* enable rgmii rxc skew and phy mode select to RGMII copper */
115 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
116 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
118 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
119 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
121 if (phydev->drv->config)
122 phydev->drv->config(phydev);
129 #ifdef CONFIG_FEC_MXC
136 int board_mmc_get_env_dev(int devno)
141 int board_late_init(void)
143 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
144 env_set("board_rev", "iMX8MQ");