1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013 Freescale Semiconductor, Inc.
4 * Copyright (C) 2014 O.S. Systems Software LTDA.
6 * Author: Fabio Estevam <festevam@gmail.com>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/crm_regs.h>
14 #include <asm/arch/iomux.h>
15 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/mx6-pins.h>
17 #include <asm/arch/sys_proto.h>
19 #include <asm/arch/mxc_hdmi.h>
20 #include <asm/mach-imx/video.h>
21 #include <asm/mach-imx/iomux-v3.h>
23 #include <linux/sizes.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
32 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
33 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
35 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
36 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
38 #define ETH_PHY_RESET IMX_GPIO_NR(1, 26)
39 #define LVDS0_EN IMX_GPIO_NR(2, 8)
40 #define LVDS0_BL_EN IMX_GPIO_NR(2, 9)
44 gd->ram_size = imx_ddr_size();
49 static iomux_v3_cfg_t const uart1_pads[] = {
50 IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
51 IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
54 static void setup_iomux_uart(void)
56 SETUP_IOMUX_PADS(uart1_pads);
59 static iomux_v3_cfg_t const lvds_pads[] = {
61 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
62 IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
63 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
64 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
65 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
68 static iomux_v3_cfg_t const enet_pads[] = {
69 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
70 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
71 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
72 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
73 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
74 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
75 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
76 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
77 MUX_PAD_CTRL(ENET_PAD_CTRL)),
78 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
79 MUX_PAD_CTRL(ENET_PAD_CTRL)),
80 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
81 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
82 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
83 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
84 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
85 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
86 /* AR8035 PHY Reset */
87 IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL)),
90 static void setup_iomux_enet(void)
92 SETUP_IOMUX_PADS(enet_pads);
94 /* Reset AR8031 PHY */
95 gpio_request(ETH_PHY_RESET, "enet_phy_reset");
96 gpio_direction_output(ETH_PHY_RESET, 0);
98 gpio_set_value(ETH_PHY_RESET, 1);
101 #if defined(CONFIG_VIDEO_IPUV3)
102 static iomux_v3_cfg_t const ft5x06_wvga_pads[] = {
103 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
104 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
105 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
106 IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
107 IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
108 IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
109 IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
110 IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
111 IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
112 IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
113 IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
114 IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
115 IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
116 IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
117 IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
118 IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
119 IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
120 IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
121 IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
122 IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
123 IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
124 IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
125 IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
126 IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18),
127 IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19),
128 IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20),
129 IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21),
130 IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22),
131 IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23),
132 IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
133 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
136 static void do_enable_hdmi(struct display_info_t const *dev)
138 imx_enable_hdmi_phy();
141 static void enable_lvds(struct display_info_t const *dev)
143 struct iomuxc *iomux = (struct iomuxc *)
146 /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
147 u32 reg = readl(&iomux->gpr[2]);
148 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
149 writel(reg, &iomux->gpr[2]);
151 /* Enable Backlight - use GPIO for Brightness adjustment */
152 SETUP_IOMUX_PAD(PAD_SD4_DAT1__GPIO2_IO09);
153 gpio_request(IMX_GPIO_NR(2, 9), "backlight_enable");
154 gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
156 gpio_request(IMX_GPIO_NR(2, 8), "brightness");
157 SETUP_IOMUX_PAD(PAD_SD4_DAT0__GPIO2_IO08);
158 gpio_direction_output(IMX_GPIO_NR(2, 8), 1);
161 static void enable_ft5x06_wvga(struct display_info_t const *dev)
163 SETUP_IOMUX_PADS(ft5x06_wvga_pads);
165 gpio_request(IMX_GPIO_NR(2, 10), "parallel_enable");
166 gpio_request(IMX_GPIO_NR(2, 11), "parallel_brightness");
167 gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
168 gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
171 struct display_info_t const displays[] = {{
174 .pixfmt = IPU_PIX_FMT_RGB24,
176 .enable = enable_ft5x06_wvga,
178 .name = "FT5x06-WVGA",
190 .vmode = FB_VMODE_NONINTERLACED
194 .pixfmt = IPU_PIX_FMT_RGB24,
196 .enable = enable_lvds,
210 .vmode = FB_VMODE_NONINTERLACED
214 .pixfmt = IPU_PIX_FMT_RGB24,
215 .detect = detect_hdmi,
216 .enable = do_enable_hdmi,
230 .vmode = FB_VMODE_NONINTERLACED
232 size_t display_count = ARRAY_SIZE(displays);
234 static void setup_display(void)
236 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
237 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
240 /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
241 SETUP_IOMUX_PADS(lvds_pads);
242 gpio_request(LVDS0_EN, "lvds0_enable");
243 gpio_request(LVDS0_BL_EN, "lvds0_bl_enable");
244 gpio_direction_output(LVDS0_EN, 1);
245 gpio_direction_output(LVDS0_BL_EN, 1);
250 reg = __raw_readl(&mxc_ccm->CCGR3);
251 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
252 writel(reg, &mxc_ccm->CCGR3);
254 /* set LDB0, LDB1 clk select to 011/011 */
255 reg = readl(&mxc_ccm->cs2cdr);
256 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
257 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
258 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
259 | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
260 writel(reg, &mxc_ccm->cs2cdr);
262 reg = readl(&mxc_ccm->cscmr2);
263 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
264 writel(reg, &mxc_ccm->cscmr2);
266 reg = readl(&mxc_ccm->chsccdr);
267 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
268 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
269 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
270 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
271 writel(reg, &mxc_ccm->chsccdr);
273 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
274 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
275 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
276 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
277 | IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT
278 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
279 | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
280 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0
281 | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
282 writel(reg, &iomux->gpr[2]);
283 reg = readl(&iomux->gpr[3]);
285 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
286 | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
287 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
288 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
290 writel(reg, &iomux->gpr[3]);
292 #endif /* CONFIG_VIDEO_IPUV3 */
294 int board_early_init_f(void)
298 #if defined(CONFIG_VIDEO_IPUV3)
305 int board_eth_init(bd_t *bis)
309 return cpu_eth_init(bis);
312 int board_phy_config(struct phy_device *phydev)
316 /* To enable AR8035 ouput a 125MHz clk from CLK_25M */
317 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
318 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
319 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
321 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
324 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
326 /* introduce tx clock delay */
327 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
328 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
330 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
332 if (phydev->drv->config)
333 phydev->drv->config(phydev);
338 int overwrite_console(void)
343 int board_late_init(void)
346 env_set("board_rev", "MX6Q");
348 env_set("board_rev", "MX6DL");
355 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
362 puts("Board: PICO-IMX6\n");