1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
4 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
16 #include <asm/cache.h>
17 #include <linux/printk.h>
18 #include <linux/kernel.h>
20 #include <asm/arcregs.h>
21 #include <fdt_support.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 #define ALL_CPU_MASK GENMASK(NR_CPUS - 1, 0)
32 #define MASTER_CPU_ID 0
33 #define APERTURE_SHIFT 28
35 #define SLAVE_CPU_READY 0x12345678
36 #define BOOTSTAGE_1 1 /* after SP, FP setup, before HW init */
37 #define BOOTSTAGE_2 2 /* after HW init, before self halt */
38 #define BOOTSTAGE_3 3 /* after self halt */
39 #define BOOTSTAGE_4 4 /* before app launch */
40 #define BOOTSTAGE_5 5 /* after app launch, unreachable */
42 #define RESET_VECTOR_ADDR 0x0
44 #define CREG_BASE (ARC_PERIPHERAL_BASE + 0x1000)
45 #define CREG_CPU_START (CREG_BASE + 0x400)
46 #define CREG_CPU_START_MASK 0xF
47 #define CREG_CPU_START_POL BIT(4)
49 #define CREG_CORE_BOOT_IMAGE GENMASK(5, 4)
51 #define CREG_CPU_0_ENTRY (CREG_BASE + 0x404)
53 #define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000)
54 #define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108)
55 #define SDIO_UHS_REG_EXT_DIV_2 (2 << 30)
57 /* Uncached access macros */
58 #define arc_read_uncached_32(ptr) \
61 __asm__ __volatile__( \
62 " ld.di %0, [%1] \n" \
68 #define arc_write_uncached_32(ptr, data)\
70 __asm__ __volatile__( \
71 " st.di %0, [%1] \n" \
73 : "r"(data), "r"(ptr)); \
76 struct hsdk_env_core_ctl {
77 u32_env entry[NR_CPUS];
78 u32_env iccm[NR_CPUS];
79 u32_env dccm[NR_CPUS];
82 struct hsdk_env_common_ctl {
97 * Uncached cross-cpu structure. All CPUs must access to this structure fields
98 * only with arc_read_uncached_32() / arc_write_uncached_32() accessors (which
99 * implement ld.di / st.di instructions). Simultaneous cached and uncached
100 * access to this area will lead to data loss.
101 * We flush all data caches in board_early_init_r() as we don't want to have
102 * any dirty line in L1d$ or SL$ in this area.
104 struct hsdk_cross_cpu {
105 /* slave CPU ready flag */
107 /* address of the area, which can be used for stack by slave CPU */
109 /* slave CPU status - bootstage number */
113 * Slave CPU data - it is copy of corresponding fields in
114 * hsdk_env_core_ctl and hsdk_env_common_ctl structures which are
115 * required for slave CPUs initialization.
116 * This fields can be populated by copying from hsdk_env_core_ctl
117 * and hsdk_env_common_ctl structures with sync_cross_cpu_data()
128 u8 cache_padding[ARCH_DMA_MINALIGN];
129 } __aligned(ARCH_DMA_MINALIGN);
131 /* Place for slave CPUs temporary stack */
132 static u32 slave_stack[256 * NR_CPUS] __aligned(ARCH_DMA_MINALIGN);
134 static struct hsdk_env_common_ctl env_common = {};
135 static struct hsdk_env_core_ctl env_core = {};
136 static struct hsdk_cross_cpu cross_cpu_data;
138 static const struct env_map_common env_map_common[] = {
139 { "core_mask", ENV_HEX, true, 0x1, 0xF, &env_common.core_mask },
140 { "non_volatile_limit", ENV_HEX, true, 0, 0xF, &env_common.nvlim },
141 { "icache_ena", ENV_HEX, true, 0, 1, &env_common.icache },
142 { "dcache_ena", ENV_HEX, true, 0, 1, &env_common.dcache },
143 #if defined(CONFIG_BOARD_HSDK_4XD)
144 { "l2_cache_ena", ENV_HEX, true, 0, 1, &env_common.l2_cache },
145 { "csm_location", ENV_HEX, true, 0, NO_CCM, &env_common.csm_location },
146 { "haps_apb_location", ENV_HEX, true, 0, 1, &env_common.haps_apb },
147 #endif /* CONFIG_BOARD_HSDK_4XD */
151 static const struct env_map_common env_map_clock[] = {
152 { "cpu_freq", ENV_DEC, false, 100, 1000, &env_common.cpu_freq },
153 { "axi_freq", ENV_DEC, false, 200, 800, &env_common.axi_freq },
154 { "tun_freq", ENV_DEC, false, 0, 150, &env_common.tun_freq },
158 static const struct env_map_percpu env_map_core[] = {
159 { "core_iccm", ENV_HEX, true, {NO_CCM, 0, NO_CCM, 0}, {NO_CCM, 0xF, NO_CCM, 0xF}, &env_core.iccm },
160 { "core_dccm", ENV_HEX, true, {NO_CCM, 0, NO_CCM, 0}, {NO_CCM, 0xF, NO_CCM, 0xF}, &env_core.dccm },
164 static const struct env_map_common env_map_mask[] = {
165 { "core_mask", ENV_HEX, false, 0x1, 0xF, &env_common.core_mask },
169 static const struct env_map_percpu env_map_go[] = {
170 { "core_entry", ENV_HEX, true, {0, 0, 0, 0}, {U32_MAX, U32_MAX, U32_MAX, U32_MAX}, &env_core.entry },
180 static inline enum board_type get_board_type_runtime(void)
182 u32 arc_id = read_aux_reg(ARC_AUX_IDENTITY) & 0xFF;
186 else if (arc_id == 0x54)
187 return T_BOARD_HSDK_4XD;
192 static inline enum board_type get_board_type_config(void)
194 if (IS_ENABLED(CONFIG_BOARD_HSDK))
196 else if (IS_ENABLED(CONFIG_BOARD_HSDK_4XD))
197 return T_BOARD_HSDK_4XD;
202 static bool is_board_match_runtime(enum board_type type_req)
204 return get_board_type_runtime() == type_req;
207 static bool is_board_match_config(enum board_type type_req)
209 return get_board_type_config() == type_req;
212 static const char * board_name(enum board_type type)
216 return "ARC HS Development Kit";
217 case T_BOARD_HSDK_4XD:
218 return "ARC HS4x/HS4xD Development Kit";
224 static bool board_mismatch(void)
226 return get_board_type_config() != get_board_type_runtime();
229 static void sync_cross_cpu_data(void)
233 for (u32 i = 0; i < NR_CPUS; i++) {
234 value = env_core.entry[i].val;
235 arc_write_uncached_32(&cross_cpu_data.entry[i], value);
238 for (u32 i = 0; i < NR_CPUS; i++) {
239 value = env_core.iccm[i].val;
240 arc_write_uncached_32(&cross_cpu_data.iccm[i], value);
243 for (u32 i = 0; i < NR_CPUS; i++) {
244 value = env_core.dccm[i].val;
245 arc_write_uncached_32(&cross_cpu_data.dccm[i], value);
248 value = env_common.core_mask.val;
249 arc_write_uncached_32(&cross_cpu_data.core_mask, value);
251 value = env_common.icache.val;
252 arc_write_uncached_32(&cross_cpu_data.icache, value);
254 value = env_common.dcache.val;
255 arc_write_uncached_32(&cross_cpu_data.dcache, value);
258 /* Can be used only on master CPU */
259 static bool is_cpu_used(u32 cpu_id)
261 return !!(env_common.core_mask.val & BIT(cpu_id));
264 /* TODO: add ICCM BCR and DCCM BCR runtime check */
265 static void init_slave_cpu_func(u32 core)
269 /* Remap ICCM to another memory region if it exists */
270 val = arc_read_uncached_32(&cross_cpu_data.iccm[core]);
272 write_aux_reg(ARC_AUX_ICCM_BASE, val << APERTURE_SHIFT);
274 /* Remap DCCM to another memory region if it exists */
275 val = arc_read_uncached_32(&cross_cpu_data.dccm[core]);
277 write_aux_reg(ARC_AUX_DCCM_BASE, val << APERTURE_SHIFT);
279 if (arc_read_uncached_32(&cross_cpu_data.icache))
284 if (arc_read_uncached_32(&cross_cpu_data.dcache))
290 static void init_cluster_nvlim(void)
292 u32 val = env_common.nvlim.val << APERTURE_SHIFT;
295 write_aux_reg(ARC_AUX_NON_VOLATILE_LIMIT, val);
296 /* AUX_AUX_CACHE_LIMIT reg is missing starting from HS48 */
297 if (is_board_match_runtime(T_BOARD_HSDK))
298 write_aux_reg(AUX_AUX_CACHE_LIMIT, val);
299 flush_n_invalidate_dcache_all();
302 static void init_cluster_slc(void)
304 /* ARC HS38 doesn't support SLC disabling */
305 if (!is_board_match_config(T_BOARD_HSDK_4XD))
308 if (env_common.l2_cache.val)
314 #define CREG_CSM_BASE (CREG_BASE + 0x210)
316 static void init_cluster_csm(void)
318 /* ARC HS38 in HSDK SoC doesn't include CSM */
319 if (!is_board_match_config(T_BOARD_HSDK_4XD))
322 if (env_common.csm_location.val == NO_CCM) {
323 write_aux_reg(ARC_AUX_CSM_ENABLE, 0);
326 * CSM base address is 256kByte aligned but we allow to map
327 * CSM only to aperture start (256MByte aligned)
328 * The field in CREG_CSM_BASE is in 17:2 bits itself so we need
331 u32 csm_base = (env_common.csm_location.val * SZ_1K) << 2;
333 write_aux_reg(ARC_AUX_CSM_ENABLE, 1);
334 writel(csm_base, (void __iomem *)CREG_CSM_BASE);
338 static void init_master_icache(void)
340 if (icache_status()) {
341 /* I$ is enabled - we need to disable it */
342 if (!env_common.icache.val)
345 /* I$ is disabled - we need to enable it */
346 if (env_common.icache.val) {
349 /* invalidate I$ right after enable */
350 invalidate_icache_all();
355 static void init_master_dcache(void)
357 if (dcache_status()) {
358 /* D$ is enabled - we need to disable it */
359 if (!env_common.dcache.val)
362 /* D$ is disabled - we need to enable it */
363 if (env_common.dcache.val)
366 /* TODO: probably we need ti invalidate D$ right after enable */
370 static int cleanup_before_go(void)
372 disable_interrupts();
373 sync_n_cleanup_cache_all();
378 void slave_cpu_set_boot_addr(u32 addr)
380 /* All cores have reset vector pointing to 0 */
381 writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
383 /* Make sure other cores see written value in memory */
384 sync_n_cleanup_cache_all();
387 static inline void halt_this_cpu(void)
389 __builtin_arc_flag(1);
392 static u32 get_masked_cpu_ctart_reg(void)
394 int cmd = readl((void __iomem *)CREG_CPU_START);
397 * Quirk for HSDK-4xD - due to HW issues HSDK can use any pulse polarity
398 * and HSDK-4xD require active low polarity of cpu_start pulse.
400 cmd &= ~CREG_CPU_START_POL;
402 cmd &= ~CREG_CPU_START_MASK;
407 static void smp_kick_cpu_x(u32 cpu_id)
411 if (cpu_id > NR_CPUS)
414 cmd = get_masked_cpu_ctart_reg();
415 cmd |= (1 << cpu_id);
416 writel(cmd, (void __iomem *)CREG_CPU_START);
419 static u32 prepare_cpu_ctart_reg(void)
421 return get_masked_cpu_ctart_reg() | env_common.core_mask.val;
424 /* slave CPU entry for configuration */
425 __attribute__((naked, noreturn, flatten)) noinline void hsdk_core_init_f(void)
427 __asm__ __volatile__(
432 : "r" (&cross_cpu_data.stack_ptr));
434 invalidate_icache_all();
436 arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_1);
437 init_slave_cpu_func(CPU_ID_GET());
439 arc_write_uncached_32(&cross_cpu_data.ready_flag, SLAVE_CPU_READY);
440 arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_2);
442 /* Halt the processor until the master kick us again */
446 * 3 NOPs after FLAG 1 instruction are no longer required for ARCv2
447 * cores but we leave them for gebug purposes.
453 arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_3);
455 /* get the updated entry - invalidate i$ */
456 invalidate_icache_all();
458 arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_4);
460 /* Run our program */
461 ((void (*)(void))(arc_read_uncached_32(&cross_cpu_data.entry[CPU_ID_GET()])))();
463 /* This bootstage is unreachable as we don't return from app we launch */
464 arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_5);
466 /* Something went terribly wrong */
471 static void clear_cross_cpu_data(void)
473 arc_write_uncached_32(&cross_cpu_data.ready_flag, 0);
474 arc_write_uncached_32(&cross_cpu_data.stack_ptr, 0);
476 for (u32 i = 0; i < NR_CPUS; i++)
477 arc_write_uncached_32(&cross_cpu_data.status[i], 0);
480 static noinline void do_init_slave_cpu(u32 cpu_id)
482 /* attempts number for check clave CPU ready_flag */
484 u32 stack_ptr = (u32)(slave_stack + (64 * cpu_id));
486 if (cpu_id >= NR_CPUS)
489 arc_write_uncached_32(&cross_cpu_data.ready_flag, 0);
491 /* Use global unique place for each slave cpu stack */
492 arc_write_uncached_32(&cross_cpu_data.stack_ptr, stack_ptr);
494 debug("CPU %u: stack pool base: %p\n", cpu_id, slave_stack);
495 debug("CPU %u: current slave stack base: %x\n", cpu_id, stack_ptr);
496 slave_cpu_set_boot_addr((u32)hsdk_core_init_f);
498 smp_kick_cpu_x(cpu_id);
500 debug("CPU %u: cross-cpu flag: %x [before timeout]\n", cpu_id,
501 arc_read_uncached_32(&cross_cpu_data.ready_flag));
503 while (!arc_read_uncached_32(&cross_cpu_data.ready_flag) && attempts--)
506 /* Just to be sure that slave cpu is halted after it set ready_flag */
510 * Only print error here if we reach timeout as there is no option to
511 * halt slave cpu (or check that slave cpu is halted)
514 pr_err("CPU %u is not responding after init!\n", cpu_id);
516 /* Check current stage of slave cpu */
517 if (arc_read_uncached_32(&cross_cpu_data.status[cpu_id]) != BOOTSTAGE_2)
518 pr_err("CPU %u status is unexpected: %d\n", cpu_id,
519 arc_read_uncached_32(&cross_cpu_data.status[cpu_id]));
521 debug("CPU %u: cross-cpu flag: %x [after timeout]\n", cpu_id,
522 arc_read_uncached_32(&cross_cpu_data.ready_flag));
523 debug("CPU %u: status: %d [after timeout]\n", cpu_id,
524 arc_read_uncached_32(&cross_cpu_data.status[cpu_id]));
527 static void do_init_slave_cpus(void)
529 clear_cross_cpu_data();
530 sync_cross_cpu_data();
532 debug("cross_cpu_data location: %#x\n", (u32)&cross_cpu_data);
534 for (u32 i = MASTER_CPU_ID + 1; i < NR_CPUS; i++)
536 do_init_slave_cpu(i);
539 static void do_init_master_cpu(void)
542 * Setup master caches even if master isn't used as we want to use
543 * same cache configuration on all running CPUs
545 init_master_icache();
546 init_master_dcache();
549 enum hsdk_axi_masters {
567 * m master AXI_M_m_SLV0 AXI_M_m_SLV1 AXI_M_m_OFFSET0 AXI_M_m_OFFSET1
568 * 0 HS (CBU) 0x11111111 0x63111111 0xFEDCBA98 0x0E543210
569 * 1 HS (RTT) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
570 * 2 AXI Tunnel 0x88888888 0x88888888 0xFEDCBA98 0x76543210
571 * 3 HDMI-VIDEO 0x77777777 0x77777777 0xFEDCBA98 0x76543210
572 * 4 HDMI-ADUIO 0x77777777 0x77777777 0xFEDCBA98 0x76543210
573 * 5 USB-HOST 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
574 * 6 ETHERNET 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
575 * 7 SDIO 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
576 * 8 GPU 0x77777777 0x77777777 0xFEDCBA98 0x76543210
577 * 9 DMAC (port #1) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
578 * 10 DMAC (port #2) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
579 * 11 DVFS 0x00000000 0x60000000 0x00000000 0x00000000
581 * Please read ARC HS Development IC Specification, section 17.2 for more
582 * information about apertures configuration.
583 * NOTE: we intentionally modify default settings in U-boot. Default settings
584 * are specified in "Table 111 CREG Address Decoder register reset values".
587 #define CREG_AXI_M_SLV0(m) ((void __iomem *)(CREG_BASE + 0x020 * (m)))
588 #define CREG_AXI_M_SLV1(m) ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x004))
589 #define CREG_AXI_M_OFT0(m) ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x008))
590 #define CREG_AXI_M_OFT1(m) ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x00C))
591 #define CREG_AXI_M_UPDT(m) ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x014))
593 #define CREG_AXI_M_HS_CORE_BOOT ((void __iomem *)(CREG_BASE + 0x010))
595 #define CREG_PAE ((void __iomem *)(CREG_BASE + 0x180))
596 #define CREG_PAE_UPDT ((void __iomem *)(CREG_BASE + 0x194))
598 void init_memory_bridge(void)
603 * M_HS_CORE has one unic register - BOOT.
604 * We need to clean boot mirror (BOOT[1:0]) bits in them.
606 reg = readl(CREG_AXI_M_HS_CORE_BOOT) & (~0x3);
607 writel(reg, CREG_AXI_M_HS_CORE_BOOT);
608 writel(0x11111111, CREG_AXI_M_SLV0(M_HS_CORE));
609 writel(0x63111111, CREG_AXI_M_SLV1(M_HS_CORE));
610 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_CORE));
611 writel(0x0E543210, CREG_AXI_M_OFT1(M_HS_CORE));
612 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_CORE));
614 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT));
615 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT));
616 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT));
617 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT));
618 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT));
620 writel(0x88888888, CREG_AXI_M_SLV0(M_AXI_TUN));
621 writel(0x88888888, CREG_AXI_M_SLV1(M_AXI_TUN));
622 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_AXI_TUN));
623 writel(0x76543210, CREG_AXI_M_OFT1(M_AXI_TUN));
624 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_AXI_TUN));
626 writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_VIDEO));
627 writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_VIDEO));
628 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_VIDEO));
629 writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_VIDEO));
630 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_VIDEO));
632 writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_AUDIO));
633 writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_AUDIO));
634 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_AUDIO));
635 writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_AUDIO));
636 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_AUDIO));
638 writel(0x77777777, CREG_AXI_M_SLV0(M_USB_HOST));
639 writel(0x77999999, CREG_AXI_M_SLV1(M_USB_HOST));
640 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_USB_HOST));
641 writel(0x76DCBA98, CREG_AXI_M_OFT1(M_USB_HOST));
642 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_USB_HOST));
644 writel(0x77777777, CREG_AXI_M_SLV0(M_ETHERNET));
645 writel(0x77999999, CREG_AXI_M_SLV1(M_ETHERNET));
646 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_ETHERNET));
647 writel(0x76DCBA98, CREG_AXI_M_OFT1(M_ETHERNET));
648 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_ETHERNET));
650 writel(0x77777777, CREG_AXI_M_SLV0(M_SDIO));
651 writel(0x77999999, CREG_AXI_M_SLV1(M_SDIO));
652 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_SDIO));
653 writel(0x76DCBA98, CREG_AXI_M_OFT1(M_SDIO));
654 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO));
656 writel(0x77777777, CREG_AXI_M_SLV0(M_GPU));
657 writel(0x77777777, CREG_AXI_M_SLV1(M_GPU));
658 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_GPU));
659 writel(0x76543210, CREG_AXI_M_OFT1(M_GPU));
660 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_GPU));
662 writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0));
663 writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_0));
664 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0));
665 writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_0));
666 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0));
668 writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1));
669 writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_1));
670 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1));
671 writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_1));
672 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1));
674 writel(0x00000000, CREG_AXI_M_SLV0(M_DVFS));
675 writel(0x60000000, CREG_AXI_M_SLV1(M_DVFS));
676 writel(0x00000000, CREG_AXI_M_OFT0(M_DVFS));
677 writel(0x00000000, CREG_AXI_M_OFT1(M_DVFS));
678 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DVFS));
680 writel(0x00000000, CREG_PAE);
681 writel(UPDATE_VAL, CREG_PAE_UPDT);
685 * For HSDK-4xD we do additional AXI bridge tweaking in hsdk_init command:
686 * - we shrink IOC region.
687 * - we configure HS CORE SLV1 aperture depending on haps_apb_location
688 * environment variable.
690 * As we've already configured AXI bridge in init_memory_bridge we don't
691 * do full configuration here but reconfigure changed part.
693 * m master AXI_M_m_SLV0 AXI_M_m_SLV1 AXI_M_m_OFFSET0 AXI_M_m_OFFSET1
694 * 0 HS (CBU) 0x11111111 0x63111111 0xFEDCBA98 0x0E543210 [haps_apb_location = 0]
695 * 0 HS (CBU) 0x11111111 0x61111111 0xFEDCBA98 0x06543210 [haps_apb_location = 1]
696 * 1 HS (RTT) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
697 * 2 AXI Tunnel 0x88888888 0x88888888 0xFEDCBA98 0x76543210
698 * 3 HDMI-VIDEO 0x77777777 0x77777777 0xFEDCBA98 0x76543210
699 * 4 HDMI-ADUIO 0x77777777 0x77777777 0xFEDCBA98 0x76543210
700 * 5 USB-HOST 0x77777777 0x77779999 0xFEDCBA98 0x7654BA98
701 * 6 ETHERNET 0x77777777 0x77779999 0xFEDCBA98 0x7654BA98
702 * 7 SDIO 0x77777777 0x77779999 0xFEDCBA98 0x7654BA98
703 * 8 GPU 0x77777777 0x77777777 0xFEDCBA98 0x76543210
704 * 9 DMAC (port #1) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
705 * 10 DMAC (port #2) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
706 * 11 DVFS 0x00000000 0x60000000 0x00000000 0x00000000
708 void tweak_memory_bridge_cfg(void)
711 * Only HSDK-4xD requre additional AXI bridge tweaking depending on
712 * haps_apb_location environment variable
714 if (!is_board_match_config(T_BOARD_HSDK_4XD))
717 if (env_common.haps_apb.val) {
718 writel(0x61111111, CREG_AXI_M_SLV1(M_HS_CORE));
719 writel(0x06543210, CREG_AXI_M_OFT1(M_HS_CORE));
721 writel(0x63111111, CREG_AXI_M_SLV1(M_HS_CORE));
722 writel(0x0E543210, CREG_AXI_M_OFT1(M_HS_CORE));
724 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_CORE));
726 writel(0x77779999, CREG_AXI_M_SLV1(M_USB_HOST));
727 writel(0x7654BA98, CREG_AXI_M_OFT1(M_USB_HOST));
728 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_USB_HOST));
730 writel(0x77779999, CREG_AXI_M_SLV1(M_ETHERNET));;
731 writel(0x7654BA98, CREG_AXI_M_OFT1(M_ETHERNET));
732 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_ETHERNET));
734 writel(0x77779999, CREG_AXI_M_SLV1(M_SDIO));
735 writel(0x7654BA98, CREG_AXI_M_OFT1(M_SDIO));
736 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO));
739 static void setup_clocks(void)
743 /* Setup CPU clock */
744 if (env_common.cpu_freq.set) {
745 rate = env_common.cpu_freq.val;
746 soc_clk_ctl("cpu-clk", &rate, CLK_ON | CLK_SET | CLK_MHZ);
749 /* Setup TUN clock */
750 if (env_common.tun_freq.set) {
751 rate = env_common.tun_freq.val;
753 soc_clk_ctl("tun-clk", &rate, CLK_ON | CLK_SET | CLK_MHZ);
755 soc_clk_ctl("tun-clk", NULL, CLK_OFF);
758 if (env_common.axi_freq.set) {
759 rate = env_common.axi_freq.val;
760 soc_clk_ctl("axi-clk", &rate, CLK_SET | CLK_ON | CLK_MHZ);
764 static void do_init_cluster(void)
767 * A multi-core ARC HS configuration always includes only one
768 * ARC_AUX_NON_VOLATILE_LIMIT register, which is shared by all the
771 init_cluster_nvlim();
774 tweak_memory_bridge_cfg();
777 static int check_master_cpu_id(void)
779 if (CPU_ID_GET() == MASTER_CPU_ID)
782 pr_err("u-boot runs on non-master cpu with id: %lu\n", CPU_ID_GET());
787 static noinline int prepare_cpus(void)
791 ret = check_master_cpu_id();
795 ret = envs_process_and_validate(env_map_common, env_map_core, is_cpu_used);
799 printf("CPU start mask is %#x\n", env_common.core_mask.val);
801 do_init_slave_cpus();
802 do_init_master_cpu();
808 static int hsdk_go_run(u32 cpu_start_reg)
810 /* Cleanup caches, disable interrupts */
813 if (env_common.halt_on_boot)
817 * 3 NOPs after FLAG 1 instruction are no longer required for ARCv2
818 * cores but we leave them for gebug purposes.
824 /* Kick chosen slave CPUs */
825 writel(cpu_start_reg, (void __iomem *)CREG_CPU_START);
827 if (is_cpu_used(MASTER_CPU_ID))
828 ((void (*)(void))(env_core.entry[MASTER_CPU_ID].val))();
832 pr_err("u-boot still runs on cpu [%ld]\n", CPU_ID_GET());
835 * We will never return after executing our program if master cpu used
836 * otherwise halt master cpu manually.
844 int board_prep_linux(bootm_headers_t *images)
849 ret = envs_read_validate_common(env_map_mask);
853 /* Rollback to default values */
854 if (!env_common.core_mask.set) {
855 env_common.core_mask.val = ALL_CPU_MASK;
856 env_common.core_mask.set = true;
859 printf("CPU start mask is %#x\n", env_common.core_mask.val);
861 if (!is_cpu_used(MASTER_CPU_ID))
862 pr_err("ERR: try to launch linux with CPU[0] disabled! It doesn't work for ARC.\n");
865 * If we want to launch linux on all CPUs we don't need to patch
866 * linux DTB as it is default configuration
868 if (env_common.core_mask.val == ALL_CPU_MASK)
871 if (!IMAGE_ENABLE_OF_LIBFDT || !images->ft_len) {
872 pr_err("WARN: core_mask setup will work properly only with external DTB!\n");
876 /* patch '/possible-cpus' property according to cpu mask */
877 ofst = fdt_path_offset(images->ft_addr, "/");
878 sprintf(mask, "%s%s%s%s",
879 is_cpu_used(0) ? "0," : "",
880 is_cpu_used(1) ? "1," : "",
881 is_cpu_used(2) ? "2," : "",
882 is_cpu_used(3) ? "3," : "");
883 ret = fdt_setprop_string(images->ft_addr, ofst, "possible-cpus", mask);
885 * If we failed to patch '/possible-cpus' property we don't need break
886 * linux loading process: kernel will handle it but linux will print
887 * warning like "Timeout: CPU1 FAILED to comeup !!!".
888 * So warn here about error, but return 0 like no error had occurred.
891 pr_err("WARN: failed to patch '/possible-cpus' property, ret=%d\n",
897 void board_jump_and_run(ulong entry, int zero, int arch, uint params)
899 void (*kernel_entry)(int zero, int arch, uint params);
902 kernel_entry = (void (*)(int, int, uint))entry;
904 /* Prepare CREG_CPU_START for kicking chosen CPUs */
905 cpu_start_reg = prepare_cpu_ctart_reg();
907 /* In case of run without hsdk_init */
908 slave_cpu_set_boot_addr(entry);
910 /* In case of run with hsdk_init */
911 for (u32 i = 0; i < NR_CPUS; i++) {
912 env_core.entry[i].val = entry;
913 env_core.entry[i].set = true;
915 /* sync cross_cpu struct as we updated core-entry variables */
916 sync_cross_cpu_data();
918 /* Kick chosen slave CPUs */
919 writel(cpu_start_reg, (void __iomem *)CREG_CPU_START);
922 kernel_entry(zero, arch, params);
925 static int hsdk_go_prepare_and_run(void)
927 /* Prepare CREG_CPU_START for kicking chosen CPUs */
928 u32 reg = prepare_cpu_ctart_reg();
930 if (env_common.halt_on_boot)
931 printf("CPU will halt before application start, start application with debugger.\n");
933 return hsdk_go_run(reg);
936 static int do_hsdk_go(struct cmd_tbl *cmdtp, int flag, int argc,
941 if (board_mismatch()) {
942 printf("ERR: U-boot is not configured for this board!\n");
943 return CMD_RET_FAILURE;
947 * Check for 'halt' parameter. 'halt' = enter halt-mode just before
948 * starting the application; can be used for debug.
951 env_common.halt_on_boot = !strcmp(argv[1], "halt");
952 if (!env_common.halt_on_boot) {
953 pr_err("Unrecognised parameter: \'%s\'\n", argv[1]);
954 return CMD_RET_FAILURE;
958 ret = check_master_cpu_id();
962 ret = envs_process_and_validate(env_map_mask, env_map_go, is_cpu_used);
966 /* sync cross_cpu struct as we updated core-entry variables */
967 sync_cross_cpu_data();
969 ret = hsdk_go_prepare_and_run();
971 return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
975 hsdk_go, 3, 0, do_hsdk_go,
976 "Synopsys HSDK specific command",
977 " - Boot stand-alone application on HSDK\n"
978 "hsdk_go halt - Boot stand-alone application on HSDK, halt CPU just before application run\n"
982 * We may simply use static variable here to store init status, but we also want
983 * to avoid the situation when we reload U-boot via MDB after previous
984 * init is done but HW reset (board reset) isn't done. So let's store the
985 * init status in any unused register (i.e CREG_CPU_0_ENTRY) so status will
986 * survive after U-boot is reloaded via MDB.
988 #define INIT_MARKER_REGISTER ((void __iomem *)CREG_CPU_0_ENTRY)
989 /* must be equal to INIT_MARKER_REGISTER reset value */
990 #define INIT_MARKER_PENDING 0
992 static bool init_marker_get(void)
994 return readl(INIT_MARKER_REGISTER) != INIT_MARKER_PENDING;
997 static void init_mark_done(void)
999 writel(~INIT_MARKER_PENDING, INIT_MARKER_REGISTER);
1002 static int do_hsdk_init(struct cmd_tbl *cmdtp, int flag, int argc,
1007 if (board_mismatch()) {
1008 printf("ERR: U-boot is not configured for this board!\n");
1009 return CMD_RET_FAILURE;
1012 /* hsdk_init can be run only once */
1013 if (init_marker_get()) {
1014 printf("HSDK HW is already initialized! Please reset the board if you want to change the configuration.\n");
1015 return CMD_RET_FAILURE;
1018 ret = prepare_cpus();
1022 return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
1026 hsdk_init, 1, 0, do_hsdk_init,
1027 "Synopsys HSDK specific command",
1031 static int do_hsdk_clock_set(struct cmd_tbl *cmdtp, int flag, int argc,
1036 /* Strip off leading subcommand argument */
1040 envs_cleanup_common(env_map_clock);
1043 printf("Set clocks to values specified in environment\n");
1044 ret = envs_read_common(env_map_clock);
1046 printf("Set clocks to values specified in args\n");
1047 ret = args_envs_enumerate(env_map_clock, 2, argc, argv);
1051 return CMD_RET_FAILURE;
1053 ret = envs_validate_common(env_map_clock);
1055 return CMD_RET_FAILURE;
1057 /* Setup clock tree HW */
1060 return CMD_RET_SUCCESS;
1063 static int do_hsdk_clock_get(struct cmd_tbl *cmdtp, int flag, int argc,
1068 if (soc_clk_ctl("cpu-clk", &rate, CLK_GET | CLK_MHZ))
1069 return CMD_RET_FAILURE;
1071 if (env_set_ulong("cpu_freq", rate))
1072 return CMD_RET_FAILURE;
1074 if (soc_clk_ctl("tun-clk", &rate, CLK_GET | CLK_MHZ))
1075 return CMD_RET_FAILURE;
1077 if (env_set_ulong("tun_freq", rate))
1078 return CMD_RET_FAILURE;
1080 if (soc_clk_ctl("axi-clk", &rate, CLK_GET | CLK_MHZ))
1081 return CMD_RET_FAILURE;
1083 if (env_set_ulong("axi_freq", rate))
1084 return CMD_RET_FAILURE;
1086 printf("Clock values are saved to environment\n");
1088 return CMD_RET_SUCCESS;
1091 static int do_hsdk_clock_print(struct cmd_tbl *cmdtp, int flag, int argc,
1095 soc_clk_ctl("cpu-clk", NULL, CLK_PRINT | CLK_MHZ);
1096 soc_clk_ctl("tun-clk", NULL, CLK_PRINT | CLK_MHZ);
1097 soc_clk_ctl("axi-clk", NULL, CLK_PRINT | CLK_MHZ);
1098 soc_clk_ctl("ddr-clk", NULL, CLK_PRINT | CLK_MHZ);
1100 return CMD_RET_SUCCESS;
1103 static int do_hsdk_clock_print_all(struct cmd_tbl *cmdtp, int flag, int argc,
1107 * NOTE: as of today we don't use some peripherals like HDMI / EBI
1108 * so we don't want to print their clocks ("hdmi-sys-clk", "hdmi-pll",
1109 * "hdmi-clk", "ebi-clk"). Nevertheless their clock subsystems is fully
1110 * functional and we can print their clocks if it is required
1113 /* CPU clock domain */
1114 soc_clk_ctl("cpu-pll", NULL, CLK_PRINT | CLK_MHZ);
1115 soc_clk_ctl("cpu-clk", NULL, CLK_PRINT | CLK_MHZ);
1118 /* SYS clock domain */
1119 soc_clk_ctl("sys-pll", NULL, CLK_PRINT | CLK_MHZ);
1120 soc_clk_ctl("apb-clk", NULL, CLK_PRINT | CLK_MHZ);
1121 soc_clk_ctl("axi-clk", NULL, CLK_PRINT | CLK_MHZ);
1122 soc_clk_ctl("eth-clk", NULL, CLK_PRINT | CLK_MHZ);
1123 soc_clk_ctl("usb-clk", NULL, CLK_PRINT | CLK_MHZ);
1124 soc_clk_ctl("sdio-clk", NULL, CLK_PRINT | CLK_MHZ);
1125 if (is_board_match_runtime(T_BOARD_HSDK_4XD))
1126 soc_clk_ctl("hdmi-sys-clk", NULL, CLK_PRINT | CLK_MHZ);
1127 soc_clk_ctl("gfx-core-clk", NULL, CLK_PRINT | CLK_MHZ);
1128 if (is_board_match_runtime(T_BOARD_HSDK)) {
1129 soc_clk_ctl("gfx-dma-clk", NULL, CLK_PRINT | CLK_MHZ);
1130 soc_clk_ctl("gfx-cfg-clk", NULL, CLK_PRINT | CLK_MHZ);
1132 soc_clk_ctl("dmac-core-clk", NULL, CLK_PRINT | CLK_MHZ);
1133 soc_clk_ctl("dmac-cfg-clk", NULL, CLK_PRINT | CLK_MHZ);
1134 soc_clk_ctl("sdio-ref-clk", NULL, CLK_PRINT | CLK_MHZ);
1135 soc_clk_ctl("spi-clk", NULL, CLK_PRINT | CLK_MHZ);
1136 soc_clk_ctl("i2c-clk", NULL, CLK_PRINT | CLK_MHZ);
1137 /* soc_clk_ctl("ebi-clk", NULL, CLK_PRINT | CLK_MHZ); */
1138 soc_clk_ctl("uart-clk", NULL, CLK_PRINT | CLK_MHZ);
1141 /* DDR clock domain */
1142 soc_clk_ctl("ddr-clk", NULL, CLK_PRINT | CLK_MHZ);
1145 /* HDMI clock domain */
1146 if (is_board_match_runtime(T_BOARD_HSDK_4XD)) {
1147 soc_clk_ctl("hdmi-pll", NULL, CLK_PRINT | CLK_MHZ);
1148 soc_clk_ctl("hdmi-clk", NULL, CLK_PRINT | CLK_MHZ);
1152 /* TUN clock domain */
1153 soc_clk_ctl("tun-pll", NULL, CLK_PRINT | CLK_MHZ);
1154 soc_clk_ctl("tun-clk", NULL, CLK_PRINT | CLK_MHZ);
1155 soc_clk_ctl("rom-clk", NULL, CLK_PRINT | CLK_MHZ);
1156 soc_clk_ctl("pwm-clk", NULL, CLK_PRINT | CLK_MHZ);
1157 if (is_board_match_runtime(T_BOARD_HSDK_4XD))
1158 soc_clk_ctl("timer-clk", NULL, CLK_PRINT | CLK_MHZ);
1161 return CMD_RET_SUCCESS;
1164 struct cmd_tbl cmd_hsdk_clock[] = {
1165 U_BOOT_CMD_MKENT(set, 3, 0, do_hsdk_clock_set, "", ""),
1166 U_BOOT_CMD_MKENT(get, 3, 0, do_hsdk_clock_get, "", ""),
1167 U_BOOT_CMD_MKENT(print, 4, 0, do_hsdk_clock_print, "", ""),
1168 U_BOOT_CMD_MKENT(print_all, 4, 0, do_hsdk_clock_print_all, "", ""),
1171 static int do_hsdk_clock(struct cmd_tbl *cmdtp, int flag, int argc,
1177 return CMD_RET_USAGE;
1179 /* Strip off leading 'hsdk_clock' command argument */
1183 c = find_cmd_tbl(argv[0], cmd_hsdk_clock, ARRAY_SIZE(cmd_hsdk_clock));
1185 return CMD_RET_USAGE;
1187 return c->cmd(cmdtp, flag, argc, argv);
1191 hsdk_clock, CONFIG_SYS_MAXARGS, 0, do_hsdk_clock,
1192 "Synopsys HSDK specific clock command",
1193 "set - Set clock to values specified in environment / command line arguments\n"
1194 "hsdk_clock get - Save clock values to environment\n"
1195 "hsdk_clock print - Print main clock values to console\n"
1196 "hsdk_clock print_all - Print all clock values to console\n"
1200 int board_early_init_f(void)
1203 * Setup AXI apertures unconditionally as we want to have DDR
1204 * in 0x00000000 region when we are kicking slave cpus.
1206 init_memory_bridge();
1209 * Switch SDIO external ciu clock divider from default div-by-8 to
1210 * minimum possible div-by-2.
1212 writel(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *)SDIO_UHS_REG_EXT);
1217 int board_early_init_r(void)
1220 * TODO: Init USB here to be able read environment from USB MSD.
1221 * It can be done with usb_init() call. We can't do it right now
1222 * due to brocken USB IP SW reset and lack of USB IP HW reset in
1223 * linux kernel (if we init USB here we will break USB in linux)
1227 * Flush all d$ as we want to use uncached area with st.di / ld.di
1228 * instructions and we don't want to have any dirty line in L1d$ or SL$
1229 * in this area. It is enough to flush all d$ once here as we access to
1230 * uncached area with regular st (non .di) instruction only when we copy
1231 * data during u-boot relocation.
1235 printf("Relocation Offset is: %08lx\n", gd->reloc_off);
1240 int board_late_init(void)
1243 * Populate environment with clock frequency values -
1244 * run hsdk_clock get callback without uboot command run.
1246 do_hsdk_clock_get(NULL, 0, 0, NULL);
1251 int checkboard(void)
1255 printf("Board: Synopsys %s\n", board_name(get_board_type_runtime()));
1257 if (board_mismatch())
1258 printf("WARN: U-boot is configured NOT for this board but for %s!\n",
1259 board_name(get_board_type_config()));
1261 reg = readl(CREG_AXI_M_HS_CORE_BOOT) & CREG_CORE_BOOT_IMAGE;
1262 printf("U-boot autostart: %s\n", reg ? "enabled" : "disabled");