1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
4 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
16 #include <asm/cache.h>
17 #include <linux/delay.h>
18 #include <linux/printk.h>
19 #include <linux/kernel.h>
21 #include <asm/arcregs.h>
22 #include <fdt_support.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 #define ALL_CPU_MASK GENMASK(NR_CPUS - 1, 0)
33 #define MASTER_CPU_ID 0
34 #define APERTURE_SHIFT 28
36 #define SLAVE_CPU_READY 0x12345678
37 #define BOOTSTAGE_1 1 /* after SP, FP setup, before HW init */
38 #define BOOTSTAGE_2 2 /* after HW init, before self halt */
39 #define BOOTSTAGE_3 3 /* after self halt */
40 #define BOOTSTAGE_4 4 /* before app launch */
41 #define BOOTSTAGE_5 5 /* after app launch, unreachable */
43 #define RESET_VECTOR_ADDR 0x0
45 #define CREG_BASE (ARC_PERIPHERAL_BASE + 0x1000)
46 #define CREG_CPU_START (CREG_BASE + 0x400)
47 #define CREG_CPU_START_MASK 0xF
48 #define CREG_CPU_START_POL BIT(4)
50 #define CREG_CORE_BOOT_IMAGE GENMASK(5, 4)
52 #define CREG_CPU_0_ENTRY (CREG_BASE + 0x404)
54 #define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000)
55 #define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108)
56 #define SDIO_UHS_REG_EXT_DIV_2 (2 << 30)
58 /* Uncached access macros */
59 #define arc_read_uncached_32(ptr) \
62 __asm__ __volatile__( \
63 " ld.di %0, [%1] \n" \
69 #define arc_write_uncached_32(ptr, data)\
71 __asm__ __volatile__( \
72 " st.di %0, [%1] \n" \
74 : "r"(data), "r"(ptr)); \
77 struct hsdk_env_core_ctl {
78 u32_env entry[NR_CPUS];
79 u32_env iccm[NR_CPUS];
80 u32_env dccm[NR_CPUS];
83 struct hsdk_env_common_ctl {
98 * Uncached cross-cpu structure. All CPUs must access to this structure fields
99 * only with arc_read_uncached_32() / arc_write_uncached_32() accessors (which
100 * implement ld.di / st.di instructions). Simultaneous cached and uncached
101 * access to this area will lead to data loss.
102 * We flush all data caches in board_early_init_r() as we don't want to have
103 * any dirty line in L1d$ or SL$ in this area.
105 struct hsdk_cross_cpu {
106 /* slave CPU ready flag */
108 /* address of the area, which can be used for stack by slave CPU */
110 /* slave CPU status - bootstage number */
114 * Slave CPU data - it is copy of corresponding fields in
115 * hsdk_env_core_ctl and hsdk_env_common_ctl structures which are
116 * required for slave CPUs initialization.
117 * This fields can be populated by copying from hsdk_env_core_ctl
118 * and hsdk_env_common_ctl structures with sync_cross_cpu_data()
129 u8 cache_padding[ARCH_DMA_MINALIGN];
130 } __aligned(ARCH_DMA_MINALIGN);
132 /* Place for slave CPUs temporary stack */
133 static u32 slave_stack[256 * NR_CPUS] __aligned(ARCH_DMA_MINALIGN);
135 static struct hsdk_env_common_ctl env_common = {};
136 static struct hsdk_env_core_ctl env_core = {};
137 static struct hsdk_cross_cpu cross_cpu_data;
139 static const struct env_map_common env_map_common[] = {
140 { "core_mask", ENV_HEX, true, 0x1, 0xF, &env_common.core_mask },
141 { "non_volatile_limit", ENV_HEX, true, 0, 0xF, &env_common.nvlim },
142 { "icache_ena", ENV_HEX, true, 0, 1, &env_common.icache },
143 { "dcache_ena", ENV_HEX, true, 0, 1, &env_common.dcache },
144 #if defined(CONFIG_BOARD_HSDK_4XD)
145 { "l2_cache_ena", ENV_HEX, true, 0, 1, &env_common.l2_cache },
146 { "csm_location", ENV_HEX, true, 0, NO_CCM, &env_common.csm_location },
147 { "haps_apb_location", ENV_HEX, true, 0, 1, &env_common.haps_apb },
148 #endif /* CONFIG_BOARD_HSDK_4XD */
152 static const struct env_map_common env_map_clock[] = {
153 { "cpu_freq", ENV_DEC, false, 100, 1000, &env_common.cpu_freq },
154 { "axi_freq", ENV_DEC, false, 200, 800, &env_common.axi_freq },
155 { "tun_freq", ENV_DEC, false, 0, 150, &env_common.tun_freq },
159 static const struct env_map_percpu env_map_core[] = {
160 { "core_iccm", ENV_HEX, true, {NO_CCM, 0, NO_CCM, 0}, {NO_CCM, 0xF, NO_CCM, 0xF}, &env_core.iccm },
161 { "core_dccm", ENV_HEX, true, {NO_CCM, 0, NO_CCM, 0}, {NO_CCM, 0xF, NO_CCM, 0xF}, &env_core.dccm },
165 static const struct env_map_common env_map_mask[] = {
166 { "core_mask", ENV_HEX, false, 0x1, 0xF, &env_common.core_mask },
170 static const struct env_map_percpu env_map_go[] = {
171 { "core_entry", ENV_HEX, true, {0, 0, 0, 0}, {U32_MAX, U32_MAX, U32_MAX, U32_MAX}, &env_core.entry },
181 static inline enum board_type get_board_type_runtime(void)
183 u32 arc_id = read_aux_reg(ARC_AUX_IDENTITY) & 0xFF;
187 else if (arc_id == 0x54)
188 return T_BOARD_HSDK_4XD;
193 static inline enum board_type get_board_type_config(void)
195 if (IS_ENABLED(CONFIG_BOARD_HSDK))
197 else if (IS_ENABLED(CONFIG_BOARD_HSDK_4XD))
198 return T_BOARD_HSDK_4XD;
203 static bool is_board_match_runtime(enum board_type type_req)
205 return get_board_type_runtime() == type_req;
208 static bool is_board_match_config(enum board_type type_req)
210 return get_board_type_config() == type_req;
213 static const char * board_name(enum board_type type)
217 return "ARC HS Development Kit";
218 case T_BOARD_HSDK_4XD:
219 return "ARC HS4x/HS4xD Development Kit";
225 static bool board_mismatch(void)
227 return get_board_type_config() != get_board_type_runtime();
230 static void sync_cross_cpu_data(void)
234 for (u32 i = 0; i < NR_CPUS; i++) {
235 value = env_core.entry[i].val;
236 arc_write_uncached_32(&cross_cpu_data.entry[i], value);
239 for (u32 i = 0; i < NR_CPUS; i++) {
240 value = env_core.iccm[i].val;
241 arc_write_uncached_32(&cross_cpu_data.iccm[i], value);
244 for (u32 i = 0; i < NR_CPUS; i++) {
245 value = env_core.dccm[i].val;
246 arc_write_uncached_32(&cross_cpu_data.dccm[i], value);
249 value = env_common.core_mask.val;
250 arc_write_uncached_32(&cross_cpu_data.core_mask, value);
252 value = env_common.icache.val;
253 arc_write_uncached_32(&cross_cpu_data.icache, value);
255 value = env_common.dcache.val;
256 arc_write_uncached_32(&cross_cpu_data.dcache, value);
259 /* Can be used only on master CPU */
260 static bool is_cpu_used(u32 cpu_id)
262 return !!(env_common.core_mask.val & BIT(cpu_id));
265 /* TODO: add ICCM BCR and DCCM BCR runtime check */
266 static void init_slave_cpu_func(u32 core)
270 /* Remap ICCM to another memory region if it exists */
271 val = arc_read_uncached_32(&cross_cpu_data.iccm[core]);
273 write_aux_reg(ARC_AUX_ICCM_BASE, val << APERTURE_SHIFT);
275 /* Remap DCCM to another memory region if it exists */
276 val = arc_read_uncached_32(&cross_cpu_data.dccm[core]);
278 write_aux_reg(ARC_AUX_DCCM_BASE, val << APERTURE_SHIFT);
280 if (arc_read_uncached_32(&cross_cpu_data.icache))
285 if (arc_read_uncached_32(&cross_cpu_data.dcache))
291 static void init_cluster_nvlim(void)
293 u32 val = env_common.nvlim.val << APERTURE_SHIFT;
296 write_aux_reg(ARC_AUX_NON_VOLATILE_LIMIT, val);
297 /* AUX_AUX_CACHE_LIMIT reg is missing starting from HS48 */
298 if (is_board_match_runtime(T_BOARD_HSDK))
299 write_aux_reg(AUX_AUX_CACHE_LIMIT, val);
300 flush_n_invalidate_dcache_all();
303 static void init_cluster_slc(void)
305 /* ARC HS38 doesn't support SLC disabling */
306 if (!is_board_match_config(T_BOARD_HSDK_4XD))
309 if (env_common.l2_cache.val)
315 #define CREG_CSM_BASE (CREG_BASE + 0x210)
317 static void init_cluster_csm(void)
319 /* ARC HS38 in HSDK SoC doesn't include CSM */
320 if (!is_board_match_config(T_BOARD_HSDK_4XD))
323 if (env_common.csm_location.val == NO_CCM) {
324 write_aux_reg(ARC_AUX_CSM_ENABLE, 0);
327 * CSM base address is 256kByte aligned but we allow to map
328 * CSM only to aperture start (256MByte aligned)
329 * The field in CREG_CSM_BASE is in 17:2 bits itself so we need
332 u32 csm_base = (env_common.csm_location.val * SZ_1K) << 2;
334 write_aux_reg(ARC_AUX_CSM_ENABLE, 1);
335 writel(csm_base, (void __iomem *)CREG_CSM_BASE);
339 static void init_master_icache(void)
341 if (icache_status()) {
342 /* I$ is enabled - we need to disable it */
343 if (!env_common.icache.val)
346 /* I$ is disabled - we need to enable it */
347 if (env_common.icache.val) {
350 /* invalidate I$ right after enable */
351 invalidate_icache_all();
356 static void init_master_dcache(void)
358 if (dcache_status()) {
359 /* D$ is enabled - we need to disable it */
360 if (!env_common.dcache.val)
363 /* D$ is disabled - we need to enable it */
364 if (env_common.dcache.val)
367 /* TODO: probably we need ti invalidate D$ right after enable */
371 static int cleanup_before_go(void)
373 disable_interrupts();
374 sync_n_cleanup_cache_all();
379 void slave_cpu_set_boot_addr(u32 addr)
381 /* All cores have reset vector pointing to 0 */
382 writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
384 /* Make sure other cores see written value in memory */
385 sync_n_cleanup_cache_all();
388 static inline void halt_this_cpu(void)
390 __builtin_arc_flag(1);
393 static u32 get_masked_cpu_ctart_reg(void)
395 int cmd = readl((void __iomem *)CREG_CPU_START);
398 * Quirk for HSDK-4xD - due to HW issues HSDK can use any pulse polarity
399 * and HSDK-4xD require active low polarity of cpu_start pulse.
401 cmd &= ~CREG_CPU_START_POL;
403 cmd &= ~CREG_CPU_START_MASK;
408 static void smp_kick_cpu_x(u32 cpu_id)
412 if (cpu_id > NR_CPUS)
415 cmd = get_masked_cpu_ctart_reg();
416 cmd |= (1 << cpu_id);
417 writel(cmd, (void __iomem *)CREG_CPU_START);
420 static u32 prepare_cpu_ctart_reg(void)
422 return get_masked_cpu_ctart_reg() | env_common.core_mask.val;
425 /* slave CPU entry for configuration */
426 __attribute__((naked, noreturn, flatten)) noinline void hsdk_core_init_f(void)
428 __asm__ __volatile__(
433 : "r" (&cross_cpu_data.stack_ptr));
435 invalidate_icache_all();
437 arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_1);
438 init_slave_cpu_func(CPU_ID_GET());
440 arc_write_uncached_32(&cross_cpu_data.ready_flag, SLAVE_CPU_READY);
441 arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_2);
443 /* Halt the processor until the master kick us again */
447 * 3 NOPs after FLAG 1 instruction are no longer required for ARCv2
448 * cores but we leave them for gebug purposes.
454 arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_3);
456 /* get the updated entry - invalidate i$ */
457 invalidate_icache_all();
459 arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_4);
461 /* Run our program */
462 ((void (*)(void))(arc_read_uncached_32(&cross_cpu_data.entry[CPU_ID_GET()])))();
464 /* This bootstage is unreachable as we don't return from app we launch */
465 arc_write_uncached_32(&cross_cpu_data.status[CPU_ID_GET()], BOOTSTAGE_5);
467 /* Something went terribly wrong */
472 static void clear_cross_cpu_data(void)
474 arc_write_uncached_32(&cross_cpu_data.ready_flag, 0);
475 arc_write_uncached_32(&cross_cpu_data.stack_ptr, 0);
477 for (u32 i = 0; i < NR_CPUS; i++)
478 arc_write_uncached_32(&cross_cpu_data.status[i], 0);
481 static noinline void do_init_slave_cpu(u32 cpu_id)
483 /* attempts number for check clave CPU ready_flag */
485 u32 stack_ptr = (u32)(slave_stack + (64 * cpu_id));
487 if (cpu_id >= NR_CPUS)
490 arc_write_uncached_32(&cross_cpu_data.ready_flag, 0);
492 /* Use global unique place for each slave cpu stack */
493 arc_write_uncached_32(&cross_cpu_data.stack_ptr, stack_ptr);
495 debug("CPU %u: stack pool base: %p\n", cpu_id, slave_stack);
496 debug("CPU %u: current slave stack base: %x\n", cpu_id, stack_ptr);
497 slave_cpu_set_boot_addr((u32)hsdk_core_init_f);
499 smp_kick_cpu_x(cpu_id);
501 debug("CPU %u: cross-cpu flag: %x [before timeout]\n", cpu_id,
502 arc_read_uncached_32(&cross_cpu_data.ready_flag));
504 while (!arc_read_uncached_32(&cross_cpu_data.ready_flag) && attempts--)
507 /* Just to be sure that slave cpu is halted after it set ready_flag */
511 * Only print error here if we reach timeout as there is no option to
512 * halt slave cpu (or check that slave cpu is halted)
515 pr_err("CPU %u is not responding after init!\n", cpu_id);
517 /* Check current stage of slave cpu */
518 if (arc_read_uncached_32(&cross_cpu_data.status[cpu_id]) != BOOTSTAGE_2)
519 pr_err("CPU %u status is unexpected: %d\n", cpu_id,
520 arc_read_uncached_32(&cross_cpu_data.status[cpu_id]));
522 debug("CPU %u: cross-cpu flag: %x [after timeout]\n", cpu_id,
523 arc_read_uncached_32(&cross_cpu_data.ready_flag));
524 debug("CPU %u: status: %d [after timeout]\n", cpu_id,
525 arc_read_uncached_32(&cross_cpu_data.status[cpu_id]));
528 static void do_init_slave_cpus(void)
530 clear_cross_cpu_data();
531 sync_cross_cpu_data();
533 debug("cross_cpu_data location: %#x\n", (u32)&cross_cpu_data);
535 for (u32 i = MASTER_CPU_ID + 1; i < NR_CPUS; i++)
537 do_init_slave_cpu(i);
540 static void do_init_master_cpu(void)
543 * Setup master caches even if master isn't used as we want to use
544 * same cache configuration on all running CPUs
546 init_master_icache();
547 init_master_dcache();
550 enum hsdk_axi_masters {
568 * m master AXI_M_m_SLV0 AXI_M_m_SLV1 AXI_M_m_OFFSET0 AXI_M_m_OFFSET1
569 * 0 HS (CBU) 0x11111111 0x63111111 0xFEDCBA98 0x0E543210
570 * 1 HS (RTT) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
571 * 2 AXI Tunnel 0x88888888 0x88888888 0xFEDCBA98 0x76543210
572 * 3 HDMI-VIDEO 0x77777777 0x77777777 0xFEDCBA98 0x76543210
573 * 4 HDMI-ADUIO 0x77777777 0x77777777 0xFEDCBA98 0x76543210
574 * 5 USB-HOST 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
575 * 6 ETHERNET 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
576 * 7 SDIO 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
577 * 8 GPU 0x77777777 0x77777777 0xFEDCBA98 0x76543210
578 * 9 DMAC (port #1) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
579 * 10 DMAC (port #2) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
580 * 11 DVFS 0x00000000 0x60000000 0x00000000 0x00000000
582 * Please read ARC HS Development IC Specification, section 17.2 for more
583 * information about apertures configuration.
584 * NOTE: we intentionally modify default settings in U-boot. Default settings
585 * are specified in "Table 111 CREG Address Decoder register reset values".
588 #define CREG_AXI_M_SLV0(m) ((void __iomem *)(CREG_BASE + 0x020 * (m)))
589 #define CREG_AXI_M_SLV1(m) ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x004))
590 #define CREG_AXI_M_OFT0(m) ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x008))
591 #define CREG_AXI_M_OFT1(m) ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x00C))
592 #define CREG_AXI_M_UPDT(m) ((void __iomem *)(CREG_BASE + 0x020 * (m) + 0x014))
594 #define CREG_AXI_M_HS_CORE_BOOT ((void __iomem *)(CREG_BASE + 0x010))
596 #define CREG_PAE ((void __iomem *)(CREG_BASE + 0x180))
597 #define CREG_PAE_UPDT ((void __iomem *)(CREG_BASE + 0x194))
599 void init_memory_bridge(void)
604 * M_HS_CORE has one unic register - BOOT.
605 * We need to clean boot mirror (BOOT[1:0]) bits in them.
607 reg = readl(CREG_AXI_M_HS_CORE_BOOT) & (~0x3);
608 writel(reg, CREG_AXI_M_HS_CORE_BOOT);
609 writel(0x11111111, CREG_AXI_M_SLV0(M_HS_CORE));
610 writel(0x63111111, CREG_AXI_M_SLV1(M_HS_CORE));
611 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_CORE));
612 writel(0x0E543210, CREG_AXI_M_OFT1(M_HS_CORE));
613 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_CORE));
615 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT));
616 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT));
617 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT));
618 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT));
619 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT));
621 writel(0x88888888, CREG_AXI_M_SLV0(M_AXI_TUN));
622 writel(0x88888888, CREG_AXI_M_SLV1(M_AXI_TUN));
623 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_AXI_TUN));
624 writel(0x76543210, CREG_AXI_M_OFT1(M_AXI_TUN));
625 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_AXI_TUN));
627 writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_VIDEO));
628 writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_VIDEO));
629 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_VIDEO));
630 writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_VIDEO));
631 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_VIDEO));
633 writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_AUDIO));
634 writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_AUDIO));
635 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_AUDIO));
636 writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_AUDIO));
637 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_AUDIO));
639 writel(0x77777777, CREG_AXI_M_SLV0(M_USB_HOST));
640 writel(0x77999999, CREG_AXI_M_SLV1(M_USB_HOST));
641 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_USB_HOST));
642 writel(0x76DCBA98, CREG_AXI_M_OFT1(M_USB_HOST));
643 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_USB_HOST));
645 writel(0x77777777, CREG_AXI_M_SLV0(M_ETHERNET));
646 writel(0x77999999, CREG_AXI_M_SLV1(M_ETHERNET));
647 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_ETHERNET));
648 writel(0x76DCBA98, CREG_AXI_M_OFT1(M_ETHERNET));
649 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_ETHERNET));
651 writel(0x77777777, CREG_AXI_M_SLV0(M_SDIO));
652 writel(0x77999999, CREG_AXI_M_SLV1(M_SDIO));
653 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_SDIO));
654 writel(0x76DCBA98, CREG_AXI_M_OFT1(M_SDIO));
655 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO));
657 writel(0x77777777, CREG_AXI_M_SLV0(M_GPU));
658 writel(0x77777777, CREG_AXI_M_SLV1(M_GPU));
659 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_GPU));
660 writel(0x76543210, CREG_AXI_M_OFT1(M_GPU));
661 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_GPU));
663 writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0));
664 writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_0));
665 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0));
666 writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_0));
667 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0));
669 writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1));
670 writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_1));
671 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1));
672 writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_1));
673 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1));
675 writel(0x00000000, CREG_AXI_M_SLV0(M_DVFS));
676 writel(0x60000000, CREG_AXI_M_SLV1(M_DVFS));
677 writel(0x00000000, CREG_AXI_M_OFT0(M_DVFS));
678 writel(0x00000000, CREG_AXI_M_OFT1(M_DVFS));
679 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DVFS));
681 writel(0x00000000, CREG_PAE);
682 writel(UPDATE_VAL, CREG_PAE_UPDT);
686 * For HSDK-4xD we do additional AXI bridge tweaking in hsdk_init command:
687 * - we shrink IOC region.
688 * - we configure HS CORE SLV1 aperture depending on haps_apb_location
689 * environment variable.
691 * As we've already configured AXI bridge in init_memory_bridge we don't
692 * do full configuration here but reconfigure changed part.
694 * m master AXI_M_m_SLV0 AXI_M_m_SLV1 AXI_M_m_OFFSET0 AXI_M_m_OFFSET1
695 * 0 HS (CBU) 0x11111111 0x63111111 0xFEDCBA98 0x0E543210 [haps_apb_location = 0]
696 * 0 HS (CBU) 0x11111111 0x61111111 0xFEDCBA98 0x06543210 [haps_apb_location = 1]
697 * 1 HS (RTT) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
698 * 2 AXI Tunnel 0x88888888 0x88888888 0xFEDCBA98 0x76543210
699 * 3 HDMI-VIDEO 0x77777777 0x77777777 0xFEDCBA98 0x76543210
700 * 4 HDMI-ADUIO 0x77777777 0x77777777 0xFEDCBA98 0x76543210
701 * 5 USB-HOST 0x77777777 0x77779999 0xFEDCBA98 0x7654BA98
702 * 6 ETHERNET 0x77777777 0x77779999 0xFEDCBA98 0x7654BA98
703 * 7 SDIO 0x77777777 0x77779999 0xFEDCBA98 0x7654BA98
704 * 8 GPU 0x77777777 0x77777777 0xFEDCBA98 0x76543210
705 * 9 DMAC (port #1) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
706 * 10 DMAC (port #2) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
707 * 11 DVFS 0x00000000 0x60000000 0x00000000 0x00000000
709 void tweak_memory_bridge_cfg(void)
712 * Only HSDK-4xD requre additional AXI bridge tweaking depending on
713 * haps_apb_location environment variable
715 if (!is_board_match_config(T_BOARD_HSDK_4XD))
718 if (env_common.haps_apb.val) {
719 writel(0x61111111, CREG_AXI_M_SLV1(M_HS_CORE));
720 writel(0x06543210, CREG_AXI_M_OFT1(M_HS_CORE));
722 writel(0x63111111, CREG_AXI_M_SLV1(M_HS_CORE));
723 writel(0x0E543210, CREG_AXI_M_OFT1(M_HS_CORE));
725 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_CORE));
727 writel(0x77779999, CREG_AXI_M_SLV1(M_USB_HOST));
728 writel(0x7654BA98, CREG_AXI_M_OFT1(M_USB_HOST));
729 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_USB_HOST));
731 writel(0x77779999, CREG_AXI_M_SLV1(M_ETHERNET));;
732 writel(0x7654BA98, CREG_AXI_M_OFT1(M_ETHERNET));
733 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_ETHERNET));
735 writel(0x77779999, CREG_AXI_M_SLV1(M_SDIO));
736 writel(0x7654BA98, CREG_AXI_M_OFT1(M_SDIO));
737 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO));
740 static void setup_clocks(void)
744 /* Setup CPU clock */
745 if (env_common.cpu_freq.set) {
746 rate = env_common.cpu_freq.val;
747 soc_clk_ctl("cpu-clk", &rate, CLK_ON | CLK_SET | CLK_MHZ);
750 /* Setup TUN clock */
751 if (env_common.tun_freq.set) {
752 rate = env_common.tun_freq.val;
754 soc_clk_ctl("tun-clk", &rate, CLK_ON | CLK_SET | CLK_MHZ);
756 soc_clk_ctl("tun-clk", NULL, CLK_OFF);
759 if (env_common.axi_freq.set) {
760 rate = env_common.axi_freq.val;
761 soc_clk_ctl("axi-clk", &rate, CLK_SET | CLK_ON | CLK_MHZ);
765 static void do_init_cluster(void)
768 * A multi-core ARC HS configuration always includes only one
769 * ARC_AUX_NON_VOLATILE_LIMIT register, which is shared by all the
772 init_cluster_nvlim();
775 tweak_memory_bridge_cfg();
778 static int check_master_cpu_id(void)
780 if (CPU_ID_GET() == MASTER_CPU_ID)
783 pr_err("u-boot runs on non-master cpu with id: %lu\n", CPU_ID_GET());
788 static noinline int prepare_cpus(void)
792 ret = check_master_cpu_id();
796 ret = envs_process_and_validate(env_map_common, env_map_core, is_cpu_used);
800 printf("CPU start mask is %#x\n", env_common.core_mask.val);
802 do_init_slave_cpus();
803 do_init_master_cpu();
809 static int hsdk_go_run(u32 cpu_start_reg)
811 /* Cleanup caches, disable interrupts */
814 if (env_common.halt_on_boot)
818 * 3 NOPs after FLAG 1 instruction are no longer required for ARCv2
819 * cores but we leave them for gebug purposes.
825 /* Kick chosen slave CPUs */
826 writel(cpu_start_reg, (void __iomem *)CREG_CPU_START);
828 if (is_cpu_used(MASTER_CPU_ID))
829 ((void (*)(void))(env_core.entry[MASTER_CPU_ID].val))();
833 pr_err("u-boot still runs on cpu [%ld]\n", CPU_ID_GET());
836 * We will never return after executing our program if master cpu used
837 * otherwise halt master cpu manually.
845 int board_prep_linux(bootm_headers_t *images)
850 ret = envs_read_validate_common(env_map_mask);
854 /* Rollback to default values */
855 if (!env_common.core_mask.set) {
856 env_common.core_mask.val = ALL_CPU_MASK;
857 env_common.core_mask.set = true;
860 printf("CPU start mask is %#x\n", env_common.core_mask.val);
862 if (!is_cpu_used(MASTER_CPU_ID))
863 pr_err("ERR: try to launch linux with CPU[0] disabled! It doesn't work for ARC.\n");
866 * If we want to launch linux on all CPUs we don't need to patch
867 * linux DTB as it is default configuration
869 if (env_common.core_mask.val == ALL_CPU_MASK)
872 if (!IMAGE_ENABLE_OF_LIBFDT || !images->ft_len) {
873 pr_err("WARN: core_mask setup will work properly only with external DTB!\n");
877 /* patch '/possible-cpus' property according to cpu mask */
878 ofst = fdt_path_offset(images->ft_addr, "/");
879 sprintf(mask, "%s%s%s%s",
880 is_cpu_used(0) ? "0," : "",
881 is_cpu_used(1) ? "1," : "",
882 is_cpu_used(2) ? "2," : "",
883 is_cpu_used(3) ? "3," : "");
884 ret = fdt_setprop_string(images->ft_addr, ofst, "possible-cpus", mask);
886 * If we failed to patch '/possible-cpus' property we don't need break
887 * linux loading process: kernel will handle it but linux will print
888 * warning like "Timeout: CPU1 FAILED to comeup !!!".
889 * So warn here about error, but return 0 like no error had occurred.
892 pr_err("WARN: failed to patch '/possible-cpus' property, ret=%d\n",
898 void board_jump_and_run(ulong entry, int zero, int arch, uint params)
900 void (*kernel_entry)(int zero, int arch, uint params);
903 kernel_entry = (void (*)(int, int, uint))entry;
905 /* Prepare CREG_CPU_START for kicking chosen CPUs */
906 cpu_start_reg = prepare_cpu_ctart_reg();
908 /* In case of run without hsdk_init */
909 slave_cpu_set_boot_addr(entry);
911 /* In case of run with hsdk_init */
912 for (u32 i = 0; i < NR_CPUS; i++) {
913 env_core.entry[i].val = entry;
914 env_core.entry[i].set = true;
916 /* sync cross_cpu struct as we updated core-entry variables */
917 sync_cross_cpu_data();
919 /* Kick chosen slave CPUs */
920 writel(cpu_start_reg, (void __iomem *)CREG_CPU_START);
923 kernel_entry(zero, arch, params);
926 static int hsdk_go_prepare_and_run(void)
928 /* Prepare CREG_CPU_START for kicking chosen CPUs */
929 u32 reg = prepare_cpu_ctart_reg();
931 if (env_common.halt_on_boot)
932 printf("CPU will halt before application start, start application with debugger.\n");
934 return hsdk_go_run(reg);
937 static int do_hsdk_go(struct cmd_tbl *cmdtp, int flag, int argc,
942 if (board_mismatch()) {
943 printf("ERR: U-boot is not configured for this board!\n");
944 return CMD_RET_FAILURE;
948 * Check for 'halt' parameter. 'halt' = enter halt-mode just before
949 * starting the application; can be used for debug.
952 env_common.halt_on_boot = !strcmp(argv[1], "halt");
953 if (!env_common.halt_on_boot) {
954 pr_err("Unrecognised parameter: \'%s\'\n", argv[1]);
955 return CMD_RET_FAILURE;
959 ret = check_master_cpu_id();
963 ret = envs_process_and_validate(env_map_mask, env_map_go, is_cpu_used);
967 /* sync cross_cpu struct as we updated core-entry variables */
968 sync_cross_cpu_data();
970 ret = hsdk_go_prepare_and_run();
972 return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
976 hsdk_go, 3, 0, do_hsdk_go,
977 "Synopsys HSDK specific command",
978 " - Boot stand-alone application on HSDK\n"
979 "hsdk_go halt - Boot stand-alone application on HSDK, halt CPU just before application run\n"
983 * We may simply use static variable here to store init status, but we also want
984 * to avoid the situation when we reload U-boot via MDB after previous
985 * init is done but HW reset (board reset) isn't done. So let's store the
986 * init status in any unused register (i.e CREG_CPU_0_ENTRY) so status will
987 * survive after U-boot is reloaded via MDB.
989 #define INIT_MARKER_REGISTER ((void __iomem *)CREG_CPU_0_ENTRY)
990 /* must be equal to INIT_MARKER_REGISTER reset value */
991 #define INIT_MARKER_PENDING 0
993 static bool init_marker_get(void)
995 return readl(INIT_MARKER_REGISTER) != INIT_MARKER_PENDING;
998 static void init_mark_done(void)
1000 writel(~INIT_MARKER_PENDING, INIT_MARKER_REGISTER);
1003 static int do_hsdk_init(struct cmd_tbl *cmdtp, int flag, int argc,
1008 if (board_mismatch()) {
1009 printf("ERR: U-boot is not configured for this board!\n");
1010 return CMD_RET_FAILURE;
1013 /* hsdk_init can be run only once */
1014 if (init_marker_get()) {
1015 printf("HSDK HW is already initialized! Please reset the board if you want to change the configuration.\n");
1016 return CMD_RET_FAILURE;
1019 ret = prepare_cpus();
1023 return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
1027 hsdk_init, 1, 0, do_hsdk_init,
1028 "Synopsys HSDK specific command",
1032 static int do_hsdk_clock_set(struct cmd_tbl *cmdtp, int flag, int argc,
1037 /* Strip off leading subcommand argument */
1041 envs_cleanup_common(env_map_clock);
1044 printf("Set clocks to values specified in environment\n");
1045 ret = envs_read_common(env_map_clock);
1047 printf("Set clocks to values specified in args\n");
1048 ret = args_envs_enumerate(env_map_clock, 2, argc, argv);
1052 return CMD_RET_FAILURE;
1054 ret = envs_validate_common(env_map_clock);
1056 return CMD_RET_FAILURE;
1058 /* Setup clock tree HW */
1061 return CMD_RET_SUCCESS;
1064 static int do_hsdk_clock_get(struct cmd_tbl *cmdtp, int flag, int argc,
1069 if (soc_clk_ctl("cpu-clk", &rate, CLK_GET | CLK_MHZ))
1070 return CMD_RET_FAILURE;
1072 if (env_set_ulong("cpu_freq", rate))
1073 return CMD_RET_FAILURE;
1075 if (soc_clk_ctl("tun-clk", &rate, CLK_GET | CLK_MHZ))
1076 return CMD_RET_FAILURE;
1078 if (env_set_ulong("tun_freq", rate))
1079 return CMD_RET_FAILURE;
1081 if (soc_clk_ctl("axi-clk", &rate, CLK_GET | CLK_MHZ))
1082 return CMD_RET_FAILURE;
1084 if (env_set_ulong("axi_freq", rate))
1085 return CMD_RET_FAILURE;
1087 printf("Clock values are saved to environment\n");
1089 return CMD_RET_SUCCESS;
1092 static int do_hsdk_clock_print(struct cmd_tbl *cmdtp, int flag, int argc,
1096 soc_clk_ctl("cpu-clk", NULL, CLK_PRINT | CLK_MHZ);
1097 soc_clk_ctl("tun-clk", NULL, CLK_PRINT | CLK_MHZ);
1098 soc_clk_ctl("axi-clk", NULL, CLK_PRINT | CLK_MHZ);
1099 soc_clk_ctl("ddr-clk", NULL, CLK_PRINT | CLK_MHZ);
1101 return CMD_RET_SUCCESS;
1104 static int do_hsdk_clock_print_all(struct cmd_tbl *cmdtp, int flag, int argc,
1108 * NOTE: as of today we don't use some peripherals like HDMI / EBI
1109 * so we don't want to print their clocks ("hdmi-sys-clk", "hdmi-pll",
1110 * "hdmi-clk", "ebi-clk"). Nevertheless their clock subsystems is fully
1111 * functional and we can print their clocks if it is required
1114 /* CPU clock domain */
1115 soc_clk_ctl("cpu-pll", NULL, CLK_PRINT | CLK_MHZ);
1116 soc_clk_ctl("cpu-clk", NULL, CLK_PRINT | CLK_MHZ);
1119 /* SYS clock domain */
1120 soc_clk_ctl("sys-pll", NULL, CLK_PRINT | CLK_MHZ);
1121 soc_clk_ctl("apb-clk", NULL, CLK_PRINT | CLK_MHZ);
1122 soc_clk_ctl("axi-clk", NULL, CLK_PRINT | CLK_MHZ);
1123 soc_clk_ctl("eth-clk", NULL, CLK_PRINT | CLK_MHZ);
1124 soc_clk_ctl("usb-clk", NULL, CLK_PRINT | CLK_MHZ);
1125 soc_clk_ctl("sdio-clk", NULL, CLK_PRINT | CLK_MHZ);
1126 if (is_board_match_runtime(T_BOARD_HSDK_4XD))
1127 soc_clk_ctl("hdmi-sys-clk", NULL, CLK_PRINT | CLK_MHZ);
1128 soc_clk_ctl("gfx-core-clk", NULL, CLK_PRINT | CLK_MHZ);
1129 if (is_board_match_runtime(T_BOARD_HSDK)) {
1130 soc_clk_ctl("gfx-dma-clk", NULL, CLK_PRINT | CLK_MHZ);
1131 soc_clk_ctl("gfx-cfg-clk", NULL, CLK_PRINT | CLK_MHZ);
1133 soc_clk_ctl("dmac-core-clk", NULL, CLK_PRINT | CLK_MHZ);
1134 soc_clk_ctl("dmac-cfg-clk", NULL, CLK_PRINT | CLK_MHZ);
1135 soc_clk_ctl("sdio-ref-clk", NULL, CLK_PRINT | CLK_MHZ);
1136 soc_clk_ctl("spi-clk", NULL, CLK_PRINT | CLK_MHZ);
1137 soc_clk_ctl("i2c-clk", NULL, CLK_PRINT | CLK_MHZ);
1138 /* soc_clk_ctl("ebi-clk", NULL, CLK_PRINT | CLK_MHZ); */
1139 soc_clk_ctl("uart-clk", NULL, CLK_PRINT | CLK_MHZ);
1142 /* DDR clock domain */
1143 soc_clk_ctl("ddr-clk", NULL, CLK_PRINT | CLK_MHZ);
1146 /* HDMI clock domain */
1147 if (is_board_match_runtime(T_BOARD_HSDK_4XD)) {
1148 soc_clk_ctl("hdmi-pll", NULL, CLK_PRINT | CLK_MHZ);
1149 soc_clk_ctl("hdmi-clk", NULL, CLK_PRINT | CLK_MHZ);
1153 /* TUN clock domain */
1154 soc_clk_ctl("tun-pll", NULL, CLK_PRINT | CLK_MHZ);
1155 soc_clk_ctl("tun-clk", NULL, CLK_PRINT | CLK_MHZ);
1156 soc_clk_ctl("rom-clk", NULL, CLK_PRINT | CLK_MHZ);
1157 soc_clk_ctl("pwm-clk", NULL, CLK_PRINT | CLK_MHZ);
1158 if (is_board_match_runtime(T_BOARD_HSDK_4XD))
1159 soc_clk_ctl("timer-clk", NULL, CLK_PRINT | CLK_MHZ);
1162 return CMD_RET_SUCCESS;
1165 struct cmd_tbl cmd_hsdk_clock[] = {
1166 U_BOOT_CMD_MKENT(set, 3, 0, do_hsdk_clock_set, "", ""),
1167 U_BOOT_CMD_MKENT(get, 3, 0, do_hsdk_clock_get, "", ""),
1168 U_BOOT_CMD_MKENT(print, 4, 0, do_hsdk_clock_print, "", ""),
1169 U_BOOT_CMD_MKENT(print_all, 4, 0, do_hsdk_clock_print_all, "", ""),
1172 static int do_hsdk_clock(struct cmd_tbl *cmdtp, int flag, int argc,
1178 return CMD_RET_USAGE;
1180 /* Strip off leading 'hsdk_clock' command argument */
1184 c = find_cmd_tbl(argv[0], cmd_hsdk_clock, ARRAY_SIZE(cmd_hsdk_clock));
1186 return CMD_RET_USAGE;
1188 return c->cmd(cmdtp, flag, argc, argv);
1192 hsdk_clock, CONFIG_SYS_MAXARGS, 0, do_hsdk_clock,
1193 "Synopsys HSDK specific clock command",
1194 "set - Set clock to values specified in environment / command line arguments\n"
1195 "hsdk_clock get - Save clock values to environment\n"
1196 "hsdk_clock print - Print main clock values to console\n"
1197 "hsdk_clock print_all - Print all clock values to console\n"
1201 int board_early_init_f(void)
1204 * Setup AXI apertures unconditionally as we want to have DDR
1205 * in 0x00000000 region when we are kicking slave cpus.
1207 init_memory_bridge();
1210 * Switch SDIO external ciu clock divider from default div-by-8 to
1211 * minimum possible div-by-2.
1213 writel(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *)SDIO_UHS_REG_EXT);
1218 int board_early_init_r(void)
1221 * TODO: Init USB here to be able read environment from USB MSD.
1222 * It can be done with usb_init() call. We can't do it right now
1223 * due to brocken USB IP SW reset and lack of USB IP HW reset in
1224 * linux kernel (if we init USB here we will break USB in linux)
1228 * Flush all d$ as we want to use uncached area with st.di / ld.di
1229 * instructions and we don't want to have any dirty line in L1d$ or SL$
1230 * in this area. It is enough to flush all d$ once here as we access to
1231 * uncached area with regular st (non .di) instruction only when we copy
1232 * data during u-boot relocation.
1236 printf("Relocation Offset is: %08lx\n", gd->reloc_off);
1241 int board_late_init(void)
1244 * Populate environment with clock frequency values -
1245 * run hsdk_clock get callback without uboot command run.
1247 do_hsdk_clock_get(NULL, 0, 0, NULL);
1252 int checkboard(void)
1256 printf("Board: Synopsys %s\n", board_name(get_board_type_runtime()));
1258 if (board_mismatch())
1259 printf("WARN: U-boot is configured NOT for this board but for %s!\n",
1260 board_name(get_board_type_config()));
1262 reg = readl(CREG_AXI_M_HS_CORE_BOOT) & CREG_CORE_BOOT_IMAGE;
1263 printf("U-boot autostart: %s\n", reg ? "enabled" : "disabled");