1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
11 #include <asm/arcregs.h>
13 DECLARE_GLOBAL_DATA_PTR;
15 #define ARC_PERIPHERAL_BASE 0xF0000000
17 #define CGU_ARC_FMEAS_ARC (void *)(ARC_PERIPHERAL_BASE + 0x84)
18 #define CGU_ARC_FMEAS_ARC_START BIT(31)
19 #define CGU_ARC_FMEAS_ARC_DONE BIT(30)
20 #define CGU_ARC_FMEAS_ARC_CNT_MASK GENMASK(14, 0)
21 #define CGU_ARC_FMEAS_ARC_RCNT_OFFSET 0
22 #define CGU_ARC_FMEAS_ARC_FCNT_OFFSET 15
24 #define SDIO_BASE (void *)(ARC_PERIPHERAL_BASE + 0x10000)
26 int mach_cpu_init(void)
31 /* Start frequency measurement */
32 writel(CGU_ARC_FMEAS_ARC_START, CGU_ARC_FMEAS_ARC);
36 data = readl(CGU_ARC_FMEAS_ARC);
37 } while (!(data & CGU_ARC_FMEAS_ARC_DONE));
39 /* Amount of reference 100 MHz clocks */
40 rcnt = ((data >> CGU_ARC_FMEAS_ARC_RCNT_OFFSET) &
41 CGU_ARC_FMEAS_ARC_CNT_MASK);
43 /* Amount of CPU clocks */
44 fcnt = ((data >> CGU_ARC_FMEAS_ARC_FCNT_OFFSET) &
45 CGU_ARC_FMEAS_ARC_CNT_MASK);
47 gd->cpu_clk = ((100 * fcnt) / rcnt) * 1000000;
52 int board_early_init_r(void)
54 #define EMSDP_PSRAM_BASE 0xf2001000
55 #define PSRAM_FLASH_CONFIG_REG_0 (void *)(EMSDP_PSRAM_BASE + 0x10)
56 #define PSRAM_FLASH_CONFIG_REG_1 (void *)(EMSDP_PSRAM_BASE + 0x14)
57 #define CRE_ENABLE BIT(31)
58 #define CRE_DRIVE_CMD BIT(6)
60 #define PSRAM_RCR_DPD BIT(1)
61 #define PSRAM_RCR_PAGE_MODE BIT(7)
64 * PSRAM_FLASH_CONFIG_REG_x[30:15] to the address lines[16:1] of flash,
67 #define PSRAM_RCR_SETUP ((PSRAM_RCR_DPD | PSRAM_RCR_PAGE_MODE) << 1)
69 // Switch PSRAM controller to command mode
70 writel(CRE_ENABLE | CRE_DRIVE_CMD, PSRAM_FLASH_CONFIG_REG_0);
71 // Program Refresh Configuration Register (RCR) for BANK0
72 writew(0, (void *)(0x10000000 + PSRAM_RCR_SETUP));
73 // Switch PSRAM controller back to memory mode
74 writel(0, PSRAM_FLASH_CONFIG_REG_0);
77 // Switch PSRAM controller to command mode
78 writel(CRE_ENABLE | CRE_DRIVE_CMD, PSRAM_FLASH_CONFIG_REG_1);
79 // Program Refresh Configuration Register (RCR) for BANK1
80 writew(0, (void *)(0x10800000 + PSRAM_RCR_SETUP));
81 // Switch PSRAM controller back to memory mode
82 writel(0, PSRAM_FLASH_CONFIG_REG_1);
84 printf("PSRAM initialized.\n");
89 #define CREG_BASE 0xF0001000
90 #define CREG_BOOT (void *)(CREG_BASE + 0x0FF0)
91 #define CREG_IP_SW_RESET (void *)(CREG_BASE + 0x0FF0)
92 #define CREG_IP_VERSION (void *)(CREG_BASE + 0x0FF8)
94 /* Bits in CREG_BOOT register */
95 #define CREG_BOOT_WP_BIT BIT(8)
97 void reset_cpu(ulong addr)
99 writel(1, CREG_IP_SW_RESET);
101 ; /* loop forever till reset */
104 static int do_emsdp_rom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
106 u32 creg_boot = readl(CREG_BOOT);
108 if (!strcmp(argv[1], "unlock"))
109 creg_boot &= ~CREG_BOOT_WP_BIT;
110 else if (!strcmp(argv[1], "lock"))
111 creg_boot |= CREG_BOOT_WP_BIT;
113 return CMD_RET_USAGE;
115 writel(creg_boot, CREG_BOOT);
117 return CMD_RET_SUCCESS;
120 cmd_tbl_t cmd_emsdp[] = {
121 U_BOOT_CMD_MKENT(rom, 2, 0, do_emsdp_rom, "", ""),
124 static int do_emsdp(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
128 c = find_cmd_tbl(argv[1], cmd_emsdp, ARRAY_SIZE(cmd_emsdp));
130 /* Strip off leading 'emsdp' command */
134 if (c == NULL || argc > c->maxargs)
135 return CMD_RET_USAGE;
137 return c->cmd(cmdtp, flag, argc, argv);
141 emsdp, CONFIG_SYS_MAXARGS, 0, do_emsdp,
142 "Synopsys EMSDP specific commands",
143 "rom unlock - Unlock non-volatile memory for writing\n"
144 "emsdp rom lock - Lock non-volatile memory to prevent writing\n"
149 int version = readl(CREG_IP_VERSION);
151 printf("Board: ARC EM Software Development Platform v%d.%d\n",
152 (version >> 16) & 0xff, version & 0xff);