board/st/stm32mp1/board.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/ddr.h>
  10 #include <linux/delay.h>
  11 #include <power/pmic.h>
  12 #include <power/stpmic1.h>
  13
  14 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  15 void board_debug_uart_init(void)
  16 {
  17 #if (CONFIG_DEBUG_UART_BASE == STM32_UART4_BASE)
  18
  19 #define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00)
  20 #define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28)
  21
  22         /* UART4 clock enable */
  23         setbits_le32(RCC_MP_APB1ENSETR, BIT(16));
  24
  25 #define GPIOG_BASE 0x50008000
  26         /* GPIOG clock enable */
  27         writel(BIT(6), RCC_MP_AHB4ENSETR);
  28         /* GPIO configuration for EVAL board
  29          * => Uart4 TX = G11
  30          */
  31         writel(0xffbfffff, GPIOG_BASE + 0x00);
  32         writel(0x00006000, GPIOG_BASE + 0x24);
  33 #else
  34
  35 #error("CONFIG_DEBUG_UART_BASE: not supported value")
  36
  37 #endif
  38 }
  39 #endif
  40
  41 #ifdef CONFIG_PMIC_STPMIC1
  42 int board_ddr_power_init(enum ddr_type ddr_type)
  43 {
  44         struct udevice *dev;
  45         bool buck3_at_1800000v = false;
  46         int ret;
  47         u32 buck2;
  48
  49         ret = uclass_get_device_by_driver(UCLASS_PMIC,
  50                                           DM_GET_DRIVER(pmic_stpmic1), &dev);
  51         if (ret)
  52                 /* No PMIC on board */
  53                 return 0;
  54
  55         switch (ddr_type) {
  56         case STM32MP_DDR3:
  57                 /* VTT = Set LDO3 to sync mode */
  58                 ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
  59                 if (ret < 0)
  60                         return ret;
  61
  62                 ret &= ~STPMIC1_LDO3_MODE;
  63                 ret &= ~STPMIC1_LDO12356_VOUT_MASK;
  64                 ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
  65
  66                 ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
  67                                      ret);
  68                 if (ret < 0)
  69                         return ret;
  70
  71                 /* VDD_DDR = Set BUCK2 to 1.35V */
  72                 ret = pmic_clrsetbits(dev,
  73                                       STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
  74                                       STPMIC1_BUCK_VOUT_MASK,
  75                                       STPMIC1_BUCK2_1350000V);
  76                 if (ret < 0)
  77                         return ret;
  78
  79                 /* Enable VDD_DDR = BUCK2 */
  80                 ret = pmic_clrsetbits(dev,
  81                                       STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
  82                                       STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
  83                 if (ret < 0)
  84                         return ret;
  85
  86                 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
  87
  88                 /* Enable VREF */
  89                 ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
  90                                       STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
  91                 if (ret < 0)
  92                         return ret;
  93
  94                 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
  95
  96                 /* Enable VTT = LDO3 */
  97                 ret = pmic_clrsetbits(dev,
  98                                       STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
  99                                       STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
 100                 if (ret < 0)
 101                         return ret;
 102
 103                 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
 104
 105                 break;
 106
 107         case STM32MP_LPDDR2_16:
 108         case STM32MP_LPDDR2_32:
 109         case STM32MP_LPDDR3_16:
 110         case STM32MP_LPDDR3_32:
 111                 /*
 112                  * configure VDD_DDR1 = LDO3
 113                  * Set LDO3 to 1.8V
 114                  * + bypass mode if BUCK3 = 1.8V
 115                  * + normal mode if BUCK3 != 1.8V
 116                  */
 117                 ret = pmic_reg_read(dev,
 118                                     STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK3));
 119                 if (ret < 0)
 120                         return ret;
 121
 122                 if ((ret & STPMIC1_BUCK3_1800000V) == STPMIC1_BUCK3_1800000V)
 123                         buck3_at_1800000v = true;
 124
 125                 ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
 126                 if (ret < 0)
 127                         return ret;
 128
 129                 ret &= ~STPMIC1_LDO3_MODE;
 130                 ret &= ~STPMIC1_LDO12356_VOUT_MASK;
 131                 ret |= STPMIC1_LDO3_1800000;
 132                 if (buck3_at_1800000v)
 133                         ret |= STPMIC1_LDO3_MODE;
 134
 135                 ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
 136                                      ret);
 137                 if (ret < 0)
 138                         return ret;
 139
 140                 /* VDD_DDR2 : Set BUCK2 to 1.2V (16bits) or 1.25V (32 bits)*/
 141                 switch (ddr_type) {
 142                 case STM32MP_LPDDR2_32:
 143                 case STM32MP_LPDDR3_32:
 144                         buck2 = STPMIC1_BUCK2_1250000V;
 145                         break;
 146                 default:
 147                 case STM32MP_LPDDR2_16:
 148                 case STM32MP_LPDDR3_16:
 149                         buck2 = STPMIC1_BUCK2_1200000V;
 150                         break;
 151                 }
 152
 153                 ret = pmic_clrsetbits(dev,
 154                                       STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
 155                                       STPMIC1_BUCK_VOUT_MASK,
 156                                       buck2);
 157                 if (ret < 0)
 158                         return ret;
 159
 160                 /* Enable VDD_DDR1 = LDO3 */
 161                 ret = pmic_clrsetbits(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
 162                                       STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
 163                 if (ret < 0)
 164                         return ret;
 165
 166                 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
 167
 168                 /* Enable VDD_DDR2 =BUCK2 */
 169                 ret = pmic_clrsetbits(dev,
 170                                       STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
 171                                       STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
 172                 if (ret < 0)
 173                         return ret;
 174
 175                 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
 176
 177                 /* Enable VREF */
 178                 ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
 179                                       STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
 180                 if (ret < 0)
 181                         return ret;
 182
 183                 mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
 184
 185                 break;
 186
 187         default:
 188                 break;
 189         };
 190
 191         return 0;
 192 }
 193 #endif