board/solidrun/mx6cuboxi/mx6cuboxi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015 Freescale Semiconductor, Inc.
   4  *
   5  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   6  *
   7  * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
   8  *
   9  * Based on SPL code from Solidrun tree, which is:
  10  * Author: Tungyi Lin <tungyilin1127@gmail.com>
  11  *
  12  * Derived from EDM_CF_IMX6 code by TechNexion,Inc
  13  * Ported to SolidRun microSOM by Rabeeh Khoury <rabeeh@solid-run.com>
  14  */
  15
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/imx-regs.h>
  18 #include <asm/arch/iomux.h>
  19 #include <asm/arch/mx6-pins.h>
  20 #include <asm/arch/mxc_hdmi.h>
  21 #include <env.h>
  22 #include <linux/errno.h>
  23 #include <asm/gpio.h>
  24 #include <asm/mach-imx/iomux-v3.h>
  25 #include <asm/mach-imx/sata.h>
  26 #include <asm/mach-imx/video.h>
  27 #include <mmc.h>
  28 #include <fsl_esdhc_imx.h>
  29 #include <malloc.h>
  30 #include <miiphy.h>
  31 #include <netdev.h>
  32 #include <asm/arch/crm_regs.h>
  33 #include <asm/io.h>
  34 #include <asm/arch/sys_proto.h>
  35 #include <spl.h>
  36 #include <usb.h>
  37 #include <usb/ehci-ci.h>
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  42         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  43         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  44
  45 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  46         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  47         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  48
  49 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  50         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  51
  52 #define ENET_PAD_CTRL_PD  (PAD_CTL_PUS_100K_DOWN |              \
  53         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  54
  55 #define ENET_PAD_CTRL_CLK  ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
  56         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  57
  58 #define ETH_PHY_RESET   IMX_GPIO_NR(4, 15)
  59 #define USB_H1_VBUS     IMX_GPIO_NR(1, 0)
  60
  61 enum board_type {
  62         CUBOXI          = 0x00,
  63         HUMMINGBOARD    = 0x01,
  64         HUMMINGBOARD2   = 0x02,
  65         UNKNOWN         = 0x03,
  66 };
  67
  68 #define MEM_STRIDE 0x4000000
  69 static u32 get_ram_size_stride_test(u32 *base, u32 maxsize)
  70 {
  71         volatile u32 *addr;
  72         u32          save[64];
  73         u32          cnt;
  74         u32          size;
  75         int          i = 0;
  76
  77         /* First save the data */
  78         for (cnt = 0; cnt < maxsize; cnt += MEM_STRIDE) {
  79                 addr = (volatile u32 *)((u32)base + cnt);       /* pointer arith! */
  80                 sync ();
  81                 save[i++] = *addr;
  82                 sync ();
  83         }
  84
  85         /* First write a signature */
  86         * (volatile u32 *)base = 0x12345678;
  87         for (size = MEM_STRIDE; size < maxsize; size += MEM_STRIDE) {
  88                 * (volatile u32 *)((u32)base + size) = size;
  89                 sync ();
  90                 if (* (volatile u32 *)((u32)base) == size) {    /* We reached the overlapping address */
  91                         break;
  92                 }
  93         }
  94
  95         /* Restore the data */
  96         for (cnt = (maxsize - MEM_STRIDE); i > 0; cnt -= MEM_STRIDE) {
  97                 addr = (volatile u32 *)((u32)base + cnt);       /* pointer arith! */
  98                 sync ();
  99                 *addr = save[i--];
 100                 sync ();
 101         }
 102
 103         return (size);
 104 }
 105
 106 int dram_init(void)
 107 {
 108         u32 max_size = imx_ddr_size();
 109
 110         gd->ram_size = get_ram_size_stride_test((u32 *) CONFIG_SYS_SDRAM_BASE,
 111                                                 (u32)max_size);
 112
 113         return 0;
 114 }
 115
 116 static iomux_v3_cfg_t const uart1_pads[] = {
 117         IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 118         IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 119 };
 120
 121 static iomux_v3_cfg_t const usdhc2_pads[] = {
 122         IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 123         IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 124         IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 125         IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 126         IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 127         IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 128 };
 129
 130 static iomux_v3_cfg_t const usdhc3_pads[] = {
 131         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 132         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 133         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 134         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 135         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 136         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 137         IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 138         IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 139         IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 140         IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 141         IOMUX_PADS(PAD_SD3_RST__SD3_RESET       | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 142 };
 143
 144 static iomux_v3_cfg_t const board_detect[] = {
 145         /* These pins are for sensing if it is a CuBox-i or a HummingBoard */
 146         IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 147         IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04   | MUX_PAD_CTRL(UART_PAD_CTRL)),
 148         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 149 };
 150
 151 static iomux_v3_cfg_t const som_rev_detect[] = {
 152         /* These pins are for sensing if it is a CuBox-i or a HummingBoard */
 153         IOMUX_PADS(PAD_CSI0_DAT14__GPIO6_IO00  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 154         IOMUX_PADS(PAD_CSI0_DAT18__GPIO6_IO04  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 155 };
 156
 157 static iomux_v3_cfg_t const usb_pads[] = {
 158         IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 159 };
 160
 161 static void setup_iomux_uart(void)
 162 {
 163         SETUP_IOMUX_PADS(uart1_pads);
 164 }
 165
 166 static struct fsl_esdhc_cfg usdhc_cfg = {
 167         .esdhc_base = USDHC2_BASE_ADDR,
 168         .max_bus_width = 4,
 169 };
 170
 171 static struct fsl_esdhc_cfg emmc_cfg = {
 172         .esdhc_base = USDHC3_BASE_ADDR,
 173         .max_bus_width = 8,
 174 };
 175
 176 int board_mmc_get_env_dev(int devno)
 177 {
 178         return devno - 1;
 179 }
 180
 181 #define USDHC2_CD_GPIO  IMX_GPIO_NR(1, 4)
 182
 183 int board_mmc_getcd(struct mmc *mmc)
 184 {
 185         struct fsl_esdhc_cfg *cfg = mmc->priv;
 186         int ret = 0;
 187
 188         switch (cfg->esdhc_base) {
 189         case USDHC2_BASE_ADDR:
 190                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 191                 break;
 192         case USDHC3_BASE_ADDR:
 193                 ret = (mmc_get_op_cond(mmc) < 0) ? 0 : 1; /* eMMC/uSDHC3 has no CD GPIO */
 194                 break;
 195         }
 196
 197         return ret;
 198 }
 199
 200 static int mmc_init_main(bd_t *bis)
 201 {
 202         int ret;
 203
 204         /*
 205          * Following map is done:
 206          * (U-Boot device node)    (Physical Port)
 207          * mmc0                    Carrier board MicroSD
 208          * mmc1                    SOM eMMC
 209          */
 210         SETUP_IOMUX_PADS(usdhc2_pads);
 211         usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 212         ret = fsl_esdhc_initialize(bis, &usdhc_cfg);
 213         if (ret)
 214                 return ret;
 215
 216         SETUP_IOMUX_PADS(usdhc3_pads);
 217         emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 218         return fsl_esdhc_initialize(bis, &emmc_cfg);
 219 }
 220
 221 static int mmc_init_spl(bd_t *bis)
 222 {
 223         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 224         unsigned reg = readl(&psrc->sbmr1) >> 11;
 225
 226         /*
 227          * Upon reading BOOT_CFG register the following map is done:
 228          * Bit 11 and 12 of BOOT_CFG register can determine the current
 229          * mmc port
 230          * 0x1                  SD2
 231          * 0x2                  SD3
 232          */
 233         switch (reg & 0x3) {
 234         case 0x1:
 235                 SETUP_IOMUX_PADS(usdhc2_pads);
 236                 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 237                 gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
 238                 return fsl_esdhc_initialize(bis, &usdhc_cfg);
 239         case 0x2:
 240                 SETUP_IOMUX_PADS(usdhc3_pads);
 241                 emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 242                 gd->arch.sdhc_clk = emmc_cfg.sdhc_clk;
 243                 return fsl_esdhc_initialize(bis, &emmc_cfg);
 244         }
 245
 246         return -ENODEV;
 247 }
 248
 249 int board_mmc_init(bd_t *bis)
 250 {
 251         if (IS_ENABLED(CONFIG_SPL_BUILD))
 252                 return mmc_init_spl(bis);
 253
 254         return mmc_init_main(bis);
 255 }
 256
 257 static iomux_v3_cfg_t const enet_pads[] = {
 258         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 259         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 260         /* AR8035 reset */
 261         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 262         /* AR8035 interrupt */
 263         IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 264         /* GPIO16 -> AR8035 25MHz */
 265         IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 266         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC       | MUX_PAD_CTRL(NO_PAD_CTRL)),
 267         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 268         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 269         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 270         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 271         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 272         /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
 273         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK)),
 274         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 275         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 276         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 277         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 278         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 279         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 280         IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 281         IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 282 };
 283
 284 static void setup_iomux_enet(void)
 285 {
 286         SETUP_IOMUX_PADS(enet_pads);
 287
 288         gpio_direction_output(ETH_PHY_RESET, 0);
 289         mdelay(10);
 290         gpio_set_value(ETH_PHY_RESET, 1);
 291         udelay(100);
 292 }
 293
 294 int board_phy_config(struct phy_device *phydev)
 295 {
 296         if (phydev->drv->config)
 297                 phydev->drv->config(phydev);
 298
 299         return 0;
 300 }
 301
 302 /* On Cuboxi Ethernet PHY can be located at addresses 0x0 or 0x4 */
 303 #define ETH_PHY_MASK    ((1 << 0x0) | (1 << 0x4))
 304
 305 int board_eth_init(bd_t *bis)
 306 {
 307         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 308         struct mii_dev *bus;
 309         struct phy_device *phydev;
 310
 311         int ret = enable_fec_anatop_clock(0, ENET_25MHZ);
 312         if (ret)
 313                 return ret;
 314
 315         /* set gpr1[ENET_CLK_SEL] */
 316         setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
 317
 318         setup_iomux_enet();
 319
 320         bus = fec_get_miibus(IMX_FEC_BASE, -1);
 321         if (!bus)
 322                 return -EINVAL;
 323
 324         phydev = phy_find_by_mask(bus, ETH_PHY_MASK, PHY_INTERFACE_MODE_RGMII);
 325         if (!phydev) {
 326                 ret = -EINVAL;
 327                 goto free_bus;
 328         }
 329
 330         debug("using phy at address %d\n", phydev->addr);
 331         ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);
 332         if (ret)
 333                 goto free_phydev;
 334
 335         return 0;
 336
 337 free_phydev:
 338         free(phydev);
 339 free_bus:
 340         free(bus);
 341         return ret;
 342 }
 343
 344 #ifdef CONFIG_VIDEO_IPUV3
 345 static void do_enable_hdmi(struct display_info_t const *dev)
 346 {
 347         imx_enable_hdmi_phy();
 348 }
 349
 350 struct display_info_t const displays[] = {
 351         {
 352                 .bus    = -1,
 353                 .addr   = 0,
 354                 .pixfmt = IPU_PIX_FMT_RGB24,
 355                 .detect = detect_hdmi,
 356                 .enable = do_enable_hdmi,
 357                 .mode   = {
 358                         .name           = "HDMI",
 359                         /* 1024x768@60Hz (VESA)*/
 360                         .refresh        = 60,
 361                         .xres           = 1024,
 362                         .yres           = 768,
 363                         .pixclock       = 15384,
 364                         .left_margin    = 160,
 365                         .right_margin   = 24,
 366                         .upper_margin   = 29,
 367                         .lower_margin   = 3,
 368                         .hsync_len      = 136,
 369                         .vsync_len      = 6,
 370                         .sync           = FB_SYNC_EXT,
 371                         .vmode          = FB_VMODE_NONINTERLACED
 372                 }
 373         }
 374 };
 375
 376 size_t display_count = ARRAY_SIZE(displays);
 377
 378 static int setup_display(void)
 379 {
 380         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 381         int reg;
 382         int timeout = 100000;
 383
 384         enable_ipu_clock();
 385         imx_setup_hdmi();
 386
 387         /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
 388         setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 389
 390         reg = readl(&ccm->analog_pll_video);
 391         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 392         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
 393         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 394         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
 395         writel(reg, &ccm->analog_pll_video);
 396
 397         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 398         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 399
 400         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 401         writel(reg, &ccm->analog_pll_video);
 402
 403         while (timeout--)
 404                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 405                         break;
 406         if (timeout < 0) {
 407                 printf("Warning: video pll lock timeout!\n");
 408                 return -ETIMEDOUT;
 409         }
 410
 411         reg = readl(&ccm->analog_pll_video);
 412         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 413         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 414         writel(reg, &ccm->analog_pll_video);
 415
 416         /* gate ipu1_di0_clk */
 417         clrbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 418
 419         /* select video_pll clock / 7  for ipu1_di0_clk -> 65MHz pixclock */
 420         reg = readl(&ccm->chsccdr);
 421         reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
 422                  MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
 423                  MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
 424         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
 425                (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
 426                (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 427         writel(reg, &ccm->chsccdr);
 428
 429         /* enable ipu1_di0_clk */
 430         setbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 431
 432         return 0;
 433 }
 434 #endif /* CONFIG_VIDEO_IPUV3 */
 435
 436 #ifdef CONFIG_USB_EHCI_MX6
 437 static void setup_usb(void)
 438 {
 439         SETUP_IOMUX_PADS(usb_pads);
 440 }
 441
 442 int board_ehci_hcd_init(int port)
 443 {
 444         if (port == 1)
 445                 gpio_direction_output(USB_H1_VBUS, 1);
 446
 447         return 0;
 448 }
 449 #endif
 450
 451 int board_early_init_f(void)
 452 {
 453         setup_iomux_uart();
 454
 455 #ifdef CONFIG_CMD_SATA
 456         setup_sata();
 457 #endif
 458
 459 #ifdef CONFIG_USB_EHCI_MX6
 460         setup_usb();
 461 #endif
 462         return 0;
 463 }
 464
 465 int board_init(void)
 466 {
 467         int ret = 0;
 468
 469         /* address of boot parameters */
 470         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 471
 472 #ifdef CONFIG_VIDEO_IPUV3
 473         ret = setup_display();
 474 #endif
 475
 476         return ret;
 477 }
 478
 479 static enum board_type board_type(void)
 480 {
 481         int val1, val2, val3;
 482
 483         SETUP_IOMUX_PADS(board_detect);
 484
 485         /*
 486          * Machine selection -
 487          * Machine      val1, val2, val3
 488          * ----------------------------
 489          * HB2            x     x    0
 490          * HB rev 3.x     x     0    x
 491          * CBi            0     1    x
 492          * HB             1     1    x
 493          */
 494
 495         gpio_direction_input(IMX_GPIO_NR(2, 8));
 496         val3 = gpio_get_value(IMX_GPIO_NR(2, 8));
 497
 498         if (val3 == 0)
 499                 return HUMMINGBOARD2;
 500
 501         gpio_direction_input(IMX_GPIO_NR(3, 4));
 502         val2 = gpio_get_value(IMX_GPIO_NR(3, 4));
 503
 504         if (val2 == 0)
 505                 return HUMMINGBOARD;
 506
 507         gpio_direction_input(IMX_GPIO_NR(4, 9));
 508         val1 = gpio_get_value(IMX_GPIO_NR(4, 9));
 509
 510         if (val1 == 0) {
 511                 return CUBOXI;
 512         } else {
 513                 return HUMMINGBOARD;
 514         }
 515 }
 516
 517 static bool is_rev_15_som(void)
 518 {
 519         int val1, val2;
 520         SETUP_IOMUX_PADS(som_rev_detect);
 521
 522         val1 = gpio_get_value(IMX_GPIO_NR(6, 0));
 523         val2 = gpio_get_value(IMX_GPIO_NR(6, 4));
 524
 525         if (val1 == 1 && val2 == 0)
 526                 return true;
 527
 528         return false;
 529 }
 530
 531 static bool has_emmc(void)
 532 {
 533         struct mmc *mmc;
 534         mmc = find_mmc_device(1);
 535         if (!mmc)
 536                 return 0;
 537         return (mmc_get_op_cond(mmc) < 0) ? 0 : 1;
 538 }
 539
 540 int checkboard(void)
 541 {
 542         switch (board_type()) {
 543         case CUBOXI:
 544                 puts("Board: MX6 Cubox-i");
 545                 break;
 546         case HUMMINGBOARD:
 547                 puts("Board: MX6 HummingBoard");
 548                 break;
 549         case HUMMINGBOARD2:
 550                 puts("Board: MX6 HummingBoard2");
 551                 break;
 552         case UNKNOWN:
 553         default:
 554                 puts("Board: Unknown\n");
 555                 goto out;
 556         }
 557
 558         if (is_rev_15_som())
 559                 puts(" (som rev 1.5)\n");
 560         else
 561                 puts("\n");
 562
 563 out:
 564         return 0;
 565 }
 566
 567 int board_late_init(void)
 568 {
 569 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 570         switch (board_type()) {
 571         case CUBOXI:
 572                 env_set("board_name", "CUBOXI");
 573                 break;
 574         case HUMMINGBOARD:
 575                 env_set("board_name", "HUMMINGBOARD");
 576                 break;
 577         case HUMMINGBOARD2:
 578                 env_set("board_name", "HUMMINGBOARD2");
 579                 break;
 580         case UNKNOWN:
 581         default:
 582                 env_set("board_name", "CUBOXI");
 583         }
 584
 585         if (is_mx6dq())
 586                 env_set("board_rev", "MX6Q");
 587         else
 588                 env_set("board_rev", "MX6DL");
 589
 590         if (is_rev_15_som())
 591                 env_set("som_rev", "V15");
 592
 593         if (has_emmc())
 594                 env_set("has_emmc", "yes");
 595
 596 #endif
 597
 598         return 0;
 599 }
 600
 601 #ifdef CONFIG_SPL_BUILD
 602 #include <asm/arch/mx6-ddr.h>
 603 static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
 604         .dram_sdclk_0 =  0x00020030,
 605         .dram_sdclk_1 =  0x00020030,
 606         .dram_cas =  0x00020030,
 607         .dram_ras =  0x00020030,
 608         .dram_reset =  0x000c0030,
 609         .dram_sdcke0 =  0x00003000,
 610         .dram_sdcke1 =  0x00003000,
 611         .dram_sdba2 =  0x00000000,
 612         .dram_sdodt0 =  0x00003030,
 613         .dram_sdodt1 =  0x00003030,
 614         .dram_sdqs0 =  0x00000030,
 615         .dram_sdqs1 =  0x00000030,
 616         .dram_sdqs2 =  0x00000030,
 617         .dram_sdqs3 =  0x00000030,
 618         .dram_sdqs4 =  0x00000030,
 619         .dram_sdqs5 =  0x00000030,
 620         .dram_sdqs6 =  0x00000030,
 621         .dram_sdqs7 =  0x00000030,
 622         .dram_dqm0 =  0x00020030,
 623         .dram_dqm1 =  0x00020030,
 624         .dram_dqm2 =  0x00020030,
 625         .dram_dqm3 =  0x00020030,
 626         .dram_dqm4 =  0x00020030,
 627         .dram_dqm5 =  0x00020030,
 628         .dram_dqm6 =  0x00020030,
 629         .dram_dqm7 =  0x00020030,
 630 };
 631
 632 static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
 633         .dram_sdclk_0 = 0x00000028,
 634         .dram_sdclk_1 = 0x00000028,
 635         .dram_cas =     0x00000028,
 636         .dram_ras =     0x00000028,
 637         .dram_reset =   0x000c0028,
 638         .dram_sdcke0 =  0x00003000,
 639         .dram_sdcke1 =  0x00003000,
 640         .dram_sdba2 =   0x00000000,
 641         .dram_sdodt0 =  0x00003030,
 642         .dram_sdodt1 =  0x00003030,
 643         .dram_sdqs0 =   0x00000028,
 644         .dram_sdqs1 =   0x00000028,
 645         .dram_sdqs2 =   0x00000028,
 646         .dram_sdqs3 =   0x00000028,
 647         .dram_sdqs4 =   0x00000028,
 648         .dram_sdqs5 =   0x00000028,
 649         .dram_sdqs6 =   0x00000028,
 650         .dram_sdqs7 =   0x00000028,
 651         .dram_dqm0 =    0x00000028,
 652         .dram_dqm1 =    0x00000028,
 653         .dram_dqm2 =    0x00000028,
 654         .dram_dqm3 =    0x00000028,
 655         .dram_dqm4 =    0x00000028,
 656         .dram_dqm5 =    0x00000028,
 657         .dram_dqm6 =    0x00000028,
 658         .dram_dqm7 =    0x00000028,
 659 };
 660
 661 static const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
 662         .grp_ddr_type =  0x000C0000,
 663         .grp_ddrmode_ctl =  0x00020000,
 664         .grp_ddrpke =  0x00000000,
 665         .grp_addds =  0x00000030,
 666         .grp_ctlds =  0x00000030,
 667         .grp_ddrmode =  0x00020000,
 668         .grp_b0ds =  0x00000030,
 669         .grp_b1ds =  0x00000030,
 670         .grp_b2ds =  0x00000030,
 671         .grp_b3ds =  0x00000030,
 672         .grp_b4ds =  0x00000030,
 673         .grp_b5ds =  0x00000030,
 674         .grp_b6ds =  0x00000030,
 675         .grp_b7ds =  0x00000030,
 676 };
 677
 678 static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 679         .grp_ddr_type = 0x000c0000,
 680         .grp_ddrmode_ctl = 0x00020000,
 681         .grp_ddrpke = 0x00000000,
 682         .grp_addds = 0x00000028,
 683         .grp_ctlds = 0x00000028,
 684         .grp_ddrmode = 0x00020000,
 685         .grp_b0ds = 0x00000028,
 686         .grp_b1ds = 0x00000028,
 687         .grp_b2ds = 0x00000028,
 688         .grp_b3ds = 0x00000028,
 689         .grp_b4ds = 0x00000028,
 690         .grp_b5ds = 0x00000028,
 691         .grp_b6ds = 0x00000028,
 692         .grp_b7ds = 0x00000028,
 693 };
 694
 695 /* microSOM with Dual processor and 1GB memory */
 696 static const struct mx6_mmdc_calibration mx6q_1g_mmcd_calib = {
 697         .p0_mpwldectrl0 =  0x00000000,
 698         .p0_mpwldectrl1 =  0x00000000,
 699         .p1_mpwldectrl0 =  0x00000000,
 700         .p1_mpwldectrl1 =  0x00000000,
 701         .p0_mpdgctrl0 =    0x0314031c,
 702         .p0_mpdgctrl1 =    0x023e0304,
 703         .p1_mpdgctrl0 =    0x03240330,
 704         .p1_mpdgctrl1 =    0x03180260,
 705         .p0_mprddlctl =    0x3630323c,
 706         .p1_mprddlctl =    0x3436283a,
 707         .p0_mpwrdlctl =    0x36344038,
 708         .p1_mpwrdlctl =    0x422a423c,
 709 };
 710
 711 /* microSOM with Quad processor and 2GB memory */
 712 static const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
 713         .p0_mpwldectrl0 =  0x00000000,
 714         .p0_mpwldectrl1 =  0x00000000,
 715         .p1_mpwldectrl0 =  0x00000000,
 716         .p1_mpwldectrl1 =  0x00000000,
 717         .p0_mpdgctrl0 =    0x0314031c,
 718         .p0_mpdgctrl1 =    0x023e0304,
 719         .p1_mpdgctrl0 =    0x03240330,
 720         .p1_mpdgctrl1 =    0x03180260,
 721         .p0_mprddlctl =    0x3630323c,
 722         .p1_mprddlctl =    0x3436283a,
 723         .p0_mpwrdlctl =    0x36344038,
 724         .p1_mpwrdlctl =    0x422a423c,
 725 };
 726
 727 /* microSOM with Solo processor and 512MB memory */
 728 static const struct mx6_mmdc_calibration mx6dl_512m_mmcd_calib = {
 729         .p0_mpwldectrl0 = 0x0045004D,
 730         .p0_mpwldectrl1 = 0x003A0047,
 731         .p0_mpdgctrl0 =   0x023C0224,
 732         .p0_mpdgctrl1 =   0x02000220,
 733         .p0_mprddlctl =   0x44444846,
 734         .p0_mpwrdlctl =   0x32343032,
 735 };
 736
 737 /* microSOM with Dual lite processor and 1GB memory */
 738 static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib = {
 739         .p0_mpwldectrl0 =  0x0045004D,
 740         .p0_mpwldectrl1 =  0x003A0047,
 741         .p1_mpwldectrl0 =  0x001F001F,
 742         .p1_mpwldectrl1 =  0x00210035,
 743         .p0_mpdgctrl0 =    0x023C0224,
 744         .p0_mpdgctrl1 =    0x02000220,
 745         .p1_mpdgctrl0 =    0x02200220,
 746         .p1_mpdgctrl1 =    0x02040208,
 747         .p0_mprddlctl =    0x44444846,
 748         .p1_mprddlctl =    0x4042463C,
 749         .p0_mpwrdlctl =    0x32343032,
 750         .p1_mpwrdlctl =    0x36363430,
 751 };
 752
 753 static struct mx6_ddr3_cfg mem_ddr_2g = {
 754         .mem_speed = 1600,
 755         .density   = 2,
 756         .width     = 16,
 757         .banks     = 8,
 758         .rowaddr   = 14,
 759         .coladdr   = 10,
 760         .pagesz    = 2,
 761         .trcd      = 1375,
 762         .trcmin    = 4875,
 763         .trasmin   = 3500,
 764 };
 765
 766 static struct mx6_ddr3_cfg mem_ddr_4g = {
 767         .mem_speed = 1600,
 768         .density = 4,
 769         .width = 16,
 770         .banks = 8,
 771         .rowaddr = 16,
 772         .coladdr = 10,
 773         .pagesz = 2,
 774         .trcd = 1375,
 775         .trcmin = 4875,
 776         .trasmin = 3500,
 777 };
 778
 779 static void ccgr_init(void)
 780 {
 781         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 782
 783         writel(0x00C03F3F, &ccm->CCGR0);
 784         writel(0x0030FC03, &ccm->CCGR1);
 785         writel(0x0FFFC000, &ccm->CCGR2);
 786         writel(0x3FF00000, &ccm->CCGR3);
 787         writel(0x00FFF300, &ccm->CCGR4);
 788         writel(0x0F0000C3, &ccm->CCGR5);
 789         writel(0x000003FF, &ccm->CCGR6);
 790 }
 791
 792 static void spl_dram_init(int width)
 793 {
 794         struct mx6_ddr_sysinfo sysinfo = {
 795                 /* width of data bus: 0=16, 1=32, 2=64 */
 796                 .dsize = width / 32,
 797                 /* config for full 4GB range so that get_mem_size() works */
 798                 .cs_density = 32,       /* 32Gb per CS */
 799                 .ncs = 1,               /* single chip select */
 800                 .cs1_mirror = 0,
 801                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 802                 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/,       /* RTT_Nom = RZQ/4 */
 803                 .walat = 1,     /* Write additional latency */
 804                 .ralat = 5,     /* Read additional latency */
 805                 .mif3_mode = 3, /* Command prediction working mode */
 806                 .bi_on = 1,     /* Bank interleaving enabled */
 807                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 808                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 809                 .ddr_type = DDR_TYPE_DDR3,
 810                 .refsel = 1,    /* Refresh cycles at 32KHz */
 811                 .refr = 7,      /* 8 refresh commands per refresh cycle */
 812         };
 813
 814         if (is_mx6dq())
 815                 mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
 816         else
 817                 mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
 818
 819         if (is_cpu_type(MXC_CPU_MX6D))
 820                 mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g);
 821         else if (is_cpu_type(MXC_CPU_MX6Q))
 822                 mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
 823         else if (is_cpu_type(MXC_CPU_MX6DL))
 824                 mx6_dram_cfg(&sysinfo, &mx6dl_1g_mmcd_calib, &mem_ddr_2g);
 825         else if (is_cpu_type(MXC_CPU_MX6SOLO))
 826                 mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g);
 827 }
 828
 829 void board_init_f(ulong dummy)
 830 {
 831         /* setup AIPS and disable watchdog */
 832         arch_cpu_init();
 833
 834         ccgr_init();
 835         gpr_init();
 836
 837         /* iomux and setup of i2c */
 838         board_early_init_f();
 839
 840         /* setup GP timer */
 841         timer_init();
 842
 843         /* UART clocks enabled and gd valid - init serial console */
 844         preloader_console_init();
 845
 846         /* DDR initialization */
 847         if (is_cpu_type(MXC_CPU_MX6SOLO))
 848                 spl_dram_init(32);
 849         else
 850                 spl_dram_init(64);
 851
 852         /* Clear the BSS. */
 853         memset(__bss_start, 0, __bss_end - __bss_start);
 854
 855         /* load/boot image from boot device */
 856         board_init_r(NULL, 0);
 857 }
 858 #endif