board/solidrun/mx6cuboxi/mx6cuboxi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015 Freescale Semiconductor, Inc.
   4  *
   5  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   6  *
   7  * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
   8  *
   9  * Based on SPL code from Solidrun tree, which is:
  10  * Author: Tungyi Lin <tungyilin1127@gmail.com>
  11  *
  12  * Derived from EDM_CF_IMX6 code by TechNexion,Inc
  13  * Ported to SolidRun microSOM by Rabeeh Khoury <rabeeh@solid-run.com>
  14  */
  15
  16 #include <common.h>
  17 #include <image.h>
  18 #include <init.h>
  19 #include <log.h>
  20 #include <net.h>
  21 #include <asm/arch/clock.h>
  22 #include <asm/arch/imx-regs.h>
  23 #include <asm/arch/iomux.h>
  24 #include <asm/arch/mx6-pins.h>
  25 #include <asm/arch/mxc_hdmi.h>
  26 #include <env.h>
  27 #include <linux/errno.h>
  28 #include <asm/gpio.h>
  29 #include <asm/mach-imx/iomux-v3.h>
  30 #include <asm/mach-imx/sata.h>
  31 #include <asm/mach-imx/video.h>
  32 #include <mmc.h>
  33 #include <fsl_esdhc_imx.h>
  34 #include <malloc.h>
  35 #include <miiphy.h>
  36 #include <netdev.h>
  37 #include <asm/arch/crm_regs.h>
  38 #include <asm/io.h>
  39 #include <asm/arch/sys_proto.h>
  40 #include <spl.h>
  41 #include <usb.h>
  42 #include <usb/ehci-ci.h>
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  47         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  48         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  49
  50 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  51         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  52         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  53
  54 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  55         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  56
  57 #define ENET_PAD_CTRL_PD  (PAD_CTL_PUS_100K_DOWN |              \
  58         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  59
  60 #define ENET_PAD_CTRL_CLK  ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
  61         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  62
  63 #define ETH_PHY_RESET   IMX_GPIO_NR(4, 15)
  64 #define USB_H1_VBUS     IMX_GPIO_NR(1, 0)
  65
  66 enum board_type {
  67         CUBOXI          = 0x00,
  68         HUMMINGBOARD    = 0x01,
  69         HUMMINGBOARD2   = 0x02,
  70         UNKNOWN         = 0x03,
  71 };
  72
  73 static struct gpio_desc board_detect_desc[5];
  74
  75 #define MEM_STRIDE 0x4000000
  76 static u32 get_ram_size_stride_test(u32 *base, u32 maxsize)
  77 {
  78         volatile u32 *addr;
  79         u32          save[64];
  80         u32          cnt;
  81         u32          size;
  82         int          i = 0;
  83
  84         /* First save the data */
  85         for (cnt = 0; cnt < maxsize; cnt += MEM_STRIDE) {
  86                 addr = (volatile u32 *)((u32)base + cnt);       /* pointer arith! */
  87                 sync ();
  88                 save[i++] = *addr;
  89                 sync ();
  90         }
  91
  92         /* First write a signature */
  93         * (volatile u32 *)base = 0x12345678;
  94         for (size = MEM_STRIDE; size < maxsize; size += MEM_STRIDE) {
  95                 * (volatile u32 *)((u32)base + size) = size;
  96                 sync ();
  97                 if (* (volatile u32 *)((u32)base) == size) {    /* We reached the overlapping address */
  98                         break;
  99                 }
 100         }
 101
 102         /* Restore the data */
 103         for (cnt = (maxsize - MEM_STRIDE); i > 0; cnt -= MEM_STRIDE) {
 104                 addr = (volatile u32 *)((u32)base + cnt);       /* pointer arith! */
 105                 sync ();
 106                 *addr = save[i--];
 107                 sync ();
 108         }
 109
 110         return (size);
 111 }
 112
 113 int dram_init(void)
 114 {
 115         u32 max_size = imx_ddr_size();
 116
 117         gd->ram_size = get_ram_size_stride_test((u32 *) CONFIG_SYS_SDRAM_BASE,
 118                                                 (u32)max_size);
 119
 120         return 0;
 121 }
 122
 123 static iomux_v3_cfg_t const uart1_pads[] = {
 124         IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 125         IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 126 };
 127
 128 static iomux_v3_cfg_t const usdhc2_pads[] = {
 129         IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 130         IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 131         IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 132         IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 133         IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 134         IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 135 };
 136
 137 static iomux_v3_cfg_t const usdhc3_pads[] = {
 138         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 139         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 140         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 141         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 142         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 143         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 144         IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 145         IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 146         IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 147         IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 148         IOMUX_PADS(PAD_SD3_RST__SD3_RESET       | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 149 };
 150
 151 static iomux_v3_cfg_t const board_detect[] = {
 152         /* These pins are for sensing if it is a CuBox-i or a HummingBoard */
 153         IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 154         IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04   | MUX_PAD_CTRL(UART_PAD_CTRL)),
 155         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 156 };
 157
 158 static iomux_v3_cfg_t const som_rev_detect[] = {
 159         /* These pins are for sensing if it is a CuBox-i or a HummingBoard */
 160         IOMUX_PADS(PAD_CSI0_DAT14__GPIO6_IO00  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 161         IOMUX_PADS(PAD_CSI0_DAT18__GPIO6_IO04  | MUX_PAD_CTRL(UART_PAD_CTRL)),
 162 };
 163
 164 static void setup_iomux_uart(void)
 165 {
 166         SETUP_IOMUX_PADS(uart1_pads);
 167 }
 168
 169 static struct fsl_esdhc_cfg usdhc_cfg = {
 170         .esdhc_base = USDHC2_BASE_ADDR,
 171         .max_bus_width = 4,
 172 };
 173
 174 static struct fsl_esdhc_cfg emmc_cfg = {
 175         .esdhc_base = USDHC3_BASE_ADDR,
 176         .max_bus_width = 8,
 177 };
 178
 179 int board_mmc_get_env_dev(int devno)
 180 {
 181         return devno;
 182 }
 183
 184 #define USDHC2_CD_GPIO  IMX_GPIO_NR(1, 4)
 185
 186 int board_mmc_getcd(struct mmc *mmc)
 187 {
 188         struct fsl_esdhc_cfg *cfg = mmc->priv;
 189         int ret = 0;
 190
 191         switch (cfg->esdhc_base) {
 192         case USDHC2_BASE_ADDR:
 193                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 194                 break;
 195         case USDHC3_BASE_ADDR:
 196                 ret = (mmc_get_op_cond(mmc) < 0) ? 0 : 1; /* eMMC/uSDHC3 has no CD GPIO */
 197                 break;
 198         }
 199
 200         return ret;
 201 }
 202
 203 static int mmc_init_spl(bd_t *bis)
 204 {
 205         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 206         unsigned reg = readl(&psrc->sbmr1) >> 11;
 207
 208         /*
 209          * Upon reading BOOT_CFG register the following map is done:
 210          * Bit 11 and 12 of BOOT_CFG register can determine the current
 211          * mmc port
 212          * 0x1                  SD2
 213          * 0x2                  SD3
 214          */
 215         switch (reg & 0x3) {
 216         case 0x1:
 217                 SETUP_IOMUX_PADS(usdhc2_pads);
 218                 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 219                 gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
 220                 return fsl_esdhc_initialize(bis, &usdhc_cfg);
 221         case 0x2:
 222                 SETUP_IOMUX_PADS(usdhc3_pads);
 223                 emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 224                 gd->arch.sdhc_clk = emmc_cfg.sdhc_clk;
 225                 return fsl_esdhc_initialize(bis, &emmc_cfg);
 226         }
 227
 228         return -ENODEV;
 229 }
 230
 231 int board_mmc_init(bd_t *bis)
 232 {
 233         if (IS_ENABLED(CONFIG_SPL_BUILD))
 234                 return mmc_init_spl(bis);
 235
 236         return 0;
 237 }
 238
 239 static iomux_v3_cfg_t const enet_pads[] = {
 240         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 241         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 242         /* AR8035 reset */
 243         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 244         /* AR8035 interrupt */
 245         IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 246         /* GPIO16 -> AR8035 25MHz */
 247         IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 248         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC       | MUX_PAD_CTRL(NO_PAD_CTRL)),
 249         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 250         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 251         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 252         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 253         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 254         /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
 255         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK)),
 256         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 257         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 258         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 259         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 260         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 261         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 262         IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 263         IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 264 };
 265
 266 static void setup_iomux_enet(void)
 267 {
 268         struct gpio_desc desc;
 269         int ret;
 270
 271         SETUP_IOMUX_PADS(enet_pads);
 272
 273         ret = dm_gpio_lookup_name("GPIO4_15", &desc);
 274         if (ret) {
 275                 printf("%s: phy reset lookup failed\n", __func__);
 276                 return;
 277         }
 278
 279         ret = dm_gpio_request(&desc, "phy-reset");
 280         if (ret) {
 281                 printf("%s: phy reset request failed\n", __func__);
 282                 return;
 283         }
 284
 285         gpio_direction_output(ETH_PHY_RESET, 0);
 286         mdelay(10);
 287         gpio_set_value(ETH_PHY_RESET, 1);
 288         udelay(100);
 289
 290         gpio_free_list_nodev(&desc, 1);
 291 }
 292
 293 int board_phy_config(struct phy_device *phydev)
 294 {
 295         if (phydev->drv->config)
 296                 phydev->drv->config(phydev);
 297
 298         return 0;
 299 }
 300
 301 /* On Cuboxi Ethernet PHY can be located at addresses 0x0 or 0x4 */
 302 #define ETH_PHY_MASK    ((1 << 0x0) | (1 << 0x4))
 303
 304 int board_eth_init(bd_t *bis)
 305 {
 306         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 307         struct mii_dev *bus;
 308         struct phy_device *phydev;
 309
 310         int ret = enable_fec_anatop_clock(0, ENET_25MHZ);
 311         if (ret)
 312                 return ret;
 313
 314         /* set gpr1[ENET_CLK_SEL] */
 315         setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
 316
 317         setup_iomux_enet();
 318
 319         bus = fec_get_miibus(IMX_FEC_BASE, -1);
 320         if (!bus)
 321                 return -EINVAL;
 322
 323         phydev = phy_find_by_mask(bus, ETH_PHY_MASK, PHY_INTERFACE_MODE_RGMII);
 324         if (!phydev) {
 325                 ret = -EINVAL;
 326                 goto free_bus;
 327         }
 328
 329         debug("using phy at address %d\n", phydev->addr);
 330         ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);
 331         if (ret)
 332                 goto free_phydev;
 333
 334         return 0;
 335
 336 free_phydev:
 337         free(phydev);
 338 free_bus:
 339         free(bus);
 340         return ret;
 341 }
 342
 343 #ifdef CONFIG_VIDEO_IPUV3
 344 static void do_enable_hdmi(struct display_info_t const *dev)
 345 {
 346         imx_enable_hdmi_phy();
 347 }
 348
 349 struct display_info_t const displays[] = {
 350         {
 351                 .bus    = -1,
 352                 .addr   = 0,
 353                 .pixfmt = IPU_PIX_FMT_RGB24,
 354                 .detect = detect_hdmi,
 355                 .enable = do_enable_hdmi,
 356                 .mode   = {
 357                         .name           = "HDMI",
 358                         /* 1024x768@60Hz (VESA)*/
 359                         .refresh        = 60,
 360                         .xres           = 1024,
 361                         .yres           = 768,
 362                         .pixclock       = 15384,
 363                         .left_margin    = 160,
 364                         .right_margin   = 24,
 365                         .upper_margin   = 29,
 366                         .lower_margin   = 3,
 367                         .hsync_len      = 136,
 368                         .vsync_len      = 6,
 369                         .sync           = FB_SYNC_EXT,
 370                         .vmode          = FB_VMODE_NONINTERLACED
 371                 }
 372         }
 373 };
 374
 375 size_t display_count = ARRAY_SIZE(displays);
 376
 377 static int setup_display(void)
 378 {
 379         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 380         int reg;
 381         int timeout = 100000;
 382
 383         enable_ipu_clock();
 384         imx_setup_hdmi();
 385
 386         /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
 387         setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 388
 389         reg = readl(&ccm->analog_pll_video);
 390         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 391         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
 392         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 393         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
 394         writel(reg, &ccm->analog_pll_video);
 395
 396         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 397         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 398
 399         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 400         writel(reg, &ccm->analog_pll_video);
 401
 402         while (timeout--)
 403                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 404                         break;
 405         if (timeout < 0) {
 406                 printf("Warning: video pll lock timeout!\n");
 407                 return -ETIMEDOUT;
 408         }
 409
 410         reg = readl(&ccm->analog_pll_video);
 411         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 412         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 413         writel(reg, &ccm->analog_pll_video);
 414
 415         /* gate ipu1_di0_clk */
 416         clrbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 417
 418         /* select video_pll clock / 7  for ipu1_di0_clk -> 65MHz pixclock */
 419         reg = readl(&ccm->chsccdr);
 420         reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
 421                  MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
 422                  MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
 423         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
 424                (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
 425                (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 426         writel(reg, &ccm->chsccdr);
 427
 428         /* enable ipu1_di0_clk */
 429         setbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 430
 431         return 0;
 432 }
 433 #endif /* CONFIG_VIDEO_IPUV3 */
 434
 435 int board_early_init_f(void)
 436 {
 437         setup_iomux_uart();
 438
 439 #ifdef CONFIG_CMD_SATA
 440         setup_sata();
 441 #endif
 442         return 0;
 443 }
 444
 445 int board_init(void)
 446 {
 447         int ret = 0;
 448
 449         /* address of boot parameters */
 450         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 451
 452 #ifdef CONFIG_VIDEO_IPUV3
 453         ret = setup_display();
 454 #endif
 455
 456         return ret;
 457 }
 458
 459 static int request_detect_gpios(void)
 460 {
 461         int node;
 462         int ret;
 463
 464         node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
 465                 "solidrun,hummingboard-detect");
 466         if (node < 0)
 467                 return -ENODEV;
 468
 469         ret = gpio_request_list_by_name_nodev(offset_to_ofnode(node),
 470                 "detect-gpios", board_detect_desc,
 471                 ARRAY_SIZE(board_detect_desc), GPIOD_IS_IN);
 472
 473         return ret;
 474 }
 475
 476 static int free_detect_gpios(void)
 477 {
 478         return gpio_free_list_nodev(board_detect_desc,
 479                 ARRAY_SIZE(board_detect_desc));
 480 }
 481
 482 static enum board_type board_type(void)
 483 {
 484         int val1, val2, val3;
 485
 486         SETUP_IOMUX_PADS(board_detect);
 487
 488         /*
 489          * Machine selection -
 490          * Machine      val1, val2, val3
 491          * ----------------------------
 492          * HB2            x     x    0
 493          * HB rev 3.x     x     0    x
 494          * CBi            0     1    x
 495          * HB             1     1    x
 496          */
 497
 498         gpio_direction_input(IMX_GPIO_NR(2, 8));
 499         val3 = gpio_get_value(IMX_GPIO_NR(2, 8));
 500
 501         if (val3 == 0)
 502                 return HUMMINGBOARD2;
 503
 504         gpio_direction_input(IMX_GPIO_NR(3, 4));
 505         val2 = gpio_get_value(IMX_GPIO_NR(3, 4));
 506
 507         if (val2 == 0)
 508                 return HUMMINGBOARD;
 509
 510         gpio_direction_input(IMX_GPIO_NR(4, 9));
 511         val1 = gpio_get_value(IMX_GPIO_NR(4, 9));
 512
 513         if (val1 == 0) {
 514                 return CUBOXI;
 515         } else {
 516                 return HUMMINGBOARD;
 517         }
 518 }
 519
 520 static bool is_rev_15_som(void)
 521 {
 522         int val1, val2;
 523         SETUP_IOMUX_PADS(som_rev_detect);
 524
 525         val1 = gpio_get_value(IMX_GPIO_NR(6, 0));
 526         val2 = gpio_get_value(IMX_GPIO_NR(6, 4));
 527
 528         if (val1 == 1 && val2 == 0)
 529                 return true;
 530
 531         return false;
 532 }
 533
 534 static bool has_emmc(void)
 535 {
 536         struct mmc *mmc;
 537         mmc = find_mmc_device(2);
 538         if (!mmc)
 539                 return 0;
 540         return (mmc_get_op_cond(mmc) < 0) ? 0 : 1;
 541 }
 542
 543 int checkboard(void)
 544 {
 545         request_detect_gpios();
 546
 547         switch (board_type()) {
 548         case CUBOXI:
 549                 puts("Board: MX6 Cubox-i");
 550                 break;
 551         case HUMMINGBOARD:
 552                 puts("Board: MX6 HummingBoard");
 553                 break;
 554         case HUMMINGBOARD2:
 555                 puts("Board: MX6 HummingBoard2");
 556                 break;
 557         case UNKNOWN:
 558         default:
 559                 puts("Board: Unknown\n");
 560                 goto out;
 561         }
 562
 563         if (is_rev_15_som())
 564                 puts(" (som rev 1.5)\n");
 565         else
 566                 puts("\n");
 567
 568         free_detect_gpios();
 569 out:
 570         return 0;
 571 }
 572
 573 /* Override the default implementation, DT model is not accurate */
 574 int show_board_info(void)
 575 {
 576         return checkboard();
 577 }
 578
 579 int board_late_init(void)
 580 {
 581 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 582         request_detect_gpios();
 583
 584         switch (board_type()) {
 585         case CUBOXI:
 586                 env_set("board_name", "CUBOXI");
 587                 break;
 588         case HUMMINGBOARD:
 589                 env_set("board_name", "HUMMINGBOARD");
 590                 break;
 591         case HUMMINGBOARD2:
 592                 env_set("board_name", "HUMMINGBOARD2");
 593                 break;
 594         case UNKNOWN:
 595         default:
 596                 env_set("board_name", "CUBOXI");
 597         }
 598
 599         if (is_mx6dq())
 600                 env_set("board_rev", "MX6Q");
 601         else
 602                 env_set("board_rev", "MX6DL");
 603
 604         if (is_rev_15_som())
 605                 env_set("som_rev", "V15");
 606
 607         if (has_emmc())
 608                 env_set("has_emmc", "yes");
 609
 610         free_detect_gpios();
 611 #endif
 612
 613         return 0;
 614 }
 615
 616 /*
 617  * This is not a perfect match. Avoid dependency on the DM GPIO driver needed
 618  * for accurate board detection. Hummingboard2 DT is good enough for U-Boot on
 619  * all Hummingboard/Cubox-i platforms.
 620  */
 621 int board_fit_config_name_match(const char *name)
 622 {
 623         char tmp_name[36];
 624
 625         snprintf(tmp_name, sizeof(tmp_name), "%s-hummingboard2-emmc-som-v15",
 626                         is_mx6dq() ? "imx6q" : "imx6dl");
 627
 628         return strcmp(name, tmp_name);
 629 }
 630
 631 #ifdef CONFIG_SPL_BUILD
 632 #include <asm/arch/mx6-ddr.h>
 633 static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
 634         .dram_sdclk_0 =  0x00020030,
 635         .dram_sdclk_1 =  0x00020030,
 636         .dram_cas =  0x00020030,
 637         .dram_ras =  0x00020030,
 638         .dram_reset =  0x000c0030,
 639         .dram_sdcke0 =  0x00003000,
 640         .dram_sdcke1 =  0x00003000,
 641         .dram_sdba2 =  0x00000000,
 642         .dram_sdodt0 =  0x00003030,
 643         .dram_sdodt1 =  0x00003030,
 644         .dram_sdqs0 =  0x00000030,
 645         .dram_sdqs1 =  0x00000030,
 646         .dram_sdqs2 =  0x00000030,
 647         .dram_sdqs3 =  0x00000030,
 648         .dram_sdqs4 =  0x00000030,
 649         .dram_sdqs5 =  0x00000030,
 650         .dram_sdqs6 =  0x00000030,
 651         .dram_sdqs7 =  0x00000030,
 652         .dram_dqm0 =  0x00020030,
 653         .dram_dqm1 =  0x00020030,
 654         .dram_dqm2 =  0x00020030,
 655         .dram_dqm3 =  0x00020030,
 656         .dram_dqm4 =  0x00020030,
 657         .dram_dqm5 =  0x00020030,
 658         .dram_dqm6 =  0x00020030,
 659         .dram_dqm7 =  0x00020030,
 660 };
 661
 662 static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
 663         .dram_sdclk_0 = 0x00000028,
 664         .dram_sdclk_1 = 0x00000028,
 665         .dram_cas =     0x00000028,
 666         .dram_ras =     0x00000028,
 667         .dram_reset =   0x000c0028,
 668         .dram_sdcke0 =  0x00003000,
 669         .dram_sdcke1 =  0x00003000,
 670         .dram_sdba2 =   0x00000000,
 671         .dram_sdodt0 =  0x00003030,
 672         .dram_sdodt1 =  0x00003030,
 673         .dram_sdqs0 =   0x00000028,
 674         .dram_sdqs1 =   0x00000028,
 675         .dram_sdqs2 =   0x00000028,
 676         .dram_sdqs3 =   0x00000028,
 677         .dram_sdqs4 =   0x00000028,
 678         .dram_sdqs5 =   0x00000028,
 679         .dram_sdqs6 =   0x00000028,
 680         .dram_sdqs7 =   0x00000028,
 681         .dram_dqm0 =    0x00000028,
 682         .dram_dqm1 =    0x00000028,
 683         .dram_dqm2 =    0x00000028,
 684         .dram_dqm3 =    0x00000028,
 685         .dram_dqm4 =    0x00000028,
 686         .dram_dqm5 =    0x00000028,
 687         .dram_dqm6 =    0x00000028,
 688         .dram_dqm7 =    0x00000028,
 689 };
 690
 691 static const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
 692         .grp_ddr_type =  0x000C0000,
 693         .grp_ddrmode_ctl =  0x00020000,
 694         .grp_ddrpke =  0x00000000,
 695         .grp_addds =  0x00000030,
 696         .grp_ctlds =  0x00000030,
 697         .grp_ddrmode =  0x00020000,
 698         .grp_b0ds =  0x00000030,
 699         .grp_b1ds =  0x00000030,
 700         .grp_b2ds =  0x00000030,
 701         .grp_b3ds =  0x00000030,
 702         .grp_b4ds =  0x00000030,
 703         .grp_b5ds =  0x00000030,
 704         .grp_b6ds =  0x00000030,
 705         .grp_b7ds =  0x00000030,
 706 };
 707
 708 static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 709         .grp_ddr_type = 0x000c0000,
 710         .grp_ddrmode_ctl = 0x00020000,
 711         .grp_ddrpke = 0x00000000,
 712         .grp_addds = 0x00000028,
 713         .grp_ctlds = 0x00000028,
 714         .grp_ddrmode = 0x00020000,
 715         .grp_b0ds = 0x00000028,
 716         .grp_b1ds = 0x00000028,
 717         .grp_b2ds = 0x00000028,
 718         .grp_b3ds = 0x00000028,
 719         .grp_b4ds = 0x00000028,
 720         .grp_b5ds = 0x00000028,
 721         .grp_b6ds = 0x00000028,
 722         .grp_b7ds = 0x00000028,
 723 };
 724
 725 /* microSOM with Dual processor and 1GB memory */
 726 static const struct mx6_mmdc_calibration mx6q_1g_mmcd_calib = {
 727         .p0_mpwldectrl0 =  0x00000000,
 728         .p0_mpwldectrl1 =  0x00000000,
 729         .p1_mpwldectrl0 =  0x00000000,
 730         .p1_mpwldectrl1 =  0x00000000,
 731         .p0_mpdgctrl0 =    0x0314031c,
 732         .p0_mpdgctrl1 =    0x023e0304,
 733         .p1_mpdgctrl0 =    0x03240330,
 734         .p1_mpdgctrl1 =    0x03180260,
 735         .p0_mprddlctl =    0x3630323c,
 736         .p1_mprddlctl =    0x3436283a,
 737         .p0_mpwrdlctl =    0x36344038,
 738         .p1_mpwrdlctl =    0x422a423c,
 739 };
 740
 741 /* microSOM with Quad processor and 2GB memory */
 742 static const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
 743         .p0_mpwldectrl0 =  0x00000000,
 744         .p0_mpwldectrl1 =  0x00000000,
 745         .p1_mpwldectrl0 =  0x00000000,
 746         .p1_mpwldectrl1 =  0x00000000,
 747         .p0_mpdgctrl0 =    0x0314031c,
 748         .p0_mpdgctrl1 =    0x023e0304,
 749         .p1_mpdgctrl0 =    0x03240330,
 750         .p1_mpdgctrl1 =    0x03180260,
 751         .p0_mprddlctl =    0x3630323c,
 752         .p1_mprddlctl =    0x3436283a,
 753         .p0_mpwrdlctl =    0x36344038,
 754         .p1_mpwrdlctl =    0x422a423c,
 755 };
 756
 757 /* microSOM with Solo processor and 512MB memory */
 758 static const struct mx6_mmdc_calibration mx6dl_512m_mmcd_calib = {
 759         .p0_mpwldectrl0 = 0x0045004D,
 760         .p0_mpwldectrl1 = 0x003A0047,
 761         .p0_mpdgctrl0 =   0x023C0224,
 762         .p0_mpdgctrl1 =   0x02000220,
 763         .p0_mprddlctl =   0x44444846,
 764         .p0_mpwrdlctl =   0x32343032,
 765 };
 766
 767 /* microSOM with Dual lite processor and 1GB memory */
 768 static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib = {
 769         .p0_mpwldectrl0 =  0x0045004D,
 770         .p0_mpwldectrl1 =  0x003A0047,
 771         .p1_mpwldectrl0 =  0x001F001F,
 772         .p1_mpwldectrl1 =  0x00210035,
 773         .p0_mpdgctrl0 =    0x023C0224,
 774         .p0_mpdgctrl1 =    0x02000220,
 775         .p1_mpdgctrl0 =    0x02200220,
 776         .p1_mpdgctrl1 =    0x02040208,
 777         .p0_mprddlctl =    0x44444846,
 778         .p1_mprddlctl =    0x4042463C,
 779         .p0_mpwrdlctl =    0x32343032,
 780         .p1_mpwrdlctl =    0x36363430,
 781 };
 782
 783 static struct mx6_ddr3_cfg mem_ddr_2g = {
 784         .mem_speed = 1600,
 785         .density   = 2,
 786         .width     = 16,
 787         .banks     = 8,
 788         .rowaddr   = 14,
 789         .coladdr   = 10,
 790         .pagesz    = 2,
 791         .trcd      = 1375,
 792         .trcmin    = 4875,
 793         .trasmin   = 3500,
 794 };
 795
 796 static struct mx6_ddr3_cfg mem_ddr_4g = {
 797         .mem_speed = 1600,
 798         .density = 4,
 799         .width = 16,
 800         .banks = 8,
 801         .rowaddr = 16,
 802         .coladdr = 10,
 803         .pagesz = 2,
 804         .trcd = 1375,
 805         .trcmin = 4875,
 806         .trasmin = 3500,
 807 };
 808
 809 static void ccgr_init(void)
 810 {
 811         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 812
 813         writel(0x00C03F3F, &ccm->CCGR0);
 814         writel(0x0030FC03, &ccm->CCGR1);
 815         writel(0x0FFFC000, &ccm->CCGR2);
 816         writel(0x3FF00000, &ccm->CCGR3);
 817         writel(0x00FFF300, &ccm->CCGR4);
 818         writel(0x0F0000C3, &ccm->CCGR5);
 819         writel(0x000003FF, &ccm->CCGR6);
 820 }
 821
 822 static void spl_dram_init(int width)
 823 {
 824         struct mx6_ddr_sysinfo sysinfo = {
 825                 /* width of data bus: 0=16, 1=32, 2=64 */
 826                 .dsize = width / 32,
 827                 /* config for full 4GB range so that get_mem_size() works */
 828                 .cs_density = 32,       /* 32Gb per CS */
 829                 .ncs = 1,               /* single chip select */
 830                 .cs1_mirror = 0,
 831                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 832                 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/,       /* RTT_Nom = RZQ/4 */
 833                 .walat = 1,     /* Write additional latency */
 834                 .ralat = 5,     /* Read additional latency */
 835                 .mif3_mode = 3, /* Command prediction working mode */
 836                 .bi_on = 1,     /* Bank interleaving enabled */
 837                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 838                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 839                 .ddr_type = DDR_TYPE_DDR3,
 840                 .refsel = 1,    /* Refresh cycles at 32KHz */
 841                 .refr = 7,      /* 8 refresh commands per refresh cycle */
 842         };
 843
 844         if (is_mx6dq())
 845                 mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
 846         else
 847                 mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
 848
 849         if (is_cpu_type(MXC_CPU_MX6D))
 850                 mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g);
 851         else if (is_cpu_type(MXC_CPU_MX6Q))
 852                 mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
 853         else if (is_cpu_type(MXC_CPU_MX6DL))
 854                 mx6_dram_cfg(&sysinfo, &mx6dl_1g_mmcd_calib, &mem_ddr_2g);
 855         else if (is_cpu_type(MXC_CPU_MX6SOLO))
 856                 mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g);
 857 }
 858
 859 void board_init_f(ulong dummy)
 860 {
 861         /* setup AIPS and disable watchdog */
 862         arch_cpu_init();
 863
 864         ccgr_init();
 865         gpr_init();
 866
 867         /* iomux and setup of i2c */
 868         board_early_init_f();
 869
 870         /* setup GP timer */
 871         timer_init();
 872
 873         /* UART clocks enabled and gd valid - init serial console */
 874         preloader_console_init();
 875
 876         /* DDR initialization */
 877         if (is_cpu_type(MXC_CPU_MX6SOLO))
 878                 spl_dram_init(32);
 879         else
 880                 spl_dram_init(64);
 881
 882         /* Clear the BSS. */
 883         memset(__bss_start, 0, __bss_end - __bss_start);
 884
 885         /* load/boot image from boot device */
 886         board_init_r(NULL, 0);
 887 }
 888 #endif