board/softing/vining_2000/vining_2000.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 samtec automotive software & electronics gmbh
   4  * Copyright (C) 2017-2019 softing automotive electronics gmbH
   5  *
   6  * Author: Christoph Fritz <chf.fritz@googlemail.com>
   7  */
   8
   9 #include <init.h>
  10 #include <net.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/crm_regs.h>
  13 #include <asm/arch/iomux.h>
  14 #include <asm/arch/imx-regs.h>
  15 #include <asm/arch/mx6-pins.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/gpio.h>
  18 #include <asm/mach-imx/iomux-v3.h>
  19 #include <asm/io.h>
  20 #include <asm/mach-imx/mxc_i2c.h>
  21 #include <env.h>
  22 #include <linux/delay.h>
  23 #include <linux/sizes.h>
  24 #include <common.h>
  25 #include <fsl_esdhc_imx.h>
  26 #include <mmc.h>
  27 #include <i2c.h>
  28 #include <miiphy.h>
  29 #include <netdev.h>
  30 #include <power/pmic.h>
  31 #include <power/pfuze100_pmic.h>
  32 #include <usb.h>
  33 #include <usb/ehci-ci.h>
  34 #include <pwm.h>
  35 #include <wait_bit.h>
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 #define UART_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |     \
  40         PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |   \
  41         PAD_CTL_SRE_FAST)
  42
  43 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PKE |     \
  44         PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm |                \
  45         PAD_CTL_SRE_FAST)
  46
  47 #define ENET_CLK_PAD_CTRL  PAD_CTL_DSE_34ohm
  48
  49 #define ENET_RX_PAD_CTRL  (PAD_CTL_PKE |                        \
  50         PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH |            \
  51         PAD_CTL_SRE_FAST)
  52
  53 #define I2C_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |      \
  54         PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED |         \
  55         PAD_CTL_DSE_40ohm)
  56
  57 #define USDHC_CLK_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_SPEED_MED |  \
  58         PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST)
  59
  60 #define USDHC_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP |     \
  61         PAD_CTL_PKE |  PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm |  \
  62         PAD_CTL_SRE_FAST)
  63
  64 #define USDHC_RESET_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP |    \
  65         PAD_CTL_PKE |  PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm)
  66
  67 #define GPIO_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |     \
  68         PAD_CTL_PKE)
  69
  70 int dram_init(void)
  71 {
  72         gd->ram_size = imx_ddr_size();
  73
  74         return 0;
  75 }
  76
  77 static iomux_v3_cfg_t const pwm_led_pads[] = {
  78         MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
  79         MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
  80         MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
  81 };
  82
  83 static int board_net_init(void)
  84 {
  85         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  86         unsigned char eth1addr[6];
  87         int ret;
  88
  89         /* just to get second mac address */
  90         imx_get_mac_from_fuse(1, eth1addr);
  91         if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
  92                 eth_env_set_enetaddr("eth1addr", eth1addr);
  93
  94         /*
  95          * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
  96          * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
  97          * ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver.
  98          */
  99         clrsetbits_le32(&iomuxc_regs->gpr[1],
 100                         IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK |
 101                         IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
 102                         IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK |
 103                         IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
 104
 105         ret = enable_fec_anatop_clock(0, ENET_50MHZ);
 106         if (ret)
 107                 goto eth_fail;
 108
 109         ret = enable_fec_anatop_clock(1, ENET_50MHZ);
 110         if (ret)
 111                 goto eth_fail;
 112
 113         return ret;
 114
 115 eth_fail:
 116         printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
 117         return ret;
 118 }
 119
 120 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 121 /* I2C1 for PMIC */
 122 static struct i2c_pads_info i2c_pad_info1 = {
 123         .scl = {
 124                 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
 125                 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
 126                 .gp = IMX_GPIO_NR(1, 0),
 127         },
 128         .sda = {
 129                 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
 130                 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
 131                 .gp = IMX_GPIO_NR(1, 1),
 132         },
 133 };
 134
 135 static struct pmic *pfuze_init(unsigned char i2cbus)
 136 {
 137         struct pmic *p;
 138         int ret;
 139         u32 reg;
 140
 141         ret = power_pfuze100_init(i2cbus);
 142         if (ret)
 143                 return NULL;
 144
 145         p = pmic_get("PFUZE100");
 146         ret = pmic_probe(p);
 147         if (ret)
 148                 return NULL;
 149
 150         pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
 151         printf("PMIC:  PFUZE%i00 ID=0x%02x\n", (reg & 1) ? 2 : 1, reg);
 152
 153         /* Set SW1AB stanby volage to 0.975V */
 154         pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
 155         reg &= ~SW1x_STBY_MASK;
 156         reg |= SW1x_0_975V;
 157         pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
 158
 159         /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
 160         pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg);
 161         reg &= ~SW1xCONF_DVSSPEED_MASK;
 162         reg |= SW1xCONF_DVSSPEED_4US;
 163         pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
 164
 165         /* Set SW1C standby voltage to 0.975V */
 166         pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
 167         reg &= ~SW1x_STBY_MASK;
 168         reg |= SW1x_0_975V;
 169         pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
 170
 171         /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
 172         pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
 173         reg &= ~SW1xCONF_DVSSPEED_MASK;
 174         reg |= SW1xCONF_DVSSPEED_4US;
 175         pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
 176
 177         return p;
 178 }
 179
 180 static int pfuze_mode_init(struct pmic *p, u32 mode)
 181 {
 182         unsigned char offset, i, switch_num;
 183         u32 id;
 184         int ret;
 185
 186         pmic_reg_read(p, PFUZE100_DEVICEID, &id);
 187         id = id & 0xf;
 188
 189         if (id == 0) {
 190                 switch_num = 6;
 191                 offset = PFUZE100_SW1CMODE;
 192         } else if (id == 1) {
 193                 switch_num = 4;
 194                 offset = PFUZE100_SW2MODE;
 195         } else {
 196                 printf("Not supported, id=%d\n", id);
 197                 return -EINVAL;
 198         }
 199
 200         ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
 201         if (ret < 0) {
 202                 printf("Set SW1AB mode error!\n");
 203                 return ret;
 204         }
 205
 206         for (i = 0; i < switch_num - 1; i++) {
 207                 ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
 208                 if (ret < 0) {
 209                         printf("Set switch 0x%x mode error!\n",
 210                                offset + i * SWITCH_SIZE);
 211                         return ret;
 212                 }
 213         }
 214
 215         return ret;
 216 }
 217
 218 int power_init_board(void)
 219 {
 220         struct pmic *p;
 221         int ret;
 222
 223         p = pfuze_init(I2C_PMIC);
 224         if (!p)
 225                 return -ENODEV;
 226
 227         ret = pfuze_mode_init(p, APS_PFM);
 228         if (ret < 0)
 229                 return ret;
 230
 231         set_ldo_voltage(LDO_ARM, 1175); /* Set VDDARM to 1.175V */
 232         set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
 233
 234         return 0;
 235 }
 236
 237 #ifdef CONFIG_USB_EHCI_MX6
 238 static iomux_v3_cfg_t const usb_otg_pads[] = {
 239         /* OGT1 */
 240         MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 241         MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
 242         /* OTG2 */
 243         MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
 244 };
 245
 246 static void setup_iomux_usb(void)
 247 {
 248         imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
 249                                          ARRAY_SIZE(usb_otg_pads));
 250 }
 251
 252 int board_usb_phy_mode(int port)
 253 {
 254         if (port == 1)
 255                 return USB_INIT_HOST;
 256         else
 257                 return usb_phy_mode(port);
 258 }
 259 #endif
 260
 261 #ifdef CONFIG_PWM_IMX
 262 static int set_pwm_leds(void)
 263 {
 264         int ret;
 265
 266         imx_iomux_v3_setup_multiple_pads(pwm_led_pads,
 267                                          ARRAY_SIZE(pwm_led_pads));
 268         /* enable backlight PWM 2, green LED */
 269         ret = pwm_init(1, 0, 0);
 270         if (ret)
 271                 goto error;
 272         /* duty cycle 200ns, period: 8000ns */
 273         ret = pwm_config(1, 200, 8000);
 274         if (ret)
 275                 goto error;
 276         ret = pwm_enable(1);
 277         if (ret)
 278                 goto error;
 279
 280         /* enable backlight PWM 1, blue LED */
 281         ret = pwm_init(0, 0, 0);
 282         if (ret)
 283                 goto error;
 284         /* duty cycle 200ns, period: 8000ns */
 285         ret = pwm_config(0, 200, 8000);
 286         if (ret)
 287                 goto error;
 288         ret = pwm_enable(0);
 289         if (ret)
 290                 goto error;
 291
 292         /* enable backlight PWM 6, red LED */
 293         ret = pwm_init(5, 0, 0);
 294         if (ret)
 295                 goto error;
 296         /* duty cycle 200ns, period: 8000ns */
 297         ret = pwm_config(5, 200, 8000);
 298         if (ret)
 299                 goto error;
 300         ret = pwm_enable(5);
 301
 302 error:
 303         return ret;
 304 }
 305 #else
 306 static int set_pwm_leds(void)
 307 {
 308         return 0;
 309 }
 310 #endif
 311
 312 #define ADCx_HC0        0x00
 313 #define ADCx_HS         0x08
 314 #define ADCx_HS_C0      BIT(0)
 315 #define ADCx_R0         0x0c
 316 #define ADCx_CFG        0x14
 317 #define ADCx_CFG_SWMODE 0x308
 318 #define ADCx_GC         0x18
 319 #define ADCx_GC_CAL     BIT(7)
 320
 321 static int read_adc(u32 *val)
 322 {
 323         int ret;
 324         void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE);
 325
 326         /* use software mode */
 327         writel(ADCx_CFG_SWMODE, b + ADCx_CFG);
 328
 329         /* start auto calibration */
 330         setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
 331         ret = wait_for_bit_le32(b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
 332         if (ret)
 333                 goto adc_exit;
 334
 335         /* start conversion */
 336         writel(0, b + ADCx_HC0);
 337
 338         /* wait for conversion */
 339         ret = wait_for_bit_le32(b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
 340         if (ret)
 341                 goto adc_exit;
 342
 343         /* read result */
 344         *val = readl(b + ADCx_R0);
 345
 346 adc_exit:
 347         if (ret)
 348                 printf("ADC failure (ret=%i)\n", ret);
 349         unmap_physmem(b, MAP_NOCACHE);
 350         return ret;
 351 }
 352
 353 #define VAL_UPPER       2498
 354 #define VAL_LOWER       1550
 355
 356 static int set_pin_state(void)
 357 {
 358         u32 val;
 359         int ret;
 360
 361         ret = read_adc(&val);
 362         if (ret)
 363                 return ret;
 364
 365         if (val >= VAL_UPPER)
 366                 env_set("pin_state", "connected");
 367         else if (val < VAL_UPPER && val > VAL_LOWER)
 368                 env_set("pin_state", "open");
 369         else
 370                 env_set("pin_state", "button");
 371
 372         return ret;
 373 }
 374
 375 int board_late_init(void)
 376 {
 377         int ret;
 378
 379         ret = set_pwm_leds();
 380         if (ret)
 381                 return ret;
 382
 383         ret = set_pin_state();
 384
 385         return ret;
 386 }
 387
 388 int board_early_init_f(void)
 389 {
 390         setup_iomux_usb();
 391
 392         return 0;
 393 }
 394
 395 int board_init(void)
 396 {
 397         /* Address of boot parameters */
 398         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 399
 400 #ifdef CONFIG_SYS_I2C_MXC
 401         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 402 #endif
 403
 404         return board_net_init();
 405 }
 406
 407 int checkboard(void)
 408 {
 409         puts("Board: VIN|ING 2000\n");
 410
 411         return 0;
 412 }
 413
 414 #define PCIE_PHY_PUP_REQ                BIT(7)
 415
 416 void board_preboot_os(void)
 417 {
 418         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 419         struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
 420
 421         /* Bring the PCI power domain up, so that old vendorkernel works. */
 422         setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
 423         setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
 424         setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
 425 }
 426
 427 #ifdef CONFIG_SPL_BUILD
 428 #include <linux/libfdt.h>
 429 #include <spl.h>
 430 #include <asm/arch/mx6-ddr.h>
 431
 432 static iomux_v3_cfg_t const pcie_pads[] = {
 433         MX6_PAD_NAND_DATA02__GPIO4_IO_6 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
 434 };
 435
 436 static iomux_v3_cfg_t const uart_pads[] = {
 437         MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 438         MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 439 };
 440
 441 static iomux_v3_cfg_t const usdhc4_pads[] = {
 442         MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 443         MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 444         MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 445         MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 446         MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 447         MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 448         MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 449         MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 450         MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 451         MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 452 };
 453
 454 static void vining2000_spl_setup_iomux_pcie(void)
 455 {
 456         imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
 457 }
 458
 459 static void vining2000_spl_setup_iomux_uart(void)
 460 {
 461         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 462 }
 463
 464 static struct fsl_esdhc_cfg usdhc_cfg = { USDHC4_BASE_ADDR };
 465
 466 int board_mmc_init(bd_t *bis)
 467 {
 468         imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 469
 470         usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 471         gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
 472         return fsl_esdhc_initialize(bis, &usdhc_cfg);
 473 }
 474
 475 int board_mmc_getcd(struct mmc *mmc)
 476 {
 477         return 1;
 478 }
 479
 480 const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
 481         .dram_dqm0              = 0x00000028,
 482         .dram_dqm1              = 0x00000028,
 483         .dram_dqm2              = 0x00000028,
 484         .dram_dqm3              = 0x00000028,
 485         .dram_ras               = 0x00000028,
 486         .dram_cas               = 0x00000028,
 487         .dram_odt0              = 0x00000028,
 488         .dram_odt1              = 0x00000028,
 489         .dram_sdba2             = 0x00000000,
 490         .dram_sdcke0            = 0x00003000,
 491         .dram_sdcke1            = 0x00003000,
 492         .dram_sdclk_0           = 0x00000030,
 493         .dram_sdqs0             = 0x00000028,
 494         .dram_sdqs1             = 0x00000028,
 495         .dram_sdqs2             = 0x00000028,
 496         .dram_sdqs3             = 0x00000028,
 497         .dram_reset             = 0x00000028,
 498 };
 499
 500 const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
 501         .grp_addds              = 0x00000028,
 502         .grp_b0ds               = 0x00000028,
 503         .grp_b1ds               = 0x00000028,
 504         .grp_b2ds               = 0x00000028,
 505         .grp_b3ds               = 0x00000028,
 506         .grp_ctlds              = 0x00000028,
 507         .grp_ddr_type           = 0x000c0000,
 508         .grp_ddrmode            = 0x00020000,
 509         .grp_ddrmode_ctl        = 0x00020000,
 510         .grp_ddrpke             = 0x00000000,
 511 };
 512
 513 const struct mx6_mmdc_calibration mx6_mmcd_calib = {
 514         .p0_mpwldectrl0         = 0x0022001C,
 515         .p0_mpwldectrl1         = 0x001F001A,
 516         .p0_mpdgctrl0           = 0x01380134,
 517         .p0_mpdgctrl1           = 0x0124011C,
 518         .p0_mprddlctl           = 0x42404444,
 519         .p0_mpwrdlctl           = 0x36383C38,
 520 };
 521
 522 static struct mx6_ddr3_cfg mem_ddr = {
 523         .mem_speed      = 1600,
 524         .density        = 4,
 525         .width          = 32,
 526         .banks          = 8,
 527         .rowaddr        = 15,
 528         .coladdr        = 10,
 529         .pagesz         = 2,
 530         .trcd           = 1391,
 531         .trcmin         = 4875,
 532         .trasmin        = 3500,
 533 };
 534
 535 static void ccgr_init(void)
 536 {
 537         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 538
 539         writel(0xF000000F, &ccm->CCGR0);        /* AIPS_TZ{1,2,3} */
 540         writel(0x303C0000, &ccm->CCGR1);        /* GPT, OCRAM */
 541         writel(0x00FFFCC0, &ccm->CCGR2);        /* IPMUX, I2C1, I2C3 */
 542         writel(0x3F300030, &ccm->CCGR3);        /* OCRAM, MMDC, ENET */
 543         writel(0x0000C003, &ccm->CCGR4);        /* PCI, PL301 */
 544         writel(0x0F0330C3, &ccm->CCGR5);        /* UART, ROM */
 545         writel(0x00000F00, &ccm->CCGR6);        /* SDHI4, EIM */
 546 }
 547
 548 static void vining2000_spl_dram_init(void)
 549 {
 550         struct mx6_ddr_sysinfo sysinfo = {
 551                 .dsize          = mem_ddr.width / 32,
 552                 .cs_density     = 24,
 553                 .ncs            = 1,
 554                 .cs1_mirror     = 0,
 555                 .rtt_wr         = 1,    /* RTT_wr = RZQ/4 */
 556                 .rtt_nom        = 1,    /* RTT_Nom = RZQ/4 */
 557                 .walat          = 1,    /* Write additional latency */
 558                 .ralat          = 5,    /* Read additional latency */
 559                 .mif3_mode      = 3,    /* Command prediction working mode */
 560                 .bi_on          = 1,    /* Bank interleaving enabled */
 561                 .sde_to_rst     = 0x10, /* 14 cycles, 200us (JEDEC default) */
 562                 .rst_to_cke     = 0x23, /* 33 cycles, 500us (JEDEC default) */
 563                 .ddr_type       = DDR_TYPE_DDR3,
 564                 .refsel         = 1,    /* Refresh cycles at 32KHz */
 565                 .refr           = 7,    /* 8 refresh commands per refresh cycle */
 566         };
 567
 568         mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 569         mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
 570
 571         /* Perform DDR DRAM calibration */
 572         udelay(100);
 573         mmdc_do_write_level_calibration(&sysinfo);
 574         mmdc_do_dqs_calibration(&sysinfo);
 575 }
 576
 577 void board_init_f(ulong dummy)
 578 {
 579         /* setup AIPS and disable watchdog */
 580         arch_cpu_init();
 581
 582         ccgr_init();
 583
 584         /* iomux setup */
 585         vining2000_spl_setup_iomux_pcie();
 586         vining2000_spl_setup_iomux_uart();
 587
 588         /* setup GP timer */
 589         timer_init();
 590
 591         /* reset the PCIe device */
 592         gpio_set_value(IMX_GPIO_NR(4, 6), 1);
 593         udelay(50);
 594         gpio_set_value(IMX_GPIO_NR(4, 6), 0);
 595
 596         /* UART clocks enabled and gd valid - init serial console */
 597         preloader_console_init();
 598
 599         /* DDR initialization */
 600         vining2000_spl_dram_init();
 601
 602         /* Clear the BSS. */
 603         memset(__bss_start, 0, __bss_end - __bss_start);
 604
 605         /* load/boot image from boot device */
 606         board_init_r(NULL, 0);
 607 }
 608 #endif