1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Stefano Babic <sbabic@denx.de>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <linux/delay.h>
15 #include <linux/errno.h>
17 #include <asm/mach-imx/iomux-v3.h>
18 #include <asm/mach-imx/video.h>
20 #include <fsl_esdhc_imx.h>
21 #include <asm/arch/crm_regs.h>
23 #include <asm/arch/sys_proto.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
36 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
37 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
39 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
40 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
41 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
43 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
44 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
45 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
47 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
48 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
50 static iomux_v3_cfg_t const uart1_pads[] = {
51 IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
52 IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
55 static iomux_v3_cfg_t const gpios_pads[] = {
56 IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
59 static iomux_v3_cfg_t const usdhc2_pads[] = {
60 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
61 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
62 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
63 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
64 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
65 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
66 IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
69 static iomux_v3_cfg_t const enet_pads[] = {
70 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
71 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
72 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
73 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
74 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
75 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
76 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
77 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
78 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
79 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
80 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
81 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
82 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
83 MUX_PAD_CTRL(ENET_PAD_CTRL)),
84 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
85 MUX_PAD_CTRL(ENET_PAD_CTRL)),
86 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
87 MUX_PAD_CTRL(ENET_PAD_CTRL)),
88 IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
91 iomux_v3_cfg_t const enet_pads1[] = {
92 /* pin 35 - 1 (PHY_AD2) on reset */
93 IOMUX_PADS(PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
94 /* pin 32 - 1 - (MODE0) all */
95 IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
96 /* pin 31 - 1 - (MODE1) all */
97 IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
98 /* pin 28 - 1 - (MODE2) all */
99 IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
100 /* pin 27 - 1 - (MODE3) all */
101 IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
102 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
103 IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
104 /* pin 42 PHY nRST */
105 IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
108 static int mx6_rgmii_rework(struct phy_device *phydev)
111 /* min rx data delay */
112 ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
114 /* min tx data delay */
115 ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
117 /* max rx/tx clock delay, min rx/tx control */
118 ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
124 int board_phy_config(struct phy_device *phydev)
126 mx6_rgmii_rework(phydev);
128 if (phydev->drv->config)
129 return phydev->drv->config(phydev);
134 #define ENET_NRST IMX_GPIO_NR(1, 25)
136 void setup_iomux_enet(void)
138 SETUP_IOMUX_PADS(enet_pads);
142 int board_eth_init(bd_t *bis)
144 uint32_t base = IMX_FEC_BASE;
145 struct mii_dev *bus = NULL;
146 struct phy_device *phydev = NULL;
151 bus = fec_get_miibus(base, -1);
155 phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR),
156 PHY_INTERFACE_MODE_RGMII);
162 ret = fec_probe(bis, -1, base, bus, phydev);
175 int board_early_init_f(void)
177 SETUP_IOMUX_PADS(uart1_pads);
184 /* Address of boot parameters */
185 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
187 /* Take in reset the ATMega processor */
188 SETUP_IOMUX_PADS(gpios_pads);
189 gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
196 gd->ram_size = imx_ddr_size();
201 struct fsl_esdhc_cfg usdhc_cfg[1] = {
202 {USDHC2_BASE_ADDR, 0},
205 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 0)
206 int board_mmc_getcd(struct mmc *mmc)
208 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
211 if (cfg->esdhc_base == USDHC2_BASE_ADDR)
217 int board_mmc_init(bd_t *bis)
221 SETUP_IOMUX_PADS(usdhc2_pads);
222 gpio_direction_input(USDHC2_CD_GPIO);
223 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
224 usdhc_cfg[0].max_bus_width = 4;
226 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
228 printf("Warning: failed to initialize mmc dev \n");
235 #if defined(CONFIG_SPL_BUILD)
236 #include <asm/arch/mx6-ddr.h>
243 #define IMX6SDL_DRIVE_STRENGTH 0x230
246 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
247 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
248 .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
249 .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
250 .dram_cas = IMX6SDL_DRIVE_STRENGTH,
251 .dram_ras = IMX6SDL_DRIVE_STRENGTH,
252 .dram_reset = IMX6SDL_DRIVE_STRENGTH,
253 .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
254 .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
255 .dram_sdba2 = 0x00000000,
256 .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
257 .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
258 .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
259 .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
260 .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
261 .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
262 .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
263 .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
264 .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
265 .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
266 .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
267 .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
268 .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
269 .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
270 .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
271 .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
272 .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
273 .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
276 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
277 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
278 .grp_ddr_type = 0x000c0000,
279 .grp_ddrmode_ctl = 0x00020000,
280 .grp_ddrpke = 0x00000000,
281 .grp_addds = IMX6SDL_DRIVE_STRENGTH,
282 .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
283 .grp_ddrmode = 0x00020000,
284 .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
285 .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
286 .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
287 .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
288 .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
289 .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
290 .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
291 .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
294 /* MT41K128M16JT-125 */
295 static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
296 /* quad = 1066, duallite = 800 */
310 static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
311 .p0_mpwldectrl0 = 0x0043004E,
312 .p0_mpwldectrl1 = 0x003D003F,
313 .p1_mpwldectrl0 = 0x00230021,
314 .p1_mpwldectrl1 = 0x0028003E,
315 .p0_mpdgctrl0 = 0x42580250,
316 .p0_mpdgctrl1 = 0x0238023C,
317 .p1_mpdgctrl0 = 0x422C0238,
318 .p1_mpdgctrl1 = 0x02180228,
319 .p0_mprddlctl = 0x44464A46,
320 .p1_mprddlctl = 0x44464A42,
321 .p0_mpwrdlctl = 0x36343236,
322 .p1_mpwrdlctl = 0x36343230,
326 static struct mx6_ddr_sysinfo mem_qdl = {
329 /* config for full 4GB range so that get_mem_size() works */
340 .refsel = 1, /* Refresh cycles at 32KHz */
341 .refr = 7, /* 8 refresh commands per refresh cycle */
344 static void ccgr_init(void)
346 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
348 /* set the default clock gate to save power */
349 writel(0x00C03F3F, &ccm->CCGR0);
350 writel(0x0030FC03, &ccm->CCGR1);
351 writel(0x0FFFC000, &ccm->CCGR2);
352 writel(0x3FF00000, &ccm->CCGR3);
353 writel(0x00FFF300, &ccm->CCGR4);
354 writel(0xFFFFFFFF, &ccm->CCGR5);
355 writel(0x000003FF, &ccm->CCGR6);
358 static void spl_dram_init(void)
360 if (is_cpu_type(MXC_CPU_MX6DL)) {
361 mt41k128m16jt_125.mem_speed = 800;
365 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
366 mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125);
368 printf("Wrong CPU for this board\n");
374 #ifdef CONFIG_MX6_DDRCAL
376 /* Perform DDR DRAM calibration */
377 mmdc_do_write_level_calibration(&mem_qdl);
378 mmdc_do_dqs_calibration(&mem_qdl);
382 static void check_bootcfg(void)
386 fuse_sense(0, 5, &val5);
387 fuse_sense(0, 6, &val6);
388 /* Check if boot from MMC */
390 puts("BT_FUSE_SEL already fused, will do nothing\n");
393 fuse_prog(0, 5, 0x00000840);
395 fuse_prog(0, 6, 0x00000010);
397 do_reset(NULL, 0, 0, NULL);
400 void board_init_f(ulong dummy)
404 /* setup AIPS and disable watchdog */
410 board_early_init_f();
415 /* UART clocks enabled and gd valid - init serial console */
416 preloader_console_init();
418 /* DDR initialization */
421 /* Set fuses for new boards and reboot if not set */
425 memset(__bss_start, 0, __bss_end - __bss_start);
427 /* load/boot image from boot device */
428 board_init_r(NULL, 0);