board/sks-kinkel/sksimx6/sksimx6.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Stefano Babic <sbabic@denx.de>
   4  */
   5
   6 #include <common.h>
   7 #include <command.h>
   8 #include <init.h>
   9 #include <net.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <linux/errno.h>
  15 #include <asm/gpio.h>
  16 #include <asm/mach-imx/iomux-v3.h>
  17 #include <asm/mach-imx/video.h>
  18 #include <mmc.h>
  19 #include <fsl_esdhc_imx.h>
  20 #include <asm/arch/crm_regs.h>
  21 #include <asm/io.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <spl.h>
  24 #include <netdev.h>
  25 #include <miiphy.h>
  26 #include <micrel.h>
  27
  28 #include <common.h>
  29 #include <malloc.h>
  30 #include <fuse.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  35         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  36         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  37
  38 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  39         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
  40         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  41
  42 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  43         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  44         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  45
  46 #define ENET_PAD_CTRL           (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  47                                  PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  48
  49 static iomux_v3_cfg_t const uart1_pads[] = {
  50         IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  51         IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  52 };
  53
  54 static iomux_v3_cfg_t const gpios_pads[] = {
  55         IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  56 };
  57
  58 static iomux_v3_cfg_t const usdhc2_pads[] = {
  59         IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  60         IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  61         IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  62         IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  63         IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  64         IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  65         IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
  66 };
  67
  68 static iomux_v3_cfg_t const enet_pads[] = {
  69         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  70         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  71         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  72         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  73         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  74         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  75         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  76         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  77         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  78         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  79         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  80         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  81         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK  |
  82                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
  83         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  84                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
  85         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
  86                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
  87         IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  88 };
  89
  90 iomux_v3_cfg_t const enet_pads1[] = {
  91         /* pin 35 - 1 (PHY_AD2) on reset */
  92         IOMUX_PADS(PAD_RGMII_RXC__GPIO6_IO30    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  93         /* pin 32 - 1 - (MODE0) all */
  94         IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  95         /* pin 31 - 1 - (MODE1) all */
  96         IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  97         /* pin 28 - 1 - (MODE2) all */
  98         IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  99         /* pin 27 - 1 - (MODE3) all */
 100         IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 101         /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
 102         IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 103         /* pin 42 PHY nRST */
 104         IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 105 };
 106
 107 static int mx6_rgmii_rework(struct phy_device *phydev)
 108 {
 109
 110         /* min rx data delay */
 111         ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
 112                                    0x0);
 113         /* min tx data delay */
 114         ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
 115                                    0x0);
 116         /* max rx/tx clock delay, min rx/tx control */
 117         ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
 118                                    0xf0f0);
 119
 120         return 0;
 121 }
 122
 123 int board_phy_config(struct phy_device *phydev)
 124 {
 125         mx6_rgmii_rework(phydev);
 126
 127         if (phydev->drv->config)
 128                 return phydev->drv->config(phydev);
 129
 130         return 0;
 131 }
 132
 133 #define ENET_NRST IMX_GPIO_NR(1, 25)
 134
 135 void setup_iomux_enet(void)
 136 {
 137         SETUP_IOMUX_PADS(enet_pads);
 138
 139 }
 140
 141 int board_eth_init(bd_t *bis)
 142 {
 143         uint32_t base = IMX_FEC_BASE;
 144         struct mii_dev *bus = NULL;
 145         struct phy_device *phydev = NULL;
 146         int ret;
 147
 148         setup_iomux_enet();
 149
 150         bus = fec_get_miibus(base, -1);
 151         if (!bus)
 152                 return -EINVAL;
 153         /* scan phy */
 154         phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR),
 155                                         PHY_INTERFACE_MODE_RGMII);
 156
 157         if (!phydev) {
 158                 ret = -EINVAL;
 159                 goto free_bus;
 160         }
 161         ret  = fec_probe(bis, -1, base, bus, phydev);
 162         if (ret)
 163                 goto free_phydev;
 164
 165         return 0;
 166
 167 free_phydev:
 168         free(phydev);
 169 free_bus:
 170         free(bus);
 171         return ret;
 172 }
 173
 174 int board_early_init_f(void)
 175 {
 176         SETUP_IOMUX_PADS(uart1_pads);
 177
 178         return 0;
 179 }
 180
 181 int board_init(void)
 182 {
 183         /* Address of boot parameters */
 184         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 185
 186         /* Take in reset the ATMega processor */
 187         SETUP_IOMUX_PADS(gpios_pads);
 188         gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
 189
 190         return 0;
 191 }
 192
 193 int dram_init(void)
 194 {
 195         gd->ram_size = imx_ddr_size();
 196
 197         return 0;
 198 }
 199
 200 struct fsl_esdhc_cfg usdhc_cfg[1] = {
 201         {USDHC2_BASE_ADDR, 0},
 202 };
 203
 204 #define USDHC2_CD_GPIO  IMX_GPIO_NR(2, 0)
 205 int board_mmc_getcd(struct mmc *mmc)
 206 {
 207         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 208         int ret = 0;
 209
 210         if (cfg->esdhc_base == USDHC2_BASE_ADDR)
 211                 ret = 1;
 212
 213         return ret;
 214 }
 215
 216 int board_mmc_init(bd_t *bis)
 217 {
 218         int ret;
 219
 220         SETUP_IOMUX_PADS(usdhc2_pads);
 221         gpio_direction_input(USDHC2_CD_GPIO);
 222         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 223         usdhc_cfg[0].max_bus_width = 4;
 224
 225         ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 226         if (ret) {
 227                 printf("Warning: failed to initialize mmc dev \n");
 228                 return ret;
 229         }
 230
 231         return 0;
 232 }
 233
 234 #if defined(CONFIG_SPL_BUILD)
 235 #include <asm/arch/mx6-ddr.h>
 236
 237 /*
 238  * Driving strength:
 239  *   0x30 == 40 Ohm
 240  *   0x28 == 48 Ohm
 241  */
 242 #define IMX6SDL_DRIVE_STRENGTH  0x230
 243
 244
 245 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
 246 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
 247         .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
 248         .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
 249         .dram_cas = IMX6SDL_DRIVE_STRENGTH,
 250         .dram_ras = IMX6SDL_DRIVE_STRENGTH,
 251         .dram_reset = IMX6SDL_DRIVE_STRENGTH,
 252         .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
 253         .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
 254         .dram_sdba2 = 0x00000000,
 255         .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
 256         .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
 257         .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
 258         .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
 259         .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
 260         .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
 261         .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
 262         .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
 263         .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
 264         .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
 265         .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
 266         .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
 267         .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
 268         .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
 269         .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
 270         .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
 271         .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
 272         .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
 273 };
 274
 275 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
 276 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 277         .grp_ddr_type = 0x000c0000,
 278         .grp_ddrmode_ctl = 0x00020000,
 279         .grp_ddrpke = 0x00000000,
 280         .grp_addds = IMX6SDL_DRIVE_STRENGTH,
 281         .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
 282         .grp_ddrmode = 0x00020000,
 283         .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
 284         .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
 285         .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
 286         .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
 287         .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
 288         .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
 289         .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
 290         .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
 291 };
 292
 293 /* MT41K128M16JT-125 */
 294 static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
 295         /* quad = 1066, duallite = 800 */
 296         .mem_speed = 1066,
 297         .density = 2,
 298         .width = 16,
 299         .banks = 8,
 300         .rowaddr = 14,
 301         .coladdr = 10,
 302         .pagesz = 2,
 303         .trcd = 1375,
 304         .trcmin = 4875,
 305         .trasmin = 3500,
 306         .SRT = 0,
 307 };
 308
 309 static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
 310         .p0_mpwldectrl0 = 0x0043004E,
 311         .p0_mpwldectrl1 = 0x003D003F,
 312         .p1_mpwldectrl0 = 0x00230021,
 313         .p1_mpwldectrl1 = 0x0028003E,
 314         .p0_mpdgctrl0 = 0x42580250,
 315         .p0_mpdgctrl1 = 0x0238023C,
 316         .p1_mpdgctrl0 = 0x422C0238,
 317         .p1_mpdgctrl1 = 0x02180228,
 318         .p0_mprddlctl = 0x44464A46,
 319         .p1_mprddlctl = 0x44464A42,
 320         .p0_mpwrdlctl = 0x36343236,
 321         .p1_mpwrdlctl = 0x36343230,
 322 };
 323
 324 /* DDR 64bit 1GB */
 325 static struct mx6_ddr_sysinfo mem_qdl = {
 326         .dsize = 2,
 327         .cs1_mirror = 0,
 328         /* config for full 4GB range so that get_mem_size() works */
 329         .cs_density = 32,
 330         .ncs = 1,
 331         .bi_on = 1,
 332         .rtt_nom = 1,
 333         .rtt_wr = 1,
 334         .ralat = 5,
 335         .walat = 0,
 336         .mif3_mode = 3,
 337         .rst_to_cke = 0x23,
 338         .sde_to_rst = 0x10,
 339         .refsel = 1,    /* Refresh cycles at 32KHz */
 340         .refr = 7,      /* 8 refresh commands per refresh cycle */
 341 };
 342
 343 static void ccgr_init(void)
 344 {
 345         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 346
 347         /* set the default clock gate to save power */
 348         writel(0x00C03F3F, &ccm->CCGR0);
 349         writel(0x0030FC03, &ccm->CCGR1);
 350         writel(0x0FFFC000, &ccm->CCGR2);
 351         writel(0x3FF00000, &ccm->CCGR3);
 352         writel(0x00FFF300, &ccm->CCGR4);
 353         writel(0xFFFFFFFF, &ccm->CCGR5);
 354         writel(0x000003FF, &ccm->CCGR6);
 355 }
 356
 357 static void spl_dram_init(void)
 358 {
 359         if (is_cpu_type(MXC_CPU_MX6DL)) {
 360                 mt41k128m16jt_125.mem_speed = 800;
 361                 mem_qdl.rtt_nom = 1;
 362                 mem_qdl.rtt_wr = 1;
 363
 364                 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 365                 mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125);
 366         } else {
 367                 printf("Wrong CPU for this board\n");
 368                 return;
 369         }
 370
 371         udelay(100);
 372
 373 #ifdef CONFIG_MX6_DDRCAL
 374
 375         /* Perform DDR DRAM calibration */
 376         mmdc_do_write_level_calibration(&mem_qdl);
 377         mmdc_do_dqs_calibration(&mem_qdl);
 378 #endif
 379 }
 380
 381 static void check_bootcfg(void)
 382 {
 383         u32 val5, val6;
 384
 385         fuse_sense(0, 5, &val5);
 386         fuse_sense(0, 6, &val6);
 387         /* Check if boot from MMC */
 388         if (val6 & 0x10) {
 389                 puts("BT_FUSE_SEL already fused, will do nothing\n");
 390                 return;
 391         }
 392         fuse_prog(0, 5, 0x00000840);
 393         /* BT_FUSE_SEL */
 394         fuse_prog(0, 6, 0x00000010);
 395
 396         do_reset(NULL, 0, 0, NULL);
 397 }
 398
 399 void board_init_f(ulong dummy)
 400 {
 401         ccgr_init();
 402
 403         /* setup AIPS and disable watchdog */
 404         arch_cpu_init();
 405
 406         gpr_init();
 407
 408         /* iomux */
 409         board_early_init_f();
 410
 411         /* setup GP timer */
 412         timer_init();
 413
 414         /* UART clocks enabled and gd valid - init serial console */
 415         preloader_console_init();
 416
 417         /* DDR initialization */
 418         spl_dram_init();
 419
 420         /* Set fuses for new boards and reboot if not set */
 421         check_bootcfg();
 422
 423         /* Clear the BSS. */
 424         memset(__bss_start, 0, __bss_end - __bss_start);
 425
 426         /* load/boot image from boot device */
 427         board_init_r(NULL, 0);
 428 }
 429 #endif