1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
7 * Achim Ehrlich <aehrlich@taskit.de>
8 * taskit GmbH <www.taskit.de>
11 * Markus Hubig <mhubig@imko.de>
12 * IMKO GmbH <www.imko.de>
14 * Heiko Schocher <hs@denx.de>
15 * DENX Software Engineering GmbH
23 #include <asm/arch/at91sam9_sdramc.h>
24 #include <asm/arch/at91sam9260_matrix.h>
25 #include <asm/arch/at91sam9_smc.h>
26 #include <asm/arch/at91_common.h>
27 #include <asm/arch/atmel_serial.h>
28 #include <asm/arch/at91_spi.h>
30 #include <asm/arch/clk.h>
31 #include <asm/arch/gpio.h>
40 DECLARE_GLOBAL_DATA_PTR;
42 static void smartweb_request_gpio(void)
44 gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
45 gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
46 gpio_request(AT91_PIN_PA26, "ena PHY");
49 static void smartweb_nand_hw_init(void)
51 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
52 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
55 /* Assign CS3 to NAND/SmartMedia Interface */
56 csa = readl(&matrix->ebicsa);
57 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
58 writel(csa, &matrix->ebicsa);
60 /* Configure SMC CS3 for NAND/SmartMedia */
61 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
62 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
64 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
65 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
67 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
69 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
70 AT91_SMC_MODE_TDF_CYCLE(2),
73 /* Configure RDY/BSY */
74 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
76 /* Enable NandFlash */
77 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
80 static void smartweb_macb_hw_init(void)
82 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
84 /* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */
85 at91_set_gpio_output(AT91_PIN_PA26, 0);
89 * RXDV (PA17) => PHY normal mode (not Test mode)
90 * ERX0 (PA14) => PHY ADDR0
91 * ERX1 (PA15) => PHY ADDR1
92 * ERX2 (PA25) => PHY ADDR2
93 * ERX3 (PA26) => PHY ADDR3
94 * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
96 * PHY has internal pull-down
98 writel(pin_to_mask(AT91_PIN_PA14) |
99 pin_to_mask(AT91_PIN_PA15) |
100 pin_to_mask(AT91_PIN_PA17) |
101 pin_to_mask(AT91_PIN_PA25) |
102 pin_to_mask(AT91_PIN_PA26) |
103 pin_to_mask(AT91_PIN_PA28) |
104 pin_to_mask(AT91_PIN_PA29),
109 /* Re-enable pull-up */
110 writel(pin_to_mask(AT91_PIN_PA14) |
111 pin_to_mask(AT91_PIN_PA15) |
112 pin_to_mask(AT91_PIN_PA17) |
113 pin_to_mask(AT91_PIN_PA25) |
114 pin_to_mask(AT91_PIN_PA26) |
115 pin_to_mask(AT91_PIN_PA28) |
116 pin_to_mask(AT91_PIN_PA29),
119 /* Initialize EMAC=MACB hardware */
123 #ifdef CONFIG_USB_GADGET_AT91
124 #include <linux/usb/at91_udc.h>
126 void at91_udp_hw_init(void)
129 at91_pllb_clk_enable(get_pllb_init());
131 /* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
132 at91_periph_clk_enable(ATMEL_ID_UDP);
134 at91_system_clk_enable(AT91SAM926x_PMC_UDP);
137 struct at91_udc_data board_udc_data = {
138 .baseaddr = ATMEL_BASE_UDP0,
142 int board_early_init_f(void)
144 /* enable this here, as we have SPL without serial support */
145 at91_seriald_hw_init();
146 smartweb_request_gpio();
152 smartweb_request_gpio();
154 at91_set_gpio_output(AT91_PIN_PC6, 0);
155 at91_set_gpio_output(AT91_PIN_PC7, 1);
157 at91_set_gpio_output(AT91_PIN_PC8, 0);
158 at91_set_gpio_output(AT91_PIN_PC9, 0);
160 at91_set_gpio_output(AT91_PIN_PC10, 0);
161 at91_set_gpio_output(AT91_PIN_PC11, 1);
163 #ifdef CONFIG_USB_GADGET_AT91
165 at91_udc_probe(&board_udc_data);
168 /* Adress of boot parameters */
169 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
171 smartweb_nand_hw_init();
172 smartweb_macb_hw_init();
178 gd->ram_size = get_ram_size(
179 (void *)CONFIG_SYS_SDRAM_BASE,
180 CONFIG_SYS_SDRAM_SIZE);
184 #ifndef CONFIG_DM_ETH
186 int board_eth_init(bd_t *bis)
188 return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
190 #endif /* CONFIG_MACB */
193 #if defined(CONFIG_SPL_BUILD)
196 #include <spi_flash.h>
198 void matrix_init(void)
200 struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
202 writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE))
203 | AT91_MATRIX_SLOT_CYCLE_(0x40),
207 void at91_spl_board_init(void)
209 smartweb_request_gpio();
210 /* power LED orange */
211 at91_set_gpio_output(AT91_PIN_PC6, 1);
212 at91_set_gpio_output(AT91_PIN_PC7, 1);
213 /* alarm LED orange */
214 at91_set_gpio_output(AT91_PIN_PC8, 1);
215 at91_set_gpio_output(AT91_PIN_PC9, 1);
217 at91_set_gpio_output(AT91_PIN_PC10, 0);
218 at91_set_gpio_output(AT91_PIN_PC11, 1);
220 smartweb_nand_hw_init();
221 at91_set_gpio_input(AT91_PIN_PA28, 1);
222 at91_set_gpio_input(AT91_PIN_PA29, 1);
224 /* check if both button are pressed */
225 if (at91_get_gpio_value(AT91_PIN_PA28) == 0 &&
226 at91_get_gpio_value(AT91_PIN_PA29) == 0) {
227 smartweb_nand_hw_init();
229 spl_nand_erase_one(0, 0);
233 #define SDRAM_BASE_CONF (AT91_SDRAMC_NC_9 | AT91_SDRAMC_NR_13 \
234 | AT91_SDRAMC_CAS_2 \
235 | AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32 \
236 | AT91_SDRAMC_TWR_VAL(2) | AT91_SDRAMC_TRC_VAL(7) \
237 | AT91_SDRAMC_TRP_VAL(2) | AT91_SDRAMC_TRCD_VAL(2) \
238 | AT91_SDRAMC_TRAS_VAL(5) | AT91_SDRAMC_TXSR_VAL(8))
242 struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX;
243 struct at91_port *port = (struct at91_port *)ATMEL_BASE_PIOC;
244 struct sdramc_reg setting;
246 setting.cr = SDRAM_BASE_CONF;
247 setting.mdr = AT91_SDRAMC_MD_SDRAM;
248 setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000;
251 * I write here directly in this register, because this
252 * approach is smaller than calling at91_set_a_periph() in a
253 * for loop. This saved me 96 bytes.
255 writel(0xffff0000, &port->pdr);
257 writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC, &ma->ebicsa);
258 sdramc_initialize(ATMEL_BASE_CS1, &setting);
262 int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
264 g_dnl_set_serialnumber("1");