board/siemens/rut/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Board functions for TI AM335X based rut board
   4  * (C) Copyright 2013 Siemens Schweiz AG
   5  * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
   6  *
   7  * Based on:
   8  * u-boot:/board/ti/am335x/board.c
   9  *
  10  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  11  */
  12
  13 #include <common.h>
  14 #include <env.h>
  15 #include <errno.h>
  16 #include <init.h>
  17 #include <spi.h>
  18 #include <spl.h>
  19 #include <asm/arch/cpu.h>
  20 #include <asm/arch/hardware.h>
  21 #include <asm/arch/omap.h>
  22 #include <asm/arch/ddr_defs.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/gpio.h>
  25 #include <asm/arch/mmc_host_def.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <asm/io.h>
  28 #include <asm/emif.h>
  29 #include <asm/gpio.h>
  30 #include <i2c.h>
  31 #include <miiphy.h>
  32 #include <cpsw.h>
  33 #include <video.h>
  34 #include <watchdog.h>
  35 #include "board.h"
  36 #include "../common/factoryset.h"
  37 #include "../../../drivers/video/da8xx-fb.h"
  38
  39 /*
  40  * Read header information from EEPROM into global structure.
  41  */
  42 static int read_eeprom(void)
  43 {
  44         return 0;
  45 }
  46
  47 #ifdef CONFIG_SPL_BUILD
  48 static void board_init_ddr(void)
  49 {
  50 struct emif_regs rut_ddr3_emif_reg_data = {
  51         .sdram_config = 0x61C04AB2,
  52         .sdram_tim1 = 0x0888A39B,
  53         .sdram_tim2 = 0x26337FDA,
  54         .sdram_tim3 = 0x501F830F,
  55         .emif_ddr_phy_ctlr_1 = 0x6,
  56         .zq_config = 0x50074BE4,
  57         .ref_ctrl = 0x93B,
  58 };
  59
  60 struct ddr_data rut_ddr3_data = {
  61         .datardsratio0 = 0x3b,
  62         .datawdsratio0 = 0x85,
  63         .datafwsratio0 = 0x100,
  64         .datawrsratio0 = 0xc1,
  65 };
  66
  67 struct cmd_control rut_ddr3_cmd_ctrl_data = {
  68         .cmd0csratio = 0x40,
  69         .cmd0iclkout = 1,
  70         .cmd1csratio = 0x40,
  71         .cmd1iclkout = 1,
  72         .cmd2csratio = 0x40,
  73         .cmd2iclkout = 1,
  74 };
  75
  76 const struct ctrl_ioregs ioregs = {
  77         .cm0ioctl               = RUT_IOCTRL_VAL,
  78         .cm1ioctl               = RUT_IOCTRL_VAL,
  79         .cm2ioctl               = RUT_IOCTRL_VAL,
  80         .dt0ioctl               = RUT_IOCTRL_VAL,
  81         .dt1ioctl               = RUT_IOCTRL_VAL,
  82 };
  83
  84         config_ddr(DDR_PLL_FREQ, &ioregs, &rut_ddr3_data,
  85                    &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0);
  86 }
  87
  88 static int request_and_pulse_reset(int gpio, const char *name)
  89 {
  90         int ret;
  91         const int delay_us = 2000; /* 2ms */
  92
  93         ret = gpio_request(gpio, name);
  94         if (ret < 0) {
  95                 printf("%s: Unable to request %s\n", __func__, name);
  96                 goto err;
  97         }
  98
  99         ret = gpio_direction_output(gpio, 0);
 100         if (ret < 0) {
 101                 printf("%s: Unable to set %s  as output\n", __func__, name);
 102                 goto err_free_gpio;
 103         }
 104
 105         udelay(delay_us);
 106
 107         gpio_set_value(gpio, 1);
 108
 109         return 0;
 110
 111 err_free_gpio:
 112         gpio_free(gpio);
 113 err:
 114         return ret;
 115 }
 116
 117 #define GPIO_TO_PIN(bank, gpio)         (32 * (bank) + (gpio))
 118 #define ETH_PHY_RESET_GPIO              GPIO_TO_PIN(2, 18)
 119 #define MAXTOUCH_RESET_GPIO             GPIO_TO_PIN(3, 18)
 120 #define DISPLAY_RESET_GPIO              GPIO_TO_PIN(3, 19)
 121
 122 #define REQUEST_AND_PULSE_RESET(N) \
 123                 request_and_pulse_reset(N, #N);
 124
 125 static void spl_siemens_board_init(void)
 126 {
 127         REQUEST_AND_PULSE_RESET(ETH_PHY_RESET_GPIO);
 128         REQUEST_AND_PULSE_RESET(MAXTOUCH_RESET_GPIO);
 129         REQUEST_AND_PULSE_RESET(DISPLAY_RESET_GPIO);
 130 }
 131 #endif /* if def CONFIG_SPL_BUILD */
 132
 133 #if defined(CONFIG_DRIVER_TI_CPSW)
 134 static void cpsw_control(int enabled)
 135 {
 136         /* VTP can be added here */
 137
 138         return;
 139 }
 140
 141 static struct cpsw_slave_data cpsw_slaves[] = {
 142         {
 143                 .slave_reg_ofs  = 0x208,
 144                 .sliver_reg_ofs = 0xd80,
 145                 .phy_addr       = 1,
 146                 .phy_if         = PHY_INTERFACE_MODE_RMII,
 147         },
 148         {
 149                 .slave_reg_ofs  = 0x308,
 150                 .sliver_reg_ofs = 0xdc0,
 151                 .phy_addr       = 0,
 152                 .phy_if         = PHY_INTERFACE_MODE_RMII,
 153         },
 154 };
 155
 156 static struct cpsw_platform_data cpsw_data = {
 157         .mdio_base              = CPSW_MDIO_BASE,
 158         .cpsw_base              = CPSW_BASE,
 159         .mdio_div               = 0xff,
 160         .channels               = 8,
 161         .cpdma_reg_ofs          = 0x800,
 162         .slaves                 = 1,
 163         .slave_data             = cpsw_slaves,
 164         .ale_reg_ofs            = 0xd00,
 165         .ale_entries            = 1024,
 166         .host_port_reg_ofs      = 0x108,
 167         .hw_stats_reg_ofs       = 0x900,
 168         .bd_ram_ofs             = 0x2000,
 169         .mac_control            = (1 << 5),
 170         .control                = cpsw_control,
 171         .host_port_num          = 0,
 172         .version                = CPSW_CTRL_VERSION_2,
 173 };
 174
 175 #if defined(CONFIG_DRIVER_TI_CPSW) || \
 176         (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
 177 int board_eth_init(bd_t *bis)
 178 {
 179         struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 180         int n = 0;
 181         int rv;
 182
 183 #ifndef CONFIG_SPL_BUILD
 184         factoryset_env_set();
 185 #endif
 186
 187         /* Set rgmii mode and enable rmii clock to be sourced from chip */
 188         writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
 189
 190         rv = cpsw_register(&cpsw_data);
 191         if (rv < 0)
 192                 printf("Error %d registering CPSW switch\n", rv);
 193         else
 194                 n += rv;
 195         return n;
 196 }
 197 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
 198 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
 199
 200 #if defined(CONFIG_HW_WATCHDOG)
 201 static bool hw_watchdog_init_done;
 202 static int  hw_watchdog_trigger_level;
 203
 204 void hw_watchdog_reset(void)
 205 {
 206         if (!hw_watchdog_init_done)
 207                 return;
 208
 209         hw_watchdog_trigger_level = hw_watchdog_trigger_level ? 0 : 1;
 210         gpio_set_value(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
 211 }
 212
 213 void hw_watchdog_init(void)
 214 {
 215         gpio_request(WATCHDOG_TRIGGER_GPIO, "watchdog_trigger");
 216         gpio_direction_output(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
 217
 218         hw_watchdog_reset();
 219
 220         hw_watchdog_init_done = 1;
 221 }
 222 #endif /* defined(CONFIG_HW_WATCHDOG) */
 223
 224 #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
 225 static struct da8xx_panel lcd_panels[] = {
 226         /* FORMIKE, 4.3", 480x800, KWH043MC17-F01 */
 227         [0] = {
 228                 .name   = "KWH043MC17-F01",
 229                 .width  = 480,
 230                 .height = 800,
 231                 .hfp = 50,              /* no spec, "don't care" values */
 232                 .hbp = 50,
 233                 .hsw = 50,
 234                 .vfp = 50,
 235                 .vbp = 50,
 236                 .vsw = 50,
 237                 .pxl_clk = 35910000,    /* tCYCD=20ns, max 50MHz, 60fps */
 238                 .invert_pxl_clk = 1,
 239         },
 240         /* FORMIKE, 4.3", 480x800, KWH043ST20-F01 */
 241         [1] = {
 242                 .name   = "KWH043ST20-F01",
 243                 .width  = 480,
 244                 .height = 800,
 245                 .hfp = 50,              /* no spec, "don't care" values */
 246                 .hbp = 50,
 247                 .hsw = 50,
 248                 .vfp = 50,
 249                 .vbp = 50,
 250                 .vsw = 50,
 251                 .pxl_clk = 35910000,    /* tCYCD=20ns, max 50MHz, 60fps */
 252                 .invert_pxl_clk = 1,
 253         },
 254         /* Multi-Inno, 4.3", 480x800, MI0430VT-1 */
 255         [2] = {
 256                 .name   = "MI0430VT-1",
 257                 .width  = 480,
 258                 .height = 800,
 259                 .hfp = 50,              /* no spec, "don't care" values */
 260                 .hbp = 50,
 261                 .hsw = 50,
 262                 .vfp = 50,
 263                 .vbp = 50,
 264                 .vsw = 50,
 265                 .pxl_clk = 35910000,    /* tCYCD=20ns, max 50MHz, 60fps */
 266                 .invert_pxl_clk = 1,
 267         },
 268 };
 269
 270 static const struct display_panel disp_panels[] = {
 271         [0] = {
 272                 WVGA,
 273                 16,     /* RGB 888 */
 274                 16,
 275                 COLOR_ACTIVE,
 276         },
 277         [1] = {
 278                 WVGA,
 279                 16,     /* RGB 888 */
 280                 16,
 281                 COLOR_ACTIVE,
 282         },
 283         [2] = {
 284                 WVGA,
 285                 24,     /* RGB 888 */
 286                 16,
 287                 COLOR_ACTIVE,
 288         },
 289 };
 290
 291 static const struct lcd_ctrl_config lcd_cfgs[] = {
 292         [0] = {
 293                 &disp_panels[0],
 294                 .ac_bias                = 255,
 295                 .ac_bias_intrpt         = 0,
 296                 .dma_burst_sz           = 16,
 297                 .bpp                    = 16,
 298                 .fdd                    = 0x80,
 299                 .tft_alt_mode           = 0,
 300                 .stn_565_mode           = 0,
 301                 .mono_8bit_mode         = 0,
 302                 .invert_line_clock      = 1,
 303                 .invert_frm_clock       = 1,
 304                 .sync_edge              = 0,
 305                 .sync_ctrl              = 1,
 306                 .raster_order           = 0,
 307         },
 308         [1] = {
 309                 &disp_panels[1],
 310                 .ac_bias                = 255,
 311                 .ac_bias_intrpt         = 0,
 312                 .dma_burst_sz           = 16,
 313                 .bpp                    = 16,
 314                 .fdd                    = 0x80,
 315                 .tft_alt_mode           = 0,
 316                 .stn_565_mode           = 0,
 317                 .mono_8bit_mode         = 0,
 318                 .invert_line_clock      = 1,
 319                 .invert_frm_clock       = 1,
 320                 .sync_edge              = 0,
 321                 .sync_ctrl              = 1,
 322                 .raster_order           = 0,
 323         },
 324         [2] = {
 325                 &disp_panels[2],
 326                 .ac_bias                = 255,
 327                 .ac_bias_intrpt         = 0,
 328                 .dma_burst_sz           = 16,
 329                 .bpp                    = 24,
 330                 .fdd                    = 0x80,
 331                 .tft_alt_mode           = 0,
 332                 .stn_565_mode           = 0,
 333                 .mono_8bit_mode         = 0,
 334                 .invert_line_clock      = 1,
 335                 .invert_frm_clock       = 1,
 336                 .sync_edge              = 0,
 337                 .sync_ctrl              = 1,
 338                 .raster_order           = 0,
 339         },
 340
 341 };
 342
 343 /* no console on this board */
 344 int board_cfb_skip(void)
 345 {
 346         return 1;
 347 }
 348
 349 #define PLL_GET_M(v) ((v >> 8) & 0x7ff)
 350 #define PLL_GET_N(v) (v & 0x7f)
 351
 352 static struct dpll_regs dpll_lcd_regs = {
 353         .cm_clkmode_dpll = CM_WKUP + 0x98,
 354         .cm_idlest_dpll = CM_WKUP + 0x48,
 355         .cm_clksel_dpll = CM_WKUP + 0x54,
 356 };
 357
 358 static int get_clk(struct dpll_regs *dpll_regs)
 359 {
 360         unsigned int val;
 361         unsigned int m, n;
 362         int f = 0;
 363
 364         val = readl(dpll_regs->cm_clksel_dpll);
 365         m = PLL_GET_M(val);
 366         n = PLL_GET_N(val);
 367         f = (m * V_OSCK) / n;
 368
 369         return f;
 370 };
 371
 372 int clk_get(int clk)
 373 {
 374         return get_clk(&dpll_lcd_regs);
 375 };
 376
 377 static int conf_disp_pll(int m, int n)
 378 {
 379         struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
 380         struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
 381 #if defined(DISPL_PLL_SPREAD_SPECTRUM)
 382         struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
 383 #endif
 384
 385         u32 *const clk_domains[] = {
 386                 &cmper->lcdclkctrl,
 387                 0
 388         };
 389         u32 *const clk_modules_explicit_en[] = {
 390                 &cmper->lcdclkctrl,
 391                 &cmper->lcdcclkstctrl,
 392                 &cmper->spi1clkctrl,
 393                 0
 394         };
 395         do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
 396
 397         do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
 398
 399 #if defined(DISPL_PLL_SPREAD_SPECTRUM)
 400         writel(0x64, &cmwkup->resv6[3]); /* 0x50 */
 401         writel(0x800, &cmwkup->resv6[2]); /* 0x4c */
 402         writel(readl(&cmwkup->clkmoddplldisp) | CM_CLKMODE_DPLL_SSC_EN_MASK,
 403                &cmwkup->clkmoddplldisp); /* 0x98 */
 404 #endif
 405         return 0;
 406 }
 407
 408 static int set_gpio(int gpio, int state)
 409 {
 410         gpio_request(gpio, "temp");
 411         gpio_direction_output(gpio, state);
 412         gpio_set_value(gpio, state);
 413         gpio_free(gpio);
 414         return 0;
 415 }
 416
 417 static int enable_lcd(void)
 418 {
 419         unsigned char buf[1];
 420
 421         set_gpio(BOARD_LCD_RESET, 0);
 422         mdelay(1);
 423         set_gpio(BOARD_LCD_RESET, 1);
 424         mdelay(1);
 425
 426         /* spi lcd init */
 427         kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_0);
 428
 429         /* backlight on */
 430         buf[0] = 0xf;
 431         i2c_write(0x24, 0x7, 1, buf, 1);
 432         buf[0] = 0x3f;
 433         i2c_write(0x24, 0x8, 1, buf, 1);
 434         return 0;
 435 }
 436
 437 int arch_early_init_r(void)
 438 {
 439         enable_lcd();
 440         return 0;
 441 }
 442
 443 static int board_video_init(void)
 444 {
 445         int i;
 446         int anzdisp = ARRAY_SIZE(lcd_panels);
 447         int display = 1;
 448
 449         for (i = 0; i < anzdisp; i++) {
 450                 if (strncmp((const char *)factory_dat.disp_name,
 451                             lcd_panels[i].name,
 452                     strlen((const char *)factory_dat.disp_name)) == 0) {
 453                         printf("DISPLAY: %s\n", factory_dat.disp_name);
 454                         break;
 455                 }
 456         }
 457         if (i == anzdisp) {
 458                 i = 1;
 459                 printf("%s: %s not found, using default %s\n", __func__,
 460                        factory_dat.disp_name, lcd_panels[i].name);
 461         }
 462         conf_disp_pll(24, 1);
 463         da8xx_video_init(&lcd_panels[display], &lcd_cfgs[display],
 464                          lcd_cfgs[display].bpp);
 465
 466         return 0;
 467 }
 468 #endif /* ifdef CONFIG_VIDEO */
 469
 470 #ifdef CONFIG_BOARD_LATE_INIT
 471 int board_late_init(void)
 472 {
 473         int ret;
 474         char tmp[2 * MAX_STRING_LENGTH + 2];
 475
 476         omap_nand_switch_ecc(1, 8);
 477
 478         if (factory_dat.asn[0] != 0)
 479                 sprintf(tmp, "%s_%s", factory_dat.asn,
 480                         factory_dat.comp_version);
 481         else
 482                 strcpy(tmp, "QMX7.E38_4.0");
 483
 484         ret = env_set("boardid", tmp);
 485         if (ret)
 486                 printf("error setting board id\n");
 487
 488         return 0;
 489 }
 490 #endif
 491
 492 #include "../common/board.c"