board/siemens/pxm2/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Board functions for TI AM335X based pxm2 board
   4  * (C) Copyright 2013 Siemens Schweiz AG
   5  * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
   6  *
   7  * Based on:
   8  * u-boot:/board/ti/am335x/board.c
   9  *
  10  * Board functions for TI AM335X based boards
  11  *
  12  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  13  */
  14
  15 #include <common.h>
  16 #include <env.h>
  17 #include <environment.h>
  18 #include <errno.h>
  19 #include <spl.h>
  20 #include <asm/arch/cpu.h>
  21 #include <asm/arch/hardware.h>
  22 #include <asm/arch/omap.h>
  23 #include <asm/arch/ddr_defs.h>
  24 #include <asm/arch/clock.h>
  25 #include <asm/arch/gpio.h>
  26 #include <asm/arch/mmc_host_def.h>
  27 #include <asm/arch/sys_proto.h>
  28 #include "../../../drivers/video/da8xx-fb.h"
  29 #include <asm/io.h>
  30 #include <asm/emif.h>
  31 #include <asm/gpio.h>
  32 #include <i2c.h>
  33 #include <miiphy.h>
  34 #include <cpsw.h>
  35 #include <watchdog.h>
  36 #include "board.h"
  37 #include "../common/factoryset.h"
  38 #include "pmic.h"
  39 #include <nand.h>
  40 #include <bmp_layout.h>
  41
  42 #ifdef CONFIG_SPL_BUILD
  43 static void board_init_ddr(void)
  44 {
  45 struct emif_regs pxm2_ddr3_emif_reg_data = {
  46         .sdram_config = 0x41805332,
  47         .sdram_tim1 = 0x666b3c9,
  48         .sdram_tim2 = 0x243631ca,
  49         .sdram_tim3 = 0x33f,
  50         .emif_ddr_phy_ctlr_1 = 0x100005,
  51         .zq_config = 0,
  52         .ref_ctrl = 0x81a,
  53 };
  54
  55 struct ddr_data pxm2_ddr3_data = {
  56         .datardsratio0 = 0x81204812,
  57         .datawdsratio0 = 0,
  58         .datafwsratio0 = 0x8020080,
  59         .datawrsratio0 = 0x4010040,
  60 };
  61
  62 struct cmd_control pxm2_ddr3_cmd_ctrl_data = {
  63         .cmd0csratio = 0x80,
  64         .cmd0iclkout = 0,
  65         .cmd1csratio = 0x80,
  66         .cmd1iclkout = 0,
  67         .cmd2csratio = 0x80,
  68         .cmd2iclkout = 0,
  69 };
  70
  71 const struct ctrl_ioregs ioregs = {
  72         .cm0ioctl               = DDR_IOCTRL_VAL,
  73         .cm1ioctl               = DDR_IOCTRL_VAL,
  74         .cm2ioctl               = DDR_IOCTRL_VAL,
  75         .dt0ioctl               = DDR_IOCTRL_VAL,
  76         .dt1ioctl               = DDR_IOCTRL_VAL,
  77 };
  78
  79         config_ddr(DDR_PLL_FREQ, &ioregs, &pxm2_ddr3_data,
  80                    &pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0);
  81 }
  82
  83 /*
  84  * voltage switching for MPU frequency switching.
  85  * @module = mpu - 0, core - 1
  86  * @vddx_op_vol_sel = vdd voltage to set
  87  */
  88
  89 #define MPU     0
  90 #define CORE    1
  91
  92 int voltage_update(unsigned int module, unsigned char vddx_op_vol_sel)
  93 {
  94         uchar buf[4];
  95         unsigned int reg_offset;
  96
  97         if (module == MPU)
  98                 reg_offset = PMIC_VDD1_OP_REG;
  99         else
 100                 reg_offset = PMIC_VDD2_OP_REG;
 101
 102         /* Select VDDx OP   */
 103         if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
 104                 return 1;
 105
 106         buf[0] &= ~PMIC_OP_REG_CMD_MASK;
 107
 108         if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
 109                 return 1;
 110
 111         /* Configure VDDx OP  Voltage */
 112         if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
 113                 return 1;
 114
 115         buf[0] &= ~PMIC_OP_REG_SEL_MASK;
 116         buf[0] |= vddx_op_vol_sel;
 117
 118         if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
 119                 return 1;
 120
 121         if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
 122                 return 1;
 123
 124         if ((buf[0] & PMIC_OP_REG_SEL_MASK) != vddx_op_vol_sel)
 125                 return 1;
 126
 127         return 0;
 128 }
 129
 130 #define OSC     (V_OSCK/1000000)
 131
 132 const struct dpll_params dpll_mpu_pxm2 = {
 133                 720, OSC-1, 1, -1, -1, -1, -1};
 134
 135 void spl_siemens_board_init(void)
 136 {
 137         uchar buf[4];
 138         /*
 139          * pxm2 PMIC code.  All boards currently want an MPU voltage
 140          * of 1.2625V and CORE voltage of 1.1375V to operate at
 141          * 720MHz.
 142          */
 143         if (i2c_probe(PMIC_CTRL_I2C_ADDR))
 144                 return;
 145
 146         /* VDD1/2 voltage selection register access by control i/f */
 147         if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
 148                 return;
 149
 150         buf[0] |= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;
 151
 152         if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
 153                 return;
 154
 155         /* Frequency switching for OPP 120 */
 156         if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) ||
 157             voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) {
 158                 printf("voltage update failed\n");
 159         }
 160 }
 161 #endif /* if def CONFIG_SPL_BUILD */
 162
 163 int read_eeprom(void)
 164 {
 165         /* nothing ToDo here for this board */
 166
 167         return 0;
 168 }
 169
 170 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 171         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 172 static void cpsw_control(int enabled)
 173 {
 174         /* VTP can be added here */
 175
 176         return;
 177 }
 178
 179 static struct cpsw_slave_data cpsw_slaves[] = {
 180         {
 181                 .slave_reg_ofs  = 0x208,
 182                 .sliver_reg_ofs = 0xd80,
 183                 .phy_addr       = 0,
 184                 .phy_if         = PHY_INTERFACE_MODE_RMII,
 185         },
 186         {
 187                 .slave_reg_ofs  = 0x308,
 188                 .sliver_reg_ofs = 0xdc0,
 189                 .phy_addr       = 1,
 190                 .phy_if         = PHY_INTERFACE_MODE_RMII,
 191         },
 192 };
 193
 194 static struct cpsw_platform_data cpsw_data = {
 195         .mdio_base              = CPSW_MDIO_BASE,
 196         .cpsw_base              = CPSW_BASE,
 197         .mdio_div               = 0xff,
 198         .channels               = 4,
 199         .cpdma_reg_ofs          = 0x800,
 200         .slaves                 = 1,
 201         .slave_data             = cpsw_slaves,
 202         .ale_reg_ofs            = 0xd00,
 203         .ale_entries            = 1024,
 204         .host_port_reg_ofs      = 0x108,
 205         .hw_stats_reg_ofs       = 0x900,
 206         .bd_ram_ofs             = 0x2000,
 207         .mac_control            = (1 << 5),
 208         .control                = cpsw_control,
 209         .host_port_num          = 0,
 210         .version                = CPSW_CTRL_VERSION_2,
 211 };
 212 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
 213
 214 #if defined(CONFIG_DRIVER_TI_CPSW) || \
 215         (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
 216 int board_eth_init(bd_t *bis)
 217 {
 218         int n = 0;
 219 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 220         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 221         struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 222 #ifdef CONFIG_FACTORYSET
 223         int rv;
 224         if (!is_valid_ethaddr(factory_dat.mac))
 225                 printf("Error: no valid mac address\n");
 226         else
 227                 eth_env_set_enetaddr("ethaddr", factory_dat.mac);
 228 #endif /* #ifdef CONFIG_FACTORYSET */
 229
 230         /* Set rgmii mode and enable rmii clock to be sourced from chip */
 231         writel(RGMII_MODE_ENABLE  | RGMII_INT_DELAY, &cdev->miisel);
 232
 233         rv = cpsw_register(&cpsw_data);
 234         if (rv < 0)
 235                 printf("Error %d registering CPSW switch\n", rv);
 236         else
 237                 n += rv;
 238 #endif
 239         return n;
 240 }
 241 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
 242
 243 #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
 244 static struct da8xx_panel lcd_panels[] = {
 245         /* AUO G156XW01 V1 */
 246         [0] = {
 247                 .name = "AUO_G156XW01_V1",
 248                 .width = 1376,
 249                 .height = 768,
 250                 .hfp = 14,
 251                 .hbp = 64,
 252                 .hsw = 56,
 253                 .vfp = 1,
 254                 .vbp = 28,
 255                 .vsw = 3,
 256                 .pxl_clk = 60000000,
 257                 .invert_pxl_clk = 0,
 258         },
 259         /* AUO B101EVN06 V0 */
 260         [1] = {
 261                 .name = "AUO_B101EVN06_V0",
 262                 .width = 1280,
 263                 .height = 800,
 264                 .hfp = 52,
 265                 .hbp = 84,
 266                 .hsw = 36,
 267                 .vfp = 3,
 268                 .vbp = 14,
 269                 .vsw = 6,
 270                 .pxl_clk = 60000000,
 271                 .invert_pxl_clk = 0,
 272         },
 273         /*
 274          * Settings from factoryset
 275          * stored in EEPROM
 276          */
 277         [2] = {
 278                 .name = "factoryset",
 279                 .width = 0,
 280                 .height = 0,
 281                 .hfp = 0,
 282                 .hbp = 0,
 283                 .hsw = 0,
 284                 .vfp = 0,
 285                 .vbp = 0,
 286                 .vsw = 0,
 287                 .pxl_clk = 60000000,
 288                 .invert_pxl_clk = 0,
 289         },
 290 };
 291
 292 static const struct display_panel disp_panel = {
 293         WVGA,
 294         32,
 295         16,
 296         COLOR_ACTIVE,
 297 };
 298
 299 static const struct lcd_ctrl_config lcd_cfg = {
 300         &disp_panel,
 301         .ac_bias                = 255,
 302         .ac_bias_intrpt         = 0,
 303         .dma_burst_sz           = 16,
 304         .bpp                    = 32,
 305         .fdd                    = 0x80,
 306         .tft_alt_mode           = 0,
 307         .stn_565_mode           = 0,
 308         .mono_8bit_mode         = 0,
 309         .invert_line_clock      = 1,
 310         .invert_frm_clock       = 1,
 311         .sync_edge              = 0,
 312         .sync_ctrl              = 1,
 313         .raster_order           = 0,
 314 };
 315
 316 static int set_gpio(int gpio, int state)
 317 {
 318         gpio_request(gpio, "temp");
 319         gpio_direction_output(gpio, state);
 320         gpio_set_value(gpio, state);
 321         gpio_free(gpio);
 322         return 0;
 323 }
 324
 325 static int enable_backlight(void)
 326 {
 327         set_gpio(BOARD_LCD_POWER, 1);
 328         set_gpio(BOARD_BACK_LIGHT, 1);
 329         set_gpio(BOARD_TOUCH_POWER, 1);
 330         return 0;
 331 }
 332
 333 static int enable_pwm(void)
 334 {
 335         struct pwmss_regs *pwmss = (struct pwmss_regs *)PWMSS0_BASE;
 336         struct pwmss_ecap_regs *ecap;
 337         int ticks = PWM_TICKS;
 338         int duty = PWM_DUTY;
 339
 340         ecap = (struct pwmss_ecap_regs *)AM33XX_ECAP0_BASE;
 341         /* enable clock */
 342         setbits_le32(&pwmss->clkconfig, ECAP_CLK_EN);
 343         /* TimeStam Counter register */
 344         writel(0xdb9, &ecap->tsctr);
 345         /* config period */
 346         writel(ticks - 1, &ecap->cap3);
 347         writel(ticks - 1, &ecap->cap1);
 348         setbits_le16(&ecap->ecctl2,
 349                      (ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK | 0xd0));
 350         /* config duty */
 351         writel(duty, &ecap->cap2);
 352         writel(duty, &ecap->cap4);
 353         /* start */
 354         setbits_le16(&ecap->ecctl2, ECTRL2_CTRSTP_FREERUN);
 355         return 0;
 356 }
 357
 358 static struct dpll_regs dpll_lcd_regs = {
 359         .cm_clkmode_dpll = CM_WKUP + 0x98,
 360         .cm_idlest_dpll = CM_WKUP + 0x48,
 361         .cm_clksel_dpll = CM_WKUP + 0x54,
 362 };
 363
 364 /* no console on this board */
 365 int board_cfb_skip(void)
 366 {
 367         return 1;
 368 }
 369
 370 #define PLL_GET_M(v) ((v >> 8) & 0x7ff)
 371 #define PLL_GET_N(v) (v & 0x7f)
 372
 373 static int get_clk(struct dpll_regs *dpll_regs)
 374 {
 375         unsigned int val;
 376         unsigned int m, n;
 377         int f = 0;
 378
 379         val = readl(dpll_regs->cm_clksel_dpll);
 380         m = PLL_GET_M(val);
 381         n = PLL_GET_N(val);
 382         f = (m * V_OSCK) / n;
 383
 384         return f;
 385 };
 386
 387 int clk_get(int clk)
 388 {
 389         return get_clk(&dpll_lcd_regs);
 390 };
 391
 392 static int conf_disp_pll(int m, int n)
 393 {
 394         struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
 395         struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
 396         struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
 397
 398         u32 *const clk_domains[] = {
 399                 &cmper->lcdclkctrl,
 400                 0
 401         };
 402         u32 *const clk_modules_explicit_en[] = {
 403                 &cmper->lcdclkctrl,
 404                 &cmper->lcdcclkstctrl,
 405                 &cmper->epwmss0clkctrl,
 406                 0
 407         };
 408         do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
 409         writel(0x0, &cmdpll->clklcdcpixelclk);
 410
 411         do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
 412
 413         return 0;
 414 }
 415
 416 static int board_video_init(void)
 417 {
 418         conf_disp_pll(24, 1);
 419         if (factory_dat.pxm50)
 420                 da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp);
 421         else
 422                 da8xx_video_init(&lcd_panels[1], &lcd_cfg, lcd_cfg.bpp);
 423
 424         enable_pwm();
 425         enable_backlight();
 426
 427         return 0;
 428 }
 429 #endif
 430
 431 #ifdef CONFIG_BOARD_LATE_INIT
 432 int board_late_init(void)
 433 {
 434         int ret;
 435
 436         omap_nand_switch_ecc(1, 8);
 437
 438 #ifdef CONFIG_FACTORYSET
 439         if (factory_dat.asn[0] != 0) {
 440                 char tmp[2 * MAX_STRING_LENGTH + 2];
 441
 442                 if (strncmp((const char *)factory_dat.asn, "PXM50", 5) == 0)
 443                         factory_dat.pxm50 = 1;
 444                 else
 445                         factory_dat.pxm50 = 0;
 446                 sprintf(tmp, "%s_%s", factory_dat.asn,
 447                         factory_dat.comp_version);
 448                 ret = env_set("boardid", tmp);
 449                 if (ret)
 450                         printf("error setting board id\n");
 451         } else {
 452                 factory_dat.pxm50 = 1;
 453                 ret = env_set("boardid", "PXM50_1.0");
 454                 if (ret)
 455                         printf("error setting board id\n");
 456         }
 457         debug("PXM50: %d\n", factory_dat.pxm50);
 458 #endif
 459
 460         return 0;
 461 }
 462 #endif
 463
 464 #include "../common/board.c"