board/siemens/draco/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Board functions for TI AM335X based draco board
   4  * (C) Copyright 2013 Siemens Schweiz AG
   5  * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
   6  *
   7  * Based on:
   8  *
   9  * Board functions for TI AM335X based boards
  10  * u-boot:/board/ti/am335x/board.c
  11  *
  12  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  13  */
  14
  15 #include <common.h>
  16 #include <env.h>
  17 #include <errno.h>
  18 #include <init.h>
  19 #include <spl.h>
  20 #include <asm/arch/cpu.h>
  21 #include <asm/arch/hardware.h>
  22 #include <asm/arch/omap.h>
  23 #include <asm/arch/ddr_defs.h>
  24 #include <asm/arch/clock.h>
  25 #include <asm/arch/gpio.h>
  26 #include <asm/arch/mmc_host_def.h>
  27 #include <asm/arch/sys_proto.h>
  28 #include <asm/arch/mem.h>
  29 #include <asm/io.h>
  30 #include <asm/emif.h>
  31 #include <asm/gpio.h>
  32 #include <i2c.h>
  33 #include <miiphy.h>
  34 #include <cpsw.h>
  35 #include <watchdog.h>
  36 #include "board.h"
  37 #include "../common/factoryset.h"
  38 #include <nand.h>
  39
  40 #ifdef CONFIG_SPL_BUILD
  41 static struct draco_baseboard_id __attribute__((section(".data"))) settings;
  42
  43 #if DDR_PLL_FREQ == 303
  44 #if !defined(CONFIG_TARGET_ETAMIN)
  45 /* Default@303MHz-i0 */
  46 const struct ddr3_data ddr3_default = {
  47         0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
  48         0x0079, 0x0888A39B, 0x26517FDA, 0x501F84EF, 0x00100206, 0x61A44A32,
  49         0x0000093B, 0x0000014A,
  50         "default name @303MHz           \0",
  51         "default marking                \0",
  52 };
  53 #else
  54 /* etamin board */
  55 const struct ddr3_data ddr3_default = {
  56         0x33524444, 0x56312e36, 0x0080, 0x0000, 0x003A, 0x0010, 0x009F,
  57         0x0050, 0x0888A39B, 0x266D7FDA, 0x501F86AF, 0x00100206, 0x61A44BB2,
  58         0x0000093B, 0x0000018A,
  59         "test-etamin                    \0",
  60         "generic-8Gbit                  \0",
  61 };
  62 #endif
  63 #elif DDR_PLL_FREQ == 400
  64 /* Default@400MHz-i0 */
  65 const struct ddr3_data ddr3_default = {
  66         0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab,
  67         0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232,
  68         0x00000618, 0x0000014A,
  69         "default name @400MHz           \0",
  70         "default marking                \0",
  71 };
  72 #endif
  73
  74 static void set_default_ddr3_timings(void)
  75 {
  76         printf("Set default DDR3 settings\n");
  77         settings.ddr3 = ddr3_default;
  78 }
  79
  80 static void print_ddr3_timings(void)
  81 {
  82         printf("\nDDR3\n");
  83         printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ);
  84         printf("device:\t\t%s\n", settings.ddr3.manu_name);
  85         printf("marking:\t%s\n", settings.ddr3.manu_marking);
  86         printf("%-20s, %-8s, %-8s, %-4s\n", "timing parameters", "eeprom",
  87                "default", "diff");
  88         PRINTARGS(magic);
  89         PRINTARGS(version);
  90         PRINTARGS(ddr3_sratio);
  91         PRINTARGS(iclkout);
  92
  93         PRINTARGS(dt0rdsratio0);
  94         PRINTARGS(dt0wdsratio0);
  95         PRINTARGS(dt0fwsratio0);
  96         PRINTARGS(dt0wrsratio0);
  97
  98         PRINTARGS(sdram_tim1);
  99         PRINTARGS(sdram_tim2);
 100         PRINTARGS(sdram_tim3);
 101
 102         PRINTARGS(emif_ddr_phy_ctlr_1);
 103
 104         PRINTARGS(sdram_config);
 105         PRINTARGS(ref_ctrl);
 106         PRINTARGS(ioctr_val);
 107 }
 108
 109 static void print_chip_data(void)
 110 {
 111         struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 112         dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
 113         printf("\nCPU BOARD\n");
 114         printf("device: \t'%s'\n", settings.chip.sdevname);
 115         printf("hw version: \t'%s'\n", settings.chip.shwver);
 116         printf("max freq: \t%d MHz\n", dpll_mpu_opp100.m);
 117 }
 118 #endif /* CONFIG_SPL_BUILD */
 119
 120 #define AM335X_NAND_ECC_MASK 0x0f
 121 #define AM335X_NAND_ECC_TYPE_16 0x02
 122
 123 static int ecc_type;
 124
 125 struct am335x_nand_geometry {
 126         u32 magic;
 127         u8 nand_geo_addr;
 128         u8 nand_geo_page;
 129         u8 nand_bus;
 130 };
 131
 132 static int draco_read_nand_geometry(void)
 133 {
 134         struct am335x_nand_geometry geo;
 135
 136         /* Read NAND geometry */
 137         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x80, 2,
 138                      (uchar *)&geo, sizeof(struct am335x_nand_geometry))) {
 139                 printf("Could not read the NAND geomtery; something fundamentally wrong on the I2C bus.\n");
 140                 return -EIO;
 141         }
 142         if (geo.magic != 0xa657b310) {
 143                 printf("%s: bad magic: %x\n", __func__, geo.magic);
 144                 return -EFAULT;
 145         }
 146         if ((geo.nand_bus & AM335X_NAND_ECC_MASK) == AM335X_NAND_ECC_TYPE_16)
 147                 ecc_type = 16;
 148         else
 149                 ecc_type = 8;
 150
 151         return 0;
 152 }
 153
 154 /*
 155  * Read header information from EEPROM into global structure.
 156  */
 157 static int read_eeprom(void)
 158 {
 159         /* Check if baseboard eeprom is available */
 160         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
 161                 printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
 162                 return 1;
 163         }
 164
 165 #ifdef CONFIG_SPL_BUILD
 166         /* Read Siemens eeprom data (DDR3) */
 167         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
 168                      (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) {
 169                 printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
 170                 set_default_ddr3_timings();
 171         }
 172         /* Read Siemens eeprom data (CHIP) */
 173         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
 174                      (uchar *)&settings.chip, sizeof(settings.chip)))
 175                 printf("Could not read chip settings\n");
 176
 177         if (ddr3_default.magic == settings.ddr3.magic &&
 178             ddr3_default.version == settings.ddr3.version) {
 179                 printf("Using DDR3 settings from EEPROM\n");
 180         } else {
 181                 if (ddr3_default.magic != settings.ddr3.magic)
 182                         printf("Warning: No valid DDR3 data in eeprom.\n");
 183                 if (ddr3_default.version != settings.ddr3.version)
 184                         printf("Warning: DDR3 data version does not match.\n");
 185
 186                 printf("Using default settings\n");
 187                 set_default_ddr3_timings();
 188         }
 189
 190         if (MAGIC_CHIP == settings.chip.magic)
 191                 print_chip_data();
 192         else
 193                 printf("Warning: No chip data in eeprom\n");
 194
 195         print_ddr3_timings();
 196
 197         return draco_read_nand_geometry();
 198 #endif
 199         return 0;
 200 }
 201
 202 #ifdef CONFIG_SPL_BUILD
 203 static void board_init_ddr(void)
 204 {
 205 struct emif_regs draco_ddr3_emif_reg_data = {
 206         .zq_config = 0x50074BE4,
 207 };
 208
 209 struct ddr_data draco_ddr3_data = {
 210 };
 211
 212 struct cmd_control draco_ddr3_cmd_ctrl_data = {
 213 };
 214
 215 struct ctrl_ioregs draco_ddr3_ioregs = {
 216 };
 217
 218         /* pass values from eeprom */
 219         draco_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
 220         draco_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
 221         draco_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
 222         draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
 223                 settings.ddr3.emif_ddr_phy_ctlr_1;
 224         draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
 225         draco_ddr3_emif_reg_data.sdram_config2 = 0x08000000;
 226         draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
 227
 228         draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
 229         draco_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
 230         draco_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
 231         draco_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
 232
 233         draco_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
 234         draco_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
 235         draco_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
 236         draco_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
 237         draco_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
 238         draco_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
 239
 240         draco_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
 241         draco_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
 242         draco_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
 243         draco_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
 244         draco_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
 245
 246         config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data,
 247                    &draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0);
 248 }
 249
 250 static void spl_siemens_board_init(void)
 251 {
 252         return;
 253 }
 254 #endif /* if def CONFIG_SPL_BUILD */
 255
 256 #ifdef CONFIG_BOARD_LATE_INIT
 257 int board_late_init(void)
 258 {
 259         int ret;
 260
 261         ret = draco_read_nand_geometry();
 262         if (ret != 0)
 263                 return ret;
 264
 265         nand_curr_device = 0;
 266         omap_nand_switch_ecc(1, ecc_type);
 267 #ifdef CONFIG_TARGET_ETAMIN
 268         nand_curr_device = 1;
 269         omap_nand_switch_ecc(1, ecc_type);
 270 #endif
 271 #ifdef CONFIG_FACTORYSET
 272         /* Set ASN in environment*/
 273         if (factory_dat.asn[0] != 0) {
 274                 env_set("dtb_name", (char *)factory_dat.asn);
 275         } else {
 276                 /* dtb suffix gets added in load script */
 277                 env_set("dtb_name", "am335x-draco");
 278         }
 279 #else
 280         env_set("dtb_name", "am335x-draco");
 281 #endif
 282
 283         return 0;
 284 }
 285 #endif
 286
 287 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 288         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 289 static void cpsw_control(int enabled)
 290 {
 291         /* VTP can be added here */
 292
 293         return;
 294 }
 295
 296 static struct cpsw_slave_data cpsw_slaves[] = {
 297         {
 298                 .slave_reg_ofs  = 0x208,
 299                 .sliver_reg_ofs = 0xd80,
 300                 .phy_addr       = 0,
 301                 .phy_if         = PHY_INTERFACE_MODE_MII,
 302         },
 303 };
 304
 305 static struct cpsw_platform_data cpsw_data = {
 306         .mdio_base              = CPSW_MDIO_BASE,
 307         .cpsw_base              = CPSW_BASE,
 308         .mdio_div               = 0xff,
 309         .channels               = 4,
 310         .cpdma_reg_ofs          = 0x800,
 311         .slaves                 = 1,
 312         .slave_data             = cpsw_slaves,
 313         .ale_reg_ofs            = 0xd00,
 314         .ale_entries            = 1024,
 315         .host_port_reg_ofs      = 0x108,
 316         .hw_stats_reg_ofs       = 0x900,
 317         .bd_ram_ofs             = 0x2000,
 318         .mac_control            = (1 << 5),
 319         .control                = cpsw_control,
 320         .host_port_num          = 0,
 321         .version                = CPSW_CTRL_VERSION_2,
 322 };
 323
 324 #if defined(CONFIG_DRIVER_TI_CPSW) || \
 325         (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
 326 int board_eth_init(bd_t *bis)
 327 {
 328         struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 329         int n = 0;
 330         int rv;
 331
 332         factoryset_env_set();
 333
 334         /* Set rgmii mode and enable rmii clock to be sourced from chip */
 335         writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
 336
 337         rv = cpsw_register(&cpsw_data);
 338         if (rv < 0)
 339                 printf("Error %d registering CPSW switch\n", rv);
 340         else
 341                 n += rv;
 342         return n;
 343 }
 344
 345 static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc,
 346                           char *const argv[])
 347 {
 348         /* Reset SMSC LAN9303 switch for default configuration */
 349         gpio_request(GPIO_LAN9303_NRST, "nRST");
 350         gpio_direction_output(GPIO_LAN9303_NRST, 0);
 351         /* assert active low reset for 200us */
 352         udelay(200);
 353         gpio_set_value(GPIO_LAN9303_NRST, 1);
 354
 355         return 0;
 356 };
 357
 358 U_BOOT_CMD(
 359         switch_rst, CONFIG_SYS_MAXARGS, 1,      do_switch_reset,
 360         "Reset LAN9303 switch via its reset pin",
 361         ""
 362 );
 363 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
 364 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
 365
 366 #ifdef CONFIG_NAND_CS_INIT
 367 /* GPMC definitions for second nand cs1 */
 368 static const u32 gpmc_nand_config[] = {
 369         ETAMIN_NAND_GPMC_CONFIG1,
 370         ETAMIN_NAND_GPMC_CONFIG2,
 371         ETAMIN_NAND_GPMC_CONFIG3,
 372         ETAMIN_NAND_GPMC_CONFIG4,
 373         ETAMIN_NAND_GPMC_CONFIG5,
 374         ETAMIN_NAND_GPMC_CONFIG6,
 375         /*CONFIG7- computed as params */
 376 };
 377
 378 static void board_nand_cs_init(void)
 379 {
 380         enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[1],
 381                               0x18000000, GPMC_SIZE_16M);
 382 }
 383 #endif
 384
 385 #include "../common/board.c"