board/siemens/draco/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Board functions for TI AM335X based draco board
   4  * (C) Copyright 2013 Siemens Schweiz AG
   5  * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
   6  *
   7  * Based on:
   8  *
   9  * Board functions for TI AM335X based boards
  10  * u-boot:/board/ti/am335x/board.c
  11  *
  12  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  13  */
  14
  15 #include <common.h>
  16 #include <env.h>
  17 #include <errno.h>
  18 #include <spl.h>
  19 #include <asm/arch/cpu.h>
  20 #include <asm/arch/hardware.h>
  21 #include <asm/arch/omap.h>
  22 #include <asm/arch/ddr_defs.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/gpio.h>
  25 #include <asm/arch/mmc_host_def.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <asm/arch/mem.h>
  28 #include <asm/io.h>
  29 #include <asm/emif.h>
  30 #include <asm/gpio.h>
  31 #include <i2c.h>
  32 #include <miiphy.h>
  33 #include <cpsw.h>
  34 #include <watchdog.h>
  35 #include "board.h"
  36 #include "../common/factoryset.h"
  37 #include <nand.h>
  38
  39 #ifdef CONFIG_SPL_BUILD
  40 static struct draco_baseboard_id __attribute__((section(".data"))) settings;
  41
  42 #if DDR_PLL_FREQ == 303
  43 #if !defined(CONFIG_TARGET_ETAMIN)
  44 /* Default@303MHz-i0 */
  45 const struct ddr3_data ddr3_default = {
  46         0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
  47         0x0079, 0x0888A39B, 0x26517FDA, 0x501F84EF, 0x00100206, 0x61A44A32,
  48         0x0000093B, 0x0000014A,
  49         "default name @303MHz           \0",
  50         "default marking                \0",
  51 };
  52 #else
  53 /* etamin board */
  54 const struct ddr3_data ddr3_default = {
  55         0x33524444, 0x56312e36, 0x0080, 0x0000, 0x003A, 0x0010, 0x009F,
  56         0x0050, 0x0888A39B, 0x266D7FDA, 0x501F86AF, 0x00100206, 0x61A44BB2,
  57         0x0000093B, 0x0000018A,
  58         "test-etamin                    \0",
  59         "generic-8Gbit                  \0",
  60 };
  61 #endif
  62 #elif DDR_PLL_FREQ == 400
  63 /* Default@400MHz-i0 */
  64 const struct ddr3_data ddr3_default = {
  65         0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab,
  66         0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232,
  67         0x00000618, 0x0000014A,
  68         "default name @400MHz           \0",
  69         "default marking                \0",
  70 };
  71 #endif
  72
  73 static void set_default_ddr3_timings(void)
  74 {
  75         printf("Set default DDR3 settings\n");
  76         settings.ddr3 = ddr3_default;
  77 }
  78
  79 static void print_ddr3_timings(void)
  80 {
  81         printf("\nDDR3\n");
  82         printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ);
  83         printf("device:\t\t%s\n", settings.ddr3.manu_name);
  84         printf("marking:\t%s\n", settings.ddr3.manu_marking);
  85         printf("%-20s, %-8s, %-8s, %-4s\n", "timing parameters", "eeprom",
  86                "default", "diff");
  87         PRINTARGS(magic);
  88         PRINTARGS(version);
  89         PRINTARGS(ddr3_sratio);
  90         PRINTARGS(iclkout);
  91
  92         PRINTARGS(dt0rdsratio0);
  93         PRINTARGS(dt0wdsratio0);
  94         PRINTARGS(dt0fwsratio0);
  95         PRINTARGS(dt0wrsratio0);
  96
  97         PRINTARGS(sdram_tim1);
  98         PRINTARGS(sdram_tim2);
  99         PRINTARGS(sdram_tim3);
 100
 101         PRINTARGS(emif_ddr_phy_ctlr_1);
 102
 103         PRINTARGS(sdram_config);
 104         PRINTARGS(ref_ctrl);
 105         PRINTARGS(ioctr_val);
 106 }
 107
 108 static void print_chip_data(void)
 109 {
 110         struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 111         dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
 112         printf("\nCPU BOARD\n");
 113         printf("device: \t'%s'\n", settings.chip.sdevname);
 114         printf("hw version: \t'%s'\n", settings.chip.shwver);
 115         printf("max freq: \t%d MHz\n", dpll_mpu_opp100.m);
 116 }
 117 #endif /* CONFIG_SPL_BUILD */
 118
 119 #define AM335X_NAND_ECC_MASK 0x0f
 120 #define AM335X_NAND_ECC_TYPE_16 0x02
 121
 122 static int ecc_type;
 123
 124 struct am335x_nand_geometry {
 125         u32 magic;
 126         u8 nand_geo_addr;
 127         u8 nand_geo_page;
 128         u8 nand_bus;
 129 };
 130
 131 static int draco_read_nand_geometry(void)
 132 {
 133         struct am335x_nand_geometry geo;
 134
 135         /* Read NAND geometry */
 136         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x80, 2,
 137                      (uchar *)&geo, sizeof(struct am335x_nand_geometry))) {
 138                 printf("Could not read the NAND geomtery; something fundamentally wrong on the I2C bus.\n");
 139                 return -EIO;
 140         }
 141         if (geo.magic != 0xa657b310) {
 142                 printf("%s: bad magic: %x\n", __func__, geo.magic);
 143                 return -EFAULT;
 144         }
 145         if ((geo.nand_bus & AM335X_NAND_ECC_MASK) == AM335X_NAND_ECC_TYPE_16)
 146                 ecc_type = 16;
 147         else
 148                 ecc_type = 8;
 149
 150         return 0;
 151 }
 152
 153 /*
 154  * Read header information from EEPROM into global structure.
 155  */
 156 static int read_eeprom(void)
 157 {
 158         /* Check if baseboard eeprom is available */
 159         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
 160                 printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
 161                 return 1;
 162         }
 163
 164 #ifdef CONFIG_SPL_BUILD
 165         /* Read Siemens eeprom data (DDR3) */
 166         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
 167                      (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) {
 168                 printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
 169                 set_default_ddr3_timings();
 170         }
 171         /* Read Siemens eeprom data (CHIP) */
 172         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
 173                      (uchar *)&settings.chip, sizeof(settings.chip)))
 174                 printf("Could not read chip settings\n");
 175
 176         if (ddr3_default.magic == settings.ddr3.magic &&
 177             ddr3_default.version == settings.ddr3.version) {
 178                 printf("Using DDR3 settings from EEPROM\n");
 179         } else {
 180                 if (ddr3_default.magic != settings.ddr3.magic)
 181                         printf("Warning: No valid DDR3 data in eeprom.\n");
 182                 if (ddr3_default.version != settings.ddr3.version)
 183                         printf("Warning: DDR3 data version does not match.\n");
 184
 185                 printf("Using default settings\n");
 186                 set_default_ddr3_timings();
 187         }
 188
 189         if (MAGIC_CHIP == settings.chip.magic)
 190                 print_chip_data();
 191         else
 192                 printf("Warning: No chip data in eeprom\n");
 193
 194         print_ddr3_timings();
 195
 196         return draco_read_nand_geometry();
 197 #endif
 198         return 0;
 199 }
 200
 201 #ifdef CONFIG_SPL_BUILD
 202 static void board_init_ddr(void)
 203 {
 204 struct emif_regs draco_ddr3_emif_reg_data = {
 205         .zq_config = 0x50074BE4,
 206 };
 207
 208 struct ddr_data draco_ddr3_data = {
 209 };
 210
 211 struct cmd_control draco_ddr3_cmd_ctrl_data = {
 212 };
 213
 214 struct ctrl_ioregs draco_ddr3_ioregs = {
 215 };
 216
 217         /* pass values from eeprom */
 218         draco_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
 219         draco_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
 220         draco_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
 221         draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
 222                 settings.ddr3.emif_ddr_phy_ctlr_1;
 223         draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
 224         draco_ddr3_emif_reg_data.sdram_config2 = 0x08000000;
 225         draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
 226
 227         draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
 228         draco_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
 229         draco_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
 230         draco_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
 231
 232         draco_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
 233         draco_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
 234         draco_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
 235         draco_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
 236         draco_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
 237         draco_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
 238
 239         draco_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
 240         draco_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
 241         draco_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
 242         draco_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
 243         draco_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
 244
 245         config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data,
 246                    &draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0);
 247 }
 248
 249 static void spl_siemens_board_init(void)
 250 {
 251         return;
 252 }
 253 #endif /* if def CONFIG_SPL_BUILD */
 254
 255 #ifdef CONFIG_BOARD_LATE_INIT
 256 int board_late_init(void)
 257 {
 258         int ret;
 259
 260         ret = draco_read_nand_geometry();
 261         if (ret != 0)
 262                 return ret;
 263
 264         nand_curr_device = 0;
 265         omap_nand_switch_ecc(1, ecc_type);
 266 #ifdef CONFIG_TARGET_ETAMIN
 267         nand_curr_device = 1;
 268         omap_nand_switch_ecc(1, ecc_type);
 269 #endif
 270 #ifdef CONFIG_FACTORYSET
 271         /* Set ASN in environment*/
 272         if (factory_dat.asn[0] != 0) {
 273                 env_set("dtb_name", (char *)factory_dat.asn);
 274         } else {
 275                 /* dtb suffix gets added in load script */
 276                 env_set("dtb_name", "am335x-draco");
 277         }
 278 #else
 279         env_set("dtb_name", "am335x-draco");
 280 #endif
 281
 282         return 0;
 283 }
 284 #endif
 285
 286 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 287         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 288 static void cpsw_control(int enabled)
 289 {
 290         /* VTP can be added here */
 291
 292         return;
 293 }
 294
 295 static struct cpsw_slave_data cpsw_slaves[] = {
 296         {
 297                 .slave_reg_ofs  = 0x208,
 298                 .sliver_reg_ofs = 0xd80,
 299                 .phy_addr       = 0,
 300                 .phy_if         = PHY_INTERFACE_MODE_MII,
 301         },
 302 };
 303
 304 static struct cpsw_platform_data cpsw_data = {
 305         .mdio_base              = CPSW_MDIO_BASE,
 306         .cpsw_base              = CPSW_BASE,
 307         .mdio_div               = 0xff,
 308         .channels               = 4,
 309         .cpdma_reg_ofs          = 0x800,
 310         .slaves                 = 1,
 311         .slave_data             = cpsw_slaves,
 312         .ale_reg_ofs            = 0xd00,
 313         .ale_entries            = 1024,
 314         .host_port_reg_ofs      = 0x108,
 315         .hw_stats_reg_ofs       = 0x900,
 316         .bd_ram_ofs             = 0x2000,
 317         .mac_control            = (1 << 5),
 318         .control                = cpsw_control,
 319         .host_port_num          = 0,
 320         .version                = CPSW_CTRL_VERSION_2,
 321 };
 322
 323 #if defined(CONFIG_DRIVER_TI_CPSW) || \
 324         (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
 325 int board_eth_init(bd_t *bis)
 326 {
 327         struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 328         int n = 0;
 329         int rv;
 330
 331         factoryset_env_set();
 332
 333         /* Set rgmii mode and enable rmii clock to be sourced from chip */
 334         writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
 335
 336         rv = cpsw_register(&cpsw_data);
 337         if (rv < 0)
 338                 printf("Error %d registering CPSW switch\n", rv);
 339         else
 340                 n += rv;
 341         return n;
 342 }
 343
 344 static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc,
 345                           char *const argv[])
 346 {
 347         /* Reset SMSC LAN9303 switch for default configuration */
 348         gpio_request(GPIO_LAN9303_NRST, "nRST");
 349         gpio_direction_output(GPIO_LAN9303_NRST, 0);
 350         /* assert active low reset for 200us */
 351         udelay(200);
 352         gpio_set_value(GPIO_LAN9303_NRST, 1);
 353
 354         return 0;
 355 };
 356
 357 U_BOOT_CMD(
 358         switch_rst, CONFIG_SYS_MAXARGS, 1,      do_switch_reset,
 359         "Reset LAN9303 switch via its reset pin",
 360         ""
 361 );
 362 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
 363 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
 364
 365 #ifdef CONFIG_NAND_CS_INIT
 366 /* GPMC definitions for second nand cs1 */
 367 static const u32 gpmc_nand_config[] = {
 368         ETAMIN_NAND_GPMC_CONFIG1,
 369         ETAMIN_NAND_GPMC_CONFIG2,
 370         ETAMIN_NAND_GPMC_CONFIG3,
 371         ETAMIN_NAND_GPMC_CONFIG4,
 372         ETAMIN_NAND_GPMC_CONFIG5,
 373         ETAMIN_NAND_GPMC_CONFIG6,
 374         /*CONFIG7- computed as params */
 375 };
 376
 377 static void board_nand_cs_init(void)
 378 {
 379         enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[1],
 380                               0x18000000, GPMC_SIZE_16M);
 381 }
 382 #endif
 383
 384 #include "../common/board.c"