1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012 Renesas Solutions Corp.
13 #include <asm/processor.h>
17 #include <spi_flash.h>
18 #include <linux/delay.h>
22 puts("BOARD: SH7752 evaluation board (R0P7752C00000RZ)\n");
27 static void init_gpio(void)
29 struct gpio_regs *gpio = GPIO_BASE;
30 struct sermux_regs *sermux = SERMUX_BASE;
33 writew(0x0000, &gpio->pacr); /* GETHER */
34 writew(0x0001, &gpio->pbcr); /* INTC */
35 writew(0x0000, &gpio->pccr); /* PWMU, INTC */
36 writew(0xeaff, &gpio->pecr); /* GPIO */
37 writew(0x0000, &gpio->pfcr); /* WDT */
38 writew(0x0000, &gpio->phcr); /* SPI1 */
39 writew(0x0000, &gpio->picr); /* SDHI */
40 writew(0x0003, &gpio->pkcr); /* SerMux */
41 writew(0x0000, &gpio->plcr); /* SerMux */
42 writew(0x0000, &gpio->pmcr); /* RIIC */
43 writew(0x0000, &gpio->pncr); /* USB, SGPIO */
44 writew(0x0000, &gpio->pocr); /* SGPIO */
45 writew(0xd555, &gpio->pqcr); /* GPIO */
46 writew(0x0000, &gpio->prcr); /* RIIC */
47 writew(0x0000, &gpio->pscr); /* RIIC */
48 writeb(0x00, &gpio->pudr);
49 writew(0x5555, &gpio->pucr); /* Debug LED */
50 writew(0x0000, &gpio->pvcr); /* RSPI */
51 writew(0x0000, &gpio->pwcr); /* EVC */
52 writew(0x0000, &gpio->pxcr); /* LBSC */
53 writew(0x0000, &gpio->pycr); /* LBSC */
54 writew(0x0000, &gpio->pzcr); /* eMMC */
55 writew(0xfe00, &gpio->psel0);
56 writew(0xff00, &gpio->psel3);
57 writew(0x771f, &gpio->psel4);
58 writew(0x00ff, &gpio->psel6);
59 writew(0xfc00, &gpio->psel7);
61 writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */
64 static void init_usb_phy(void)
66 struct usb_common_regs *common0 = USB0_COMMON_BASE;
67 struct usb_common_regs *common1 = USB1_COMMON_BASE;
68 struct usb0_phy_regs *phy = USB0_PHY_BASE;
69 struct usb1_port_regs *port = USB1_PORT_BASE;
70 struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
72 writew(0x0100, &phy->reset); /* set reset */
73 /* port0 = USB0, port1 = USB1 */
74 writew(0x0002, &phy->portsel);
75 writel(0x0001, &port->port1sel); /* port1 = Host */
76 writew(0x0111, &phy->reset); /* clear reset */
78 writew(0x4000, &common0->suspmode);
79 writew(0x4000, &common1->suspmode);
81 #if defined(__LITTLE_ENDIAN)
82 writel(0x00000000, &align->ehcidatac);
83 writel(0x00000000, &align->ohcidatac);
87 static void init_gether_mdio(void)
89 struct gpio_regs *gpio = GPIO_BASE;
91 writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);
92 writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */
95 static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
97 struct ether_mac_regs *ether;
101 string_to_enetaddr(mac_string, mac);
104 ether = GETHER0_MAC_BASE;
106 ether = GETHER1_MAC_BASE;
108 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
109 writel(val, ðer->mahr);
110 val = (mac[4] << 8) | mac[5];
111 writel(val, ðer->malr);
114 /*****************************************************************
115 * This PMB must be set on this timing. The lowlevel_init is run on
116 * Area 0(phys 0x00000000), so we have to map it.
118 * The new PMB table is following:
119 * ent virt phys v sz c wt
120 * 0 0xa0000000 0x40000000 1 128M 0 1
121 * 1 0xa8000000 0x48000000 1 128M 0 1
122 * 2 0xb0000000 0x50000000 1 128M 0 1
123 * 3 0xb8000000 0x58000000 1 128M 0 1
124 * 4 0x80000000 0x40000000 1 128M 1 1
125 * 5 0x88000000 0x48000000 1 128M 1 1
126 * 6 0x90000000 0x50000000 1 128M 1 1
127 * 7 0x98000000 0x58000000 1 128M 1 1
129 static void set_pmb_on_board_init(void)
131 struct mmu_regs *mmu = MMU_BASE;
134 writel(0x00000004, &mmu->mmucr);
136 /* delete PMB for SPIBOOT */
137 writel(0, PMB_ADDR_BASE(0));
138 writel(0, PMB_DATA_BASE(0));
140 /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
141 /* ppn ub v s1 s0 c wt */
142 writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
143 writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
144 writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
145 writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
146 writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
147 writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
148 writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
149 writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
150 writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
151 writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
152 writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
153 writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
159 set_pmb_on_board_init();
167 int board_mmc_init(bd_t *bis)
169 struct gpio_regs *gpio = GPIO_BASE;
171 writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);
172 writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
174 writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */
177 return mmcif_mmc_init();
180 static int get_sh_eth_mac_raw(unsigned char *buf, int size)
182 #ifdef CONFIG_DEPRECATED
183 struct spi_flash *spi;
186 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
188 printf("%s: spi_flash probe failed.\n", __func__);
192 ret = spi_flash_read(spi, SH7752EVB_ETHERNET_MAC_BASE, size, buf);
194 printf("%s: spi_flash read failed.\n", __func__);
204 static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
206 memcpy(mac_string, &buf[channel * (SH7752EVB_ETHERNET_MAC_SIZE + 1)],
207 SH7752EVB_ETHERNET_MAC_SIZE);
208 mac_string[SH7752EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
213 static void init_ethernet_mac(void)
222 printf("%s: malloc failed.\n", __func__);
225 get_sh_eth_mac_raw(buf, 256);
227 /* Gigabit Ethernet */
228 for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
229 get_sh_eth_mac(i, mac_string, buf);
231 env_set("ethaddr", mac_string);
233 sprintf(env_string, "eth%daddr", i);
234 env_set(env_string, mac_string);
236 set_mac_to_sh_giga_eth_register(i, mac_string);
242 int board_late_init(void)
249 #ifdef CONFIG_DEPRECATED
250 int do_write_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
253 char mac_string[256];
254 struct spi_flash *spi;
260 printf("%s: malloc failed.\n", __func__);
264 get_sh_eth_mac_raw(buf, 256);
266 /* print current MAC address */
267 for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
268 get_sh_eth_mac(i, mac_string, buf);
269 printf("GETHERC ch%d = %s\n", i, mac_string);
276 memset(mac_string, 0xff, sizeof(mac_string));
277 sprintf(mac_string, "%s\t%s",
280 /* write MAC data to SPI rom */
281 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
283 printf("%s: spi_flash probe failed.\n", __func__);
287 ret = spi_flash_erase(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
288 SH7752EVB_SPI_SECTOR_SIZE);
290 printf("%s: spi_flash erase failed.\n", __func__);
294 ret = spi_flash_write(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
295 sizeof(mac_string), mac_string);
297 printf("%s: spi_flash write failed.\n", __func__);
303 puts("The writing of the MAC address to SPI ROM was completed.\n");
309 write_mac, 3, 1, do_write_mac,
310 "write MAC address for GETHERC",
311 "[GETHERC ch0] [GETHERC ch1]\n"