1 // SPDX-License-Identifier: GPL-2.0
3 * board/renesas/koelsch/koelsch.c
5 * Copyright (C) 2013 Renesas Electronics Corporation
16 #include <dm/platform_data/serial_sh.h>
17 #include <env_internal.h>
18 #include <asm/processor.h>
19 #include <asm/mach-types.h>
21 #include <linux/delay.h>
22 #include <linux/errno.h>
23 #include <asm/arch/sys_proto.h>
25 #include <asm/arch/rmobile.h>
26 #include <asm/arch/rcar-mstp.h>
27 #include <asm/arch/sh_sdhi.h>
34 DECLARE_GLOBAL_DATA_PTR;
36 #define CLK2MHZ(clk) (clk / 1000 / 1000)
39 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
40 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
44 writel(0xA5A5A500, &rwdt->rwtcsra);
45 writel(0xA5A5A500, &swdt->swtcsra);
47 /* CPU frequency setting. Set to 1.5GHz */
48 stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
49 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
55 #define TMU0_MSTP125 BIT(25)
57 #define SD1CKCR 0xE6150078
58 #define SD2CKCR 0xE615026C
59 #define SD_97500KHZ 0x7
61 int board_early_init_f(void)
63 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
66 * SD0 clock is set to 97.5MHz by default.
67 * Set SD1 and SD2 to the 97.5MHz as well.
69 writel(SD_97500KHZ, SD1CKCR);
70 writel(SD_97500KHZ, SD2CKCR);
75 #define ETHERNET_PHY_RESET 176 /* GPIO 5 22 */
79 /* adress of boot parameters */
80 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
82 /* Force ethernet PHY out of reset */
83 gpio_request(ETHERNET_PHY_RESET, "phy_reset");
84 gpio_direction_output(ETHERNET_PHY_RESET, 0);
86 gpio_direction_output(ETHERNET_PHY_RESET, 1);
93 if (fdtdec_setup_mem_size_base() != 0)
99 int dram_init_banksize(void)
101 fdtdec_setup_memory_banksize();
106 /* Koelsch has KSZ8041NL/RNL */
107 #define PHY_CONTROL1 0x1E
108 #define PHY_LED_MODE 0xC000
109 #define PHY_LED_MODE_ACK 0x4000
110 int board_phy_config(struct phy_device *phydev)
112 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
113 ret &= ~PHY_LED_MODE;
114 ret |= PHY_LED_MODE_ACK;
115 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
120 void reset_cpu(ulong addr)
123 const u8 pmic_bus = 6;
124 const u8 pmic_addr = 0x58;
128 ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
132 ret = dm_i2c_read(dev, 0x13, &data, 1);
138 ret = dm_i2c_write(dev, 0x13, &data, 1);
143 enum env_location env_get_location(enum env_operation op, int prio)
145 const u32 load_magic = 0xb33fc0de;
147 /* Block environment access if loaded using JTAG */
148 if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
155 return ENVL_SPI_FLASH;