board/renesas/blanche/blanche.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * board/renesas/blanche/blanche.c
   4  *     This file is blanche board support.
   5  *
   6  * Copyright (C) 2016 Renesas Electronics Corporation
   7  */
   8
   9 #include <common.h>
  10 #include <asm/arch/mmc.h>
  11 #include <asm/arch/rcar-mstp.h>
  12 #include <asm/arch/rmobile.h>
  13 #include <asm/arch/sh_sdhi.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <asm/gpio.h>
  16 #include <asm/io.h>
  17 #include <asm/mach-types.h>
  18 #include <asm/processor.h>
  19 #include <dm.h>
  20 #include <dm/platform_data/serial_sh.h>
  21 #include <environment.h>
  22 #include <i2c.h>
  23 #include <linux/errno.h>
  24 #include <malloc.h>
  25 #include <miiphy.h>
  26 #include <mmc.h>
  27 #include <netdev.h>
  28 #include "qos.h"
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 #define CPG_PLL1CR      0xE6150028
  33 #define CPG_PLL3CR      0xE61500DC
  34
  35 #define TMU0_MSTP125    BIT(25)
  36 #define QSPI_MSTP917    BIT(17)
  37
  38 struct reg_config {
  39         u16     off;
  40         u32     val;
  41 };
  42
  43 static void blanche_init_sys(void)
  44 {
  45         struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
  46         struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
  47         u32 cpu_type;
  48
  49         cpu_type = rmobile_get_cpu_type();
  50         if (cpu_type == 0x4A) {
  51                 writel(0x4D000000, CPG_PLL1CR);
  52                 writel(0x4F000000, CPG_PLL3CR);
  53         }
  54
  55         /* Watchdog init */
  56         writel(0xA5A5A500, &rwdt->rwtcsra);
  57         writel(0xA5A5A500, &swdt->swtcsra);
  58 }
  59
  60 static void blanche_init_pfc(void)
  61 {
  62         static const struct reg_config pfc_with_unlock[] = {
  63                 { 0x0004, 0x0bffffff },
  64                 { 0x0008, 0x002fffff },
  65                 { 0x0014, 0x00000fff },
  66                 { 0x0018, 0x00010fff },
  67                 { 0x001c, 0x00010fff },
  68                 { 0x0020, 0x00010fff },
  69                 { 0x0024, 0x00010fff },
  70                 { 0x0028, 0x00010fff },
  71                 { 0x002c, 0x04006000 },
  72                 { 0x0030, 0x303fefe0 },
  73                 { 0x0058, 0x0002000e },
  74         };
  75
  76         static const struct reg_config pfc_without_unlock[] = {
  77                 { 0x0108, 0x00000000 },
  78                 { 0x010c, 0x0803FF40 },
  79                 { 0x0110, 0x0000FFFF },
  80                 { 0x0114, 0x00010FFF },
  81                 { 0x011c, 0x0001AFFF },
  82                 { 0x0124, 0x0001CFFF },
  83                 { 0x0128, 0xC0438001 },
  84                 { 0x012c, 0x0FC00007 },
  85         };
  86
  87         static const u32 pfc_base = 0xe6060000;
  88
  89         unsigned int i;
  90
  91         for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
  92                 writel(~pfc_with_unlock[i].val, pfc_base);
  93                 writel(pfc_with_unlock[i].val,
  94                        pfc_base | pfc_with_unlock[i].off);
  95         }
  96
  97         for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
  98                 writel(pfc_without_unlock[i].val,
  99                        pfc_base | pfc_without_unlock[i].off);
 100 }
 101
 102 static void blanche_init_lbsc(void)
 103 {
 104         static const struct reg_config lbsc_config[] = {
 105                 { 0x00, 0x00000020 },
 106                 { 0x08, 0x00002020 },
 107                 { 0x30, 0x2a103320 },
 108                 { 0x38, 0x19102110 },
 109         };
 110
 111         static const u32 lbsc_base = 0xfec00200;
 112
 113         unsigned int i;
 114
 115         for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
 116                 writel(lbsc_config[i].val,
 117                        lbsc_base | lbsc_config[i].off);
 118                 writel(lbsc_config[i].val,
 119                        lbsc_base | (lbsc_config[i].off + 4));
 120         }
 121 }
 122
 123 #if defined(CONFIG_MTD_NOR_FLASH)
 124 static void dbsc_wait(u16 reg)
 125 {
 126         static const u32 dbsc3_0_base = DBSC3_0_BASE;
 127
 128         while (!(readl(dbsc3_0_base + reg) & BIT(0)))
 129                 ;
 130 }
 131
 132 static void blanche_init_dbsc(void)
 133 {
 134         static const struct reg_config dbsc_config1[] = {
 135                 { 0x0280, 0x0000a55a },
 136                 { 0x0018, 0x21000000 },
 137                 { 0x0018, 0x11000000 },
 138                 { 0x0018, 0x10000000 },
 139                 { 0x0290, 0x00000001 },
 140                 { 0x02a0, 0x80000000 },
 141                 { 0x0290, 0x00000004 },
 142         };
 143
 144         static const struct reg_config dbsc_config2[] = {
 145                 { 0x0290, 0x00000006 },
 146                 { 0x02a0, 0x0001c000 },
 147         };
 148
 149         static const struct reg_config dbsc_config4[] = {
 150                 { 0x0290, 0x0000000f },
 151                 { 0x02a0, 0x00181ee4 },
 152                 { 0x0290, 0x00000010 },
 153                 { 0x02a0, 0xf00464db },
 154                 { 0x0290, 0x00000061 },
 155                 { 0x02a0, 0x0000008d },
 156                 { 0x0290, 0x00000001 },
 157                 { 0x02a0, 0x00000073 },
 158                 { 0x0020, 0x00000007 },
 159                 { 0x0024, 0x0f030a02 },
 160                 { 0x0030, 0x00000001 },
 161                 { 0x00b0, 0x00000000 },
 162                 { 0x0040, 0x0000000b },
 163                 { 0x0044, 0x00000008 },
 164                 { 0x0048, 0x00000000 },
 165                 { 0x0050, 0x0000000b },
 166                 { 0x0054, 0x000c000b },
 167                 { 0x0058, 0x00000027 },
 168                 { 0x005c, 0x0000001c },
 169                 { 0x0060, 0x00000006 },
 170                 { 0x0064, 0x00000020 },
 171                 { 0x0068, 0x00000008 },
 172                 { 0x006c, 0x0000000c },
 173                 { 0x0070, 0x00000009 },
 174                 { 0x0074, 0x00000012 },
 175                 { 0x0078, 0x000000d0 },
 176                 { 0x007c, 0x00140005 },
 177                 { 0x0080, 0x00050004 },
 178                 { 0x0084, 0x70233005 },
 179                 { 0x0088, 0x000c0000 },
 180                 { 0x008c, 0x00000300 },
 181                 { 0x0090, 0x00000040 },
 182                 { 0x0100, 0x00000001 },
 183                 { 0x00c0, 0x00020001 },
 184                 { 0x00c8, 0x20082004 },
 185                 { 0x0380, 0x00020002 },
 186                 { 0x0390, 0x0000001f },
 187         };
 188
 189         static const struct reg_config dbsc_config5[] = {
 190                 { 0x0244, 0x00000011 },
 191                 { 0x0290, 0x00000003 },
 192                 { 0x02a0, 0x0300c4e1 },
 193                 { 0x0290, 0x00000023 },
 194                 { 0x02a0, 0x00fcdb60 },
 195                 { 0x0290, 0x00000011 },
 196                 { 0x02a0, 0x1000040b },
 197                 { 0x0290, 0x00000012 },
 198                 { 0x02a0, 0x9d9cbb66 },
 199                 { 0x0290, 0x00000013 },
 200                 { 0x02a0, 0x1a868400 },
 201                 { 0x0290, 0x00000014 },
 202                 { 0x02a0, 0x300214d8 },
 203                 { 0x0290, 0x00000015 },
 204                 { 0x02a0, 0x00000d70 },
 205                 { 0x0290, 0x00000016 },
 206                 { 0x02a0, 0x00000004 },
 207                 { 0x0290, 0x00000017 },
 208                 { 0x02a0, 0x00000018 },
 209                 { 0x0290, 0x0000001a },
 210                 { 0x02a0, 0x910035c7 },
 211                 { 0x0290, 0x00000004 },
 212         };
 213
 214         static const struct reg_config dbsc_config6[] = {
 215                 { 0x0290, 0x00000001 },
 216                 { 0x02a0, 0x00000181 },
 217                 { 0x0018, 0x11000000 },
 218                 { 0x0290, 0x00000004 },
 219         };
 220
 221         static const struct reg_config dbsc_config7[] = {
 222                 { 0x0290, 0x00000001 },
 223                 { 0x02a0, 0x0000fe01 },
 224                 { 0x0304, 0x00000000 },
 225                 { 0x00f4, 0x01004c20 },
 226                 { 0x00f8, 0x014000aa },
 227                 { 0x00e0, 0x00000140 },
 228                 { 0x00e4, 0x00081860 },
 229                 { 0x00e8, 0x00010000 },
 230                 { 0x0290, 0x00000004 },
 231         };
 232
 233         static const struct reg_config dbsc_config8[] = {
 234                 { 0x0014, 0x00000001 },
 235                 { 0x0010, 0x00000001 },
 236                 { 0x0280, 0x00000000 },
 237         };
 238
 239         static const u32 dbsc3_0_base = DBSC3_0_BASE;
 240         unsigned int i;
 241
 242         for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
 243                 writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
 244
 245         dbsc_wait(0x2a0);
 246
 247         for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++)
 248                 writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
 249
 250         for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
 251                 writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
 252
 253         dbsc_wait(0x240);
 254
 255         for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
 256                 writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
 257
 258         dbsc_wait(0x2a0);
 259
 260         for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
 261                 writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
 262
 263         dbsc_wait(0x2a0);
 264
 265         for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
 266                 writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
 267
 268         dbsc_wait(0x2a0);
 269
 270         for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
 271                 writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
 272
 273 }
 274
 275 static void s_init_wait(volatile unsigned int cnt)
 276 {
 277         volatile u32 i = cnt * 0x10000;
 278
 279         while (i-- > 0)
 280                 ;
 281 }
 282 #endif
 283
 284 void s_init(void)
 285 {
 286         blanche_init_sys();
 287         qos_init();
 288         blanche_init_pfc();
 289         blanche_init_lbsc();
 290 #if defined(CONFIG_MTD_NOR_FLASH)
 291         s_init_wait(10);
 292         blanche_init_dbsc();
 293 #endif /* CONFIG_MTD_NOR_FLASH */
 294 }
 295
 296 int board_early_init_f(void)
 297 {
 298         /* TMU0 */
 299         mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
 300         /* QSPI */
 301         mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
 302
 303         return 0;
 304 }
 305
 306 int board_init(void)
 307 {
 308         /* adress of boot parameters */
 309         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 310
 311         return 0;
 312 }
 313
 314 /* Added for BLANCHE(R-CarV2H board) */
 315 int board_eth_init(bd_t *bis)
 316 {
 317         int rc = 0;
 318
 319 #ifdef CONFIG_SMC911X
 320         struct eth_device *dev;
 321         uchar eth_addr[6];
 322
 323         rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
 324
 325         if (!eth_env_get_enetaddr("ethaddr", eth_addr)) {
 326                 dev = eth_get_dev_by_index(0);
 327                 if (dev) {
 328                         eth_env_set_enetaddr("ethaddr", dev->enetaddr);
 329                 } else {
 330                         printf("blanche: Couldn't get eth device\n");
 331                         rc = -1;
 332                 }
 333         }
 334
 335 #endif
 336
 337         return rc;
 338 }
 339
 340 int dram_init(void)
 341 {
 342         if (fdtdec_setup_mem_size_base() != 0)
 343                 return -EINVAL;
 344
 345         return 0;
 346 }
 347
 348 int dram_init_banksize(void)
 349 {
 350         fdtdec_setup_memory_banksize();
 351
 352         return 0;
 353 }
 354
 355 void reset_cpu(ulong addr)
 356 {
 357 }