board/phytec/pfla02/pfla02.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 Stefano Babic <sbabic@denx.de>
   4  */
   5
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <init.h>
   9 #include <log.h>
  10 #include <net.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/iomux.h>
  15 #include <asm/arch/crm_regs.h>
  16 #include <asm/arch/iomux.h>
  17 #include <asm/arch/mx6-pins.h>
  18 #include <asm/mach-imx/iomux-v3.h>
  19 #include <asm/mach-imx/boot_mode.h>
  20 #include <asm/mach-imx/mxc_i2c.h>
  21 #include <asm/mach-imx/spi.h>
  22 #include <env.h>
  23 #include <linux/delay.h>
  24 #include <linux/errno.h>
  25 #include <asm/gpio.h>
  26 #include <mmc.h>
  27 #include <i2c.h>
  28 #include <fsl_esdhc_imx.h>
  29 #include <nand.h>
  30 #include <miiphy.h>
  31 #include <netdev.h>
  32 #include <asm/arch/sys_proto.h>
  33 #include <asm/sections.h>
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  38         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  39         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  40
  41 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  42         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  43         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  44
  45 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  46         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  47
  48 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  49                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  50
  51 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  52         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  53         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  54
  55 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  56
  57 #define ASRC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP  |     \
  58                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  59
  60 #define NAND_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  61                PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  62
  63 #define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 14)
  64 #define USDHC2_CD_GPIO  IMX_GPIO_NR(1, 4)
  65 #define GREEN_LED       IMX_GPIO_NR(2, 31)
  66 #define RED_LED         IMX_GPIO_NR(1, 30)
  67 #define IMX6Q_DRIVE_STRENGTH    0x30
  68
  69 int dram_init(void)
  70 {
  71         gd->ram_size = imx_ddr_size();
  72         return 0;
  73 }
  74
  75 static iomux_v3_cfg_t const uart4_pads[] = {
  76         IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  77         IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  78 };
  79
  80 static iomux_v3_cfg_t const enet_pads[] = {
  81         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  82         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC       | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  83         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  84         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  85         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  86         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  87         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  88         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  89                         MUX_PAD_CTRL(ENET_PAD_CTRL)),
  90         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
  91                         MUX_PAD_CTRL(ENET_PAD_CTRL)),
  92         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  93         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  94         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  95         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  96         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  97         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
  98                         MUX_PAD_CTRL(ENET_PAD_CTRL)),
  99         IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 100 };
 101
 102 static iomux_v3_cfg_t const ecspi3_pads[] = {
 103         IOMUX_PADS(PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 104         IOMUX_PADS(PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 105         IOMUX_PADS(PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 106         IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24  | MUX_PAD_CTRL(NO_PAD_CTRL)),
 107 };
 108
 109 static iomux_v3_cfg_t const gpios_pads[] = {
 110         IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 111         IOMUX_PADS(PAD_SD4_DAT4__GPIO2_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 112         IOMUX_PADS(PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 113         IOMUX_PADS(PAD_SD4_DAT6__GPIO2_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 114         IOMUX_PADS(PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 115         IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 116         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 117         IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 118 };
 119
 120 #ifdef CONFIG_CMD_NAND
 121 /* NAND */
 122 static iomux_v3_cfg_t const nfc_pads[] = {
 123         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE      | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 124         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE      | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 125         IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 126         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B  | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 127         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 128         IOMUX_PADS(PAD_NANDF_CS1__NAND_CE1_B    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 129         IOMUX_PADS(PAD_NANDF_CS2__NAND_CE2_B    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 130         IOMUX_PADS(PAD_NANDF_CS3__NAND_CE3_B    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 131         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B       | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 132         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B       | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 133         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 134         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 135         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 136         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 137         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 138         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 139         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 140         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 141         IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS       | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 142 };
 143 #endif
 144
 145 static struct i2c_pads_info i2c_pad_info = {
 146         .scl = {
 147                 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | I2C_PAD,
 148                 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | I2C_PAD,
 149                 .gp = IMX_GPIO_NR(3, 21)
 150         },
 151         .sda = {
 152                 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | I2C_PAD,
 153                 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | I2C_PAD,
 154                 .gp = IMX_GPIO_NR(3, 28)
 155         }
 156 };
 157
 158 static struct fsl_esdhc_cfg usdhc_cfg[] = {
 159         {USDHC3_BASE_ADDR,
 160         .max_bus_width = 4},
 161         {.esdhc_base = USDHC2_BASE_ADDR,
 162         .max_bus_width = 4},
 163 };
 164
 165 #if !defined(CONFIG_SPL_BUILD)
 166 static iomux_v3_cfg_t const usdhc2_pads[] = {
 167         IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 168         IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 169         IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 170         IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 171         IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 172         IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 173         IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 174         IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04       | MUX_PAD_CTRL(NO_PAD_CTRL)),
 175 };
 176 #endif
 177
 178 static iomux_v3_cfg_t const usdhc3_pads[] = {
 179         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 180         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 181         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 182         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 183         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 184         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 185         IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 186         IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 187         IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 188         IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 189 };
 190
 191 int board_mmc_get_env_dev(int devno)
 192 {
 193         return devno - 1;
 194 }
 195
 196 int board_mmc_getcd(struct mmc *mmc)
 197 {
 198         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 199         int ret = 0;
 200
 201         switch (cfg->esdhc_base) {
 202         case USDHC2_BASE_ADDR:
 203                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 204                 ret = 1;
 205                 break;
 206         case USDHC3_BASE_ADDR:
 207                 ret = 1;
 208                 break;
 209         }
 210
 211         return ret;
 212 }
 213
 214 #ifndef CONFIG_SPL_BUILD
 215 int board_mmc_init(bd_t *bis)
 216 {
 217         int ret;
 218         int i;
 219
 220         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 221                 switch (i) {
 222                 case 0:
 223                         SETUP_IOMUX_PADS(usdhc3_pads);
 224                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 225                         break;
 226                 case 1:
 227                         SETUP_IOMUX_PADS(usdhc2_pads);
 228                         gpio_direction_input(USDHC2_CD_GPIO);
 229                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 230                         break;
 231                 default:
 232                         printf("Warning: you configured more USDHC controllers"
 233                                "(%d) then supported by the board (%d)\n",
 234                                i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 235                         return -EINVAL;
 236                 }
 237
 238                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 239                 if (ret)
 240                         return ret;
 241         }
 242
 243         return 0;
 244 }
 245 #endif
 246
 247 static void setup_iomux_uart(void)
 248 {
 249         SETUP_IOMUX_PADS(uart4_pads);
 250 }
 251
 252 static void setup_iomux_enet(void)
 253 {
 254         SETUP_IOMUX_PADS(enet_pads);
 255
 256         gpio_direction_output(ENET_PHY_RESET_GPIO, 0);
 257         mdelay(10);
 258         gpio_set_value(ENET_PHY_RESET_GPIO, 1);
 259         mdelay(30);
 260 }
 261
 262 static void setup_spi(void)
 263 {
 264         gpio_request(IMX_GPIO_NR(4, 24), "spi_cs0");
 265         gpio_direction_output(IMX_GPIO_NR(4, 24), 1);
 266
 267         SETUP_IOMUX_PADS(ecspi3_pads);
 268
 269         enable_spi_clk(true, 2);
 270 }
 271
 272 static void setup_gpios(void)
 273 {
 274         SETUP_IOMUX_PADS(gpios_pads);
 275 }
 276
 277 #ifdef CONFIG_CMD_NAND
 278 static void setup_gpmi_nand(void)
 279 {
 280         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 281
 282         /* config gpmi nand iomux */
 283         SETUP_IOMUX_PADS(nfc_pads);
 284
 285         /* gate ENFC_CLK_ROOT clock first,before clk source switch */
 286         clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 287
 288         /* config gpmi and bch clock to 100 MHz */
 289         clrsetbits_le32(&mxc_ccm->cs2cdr,
 290                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 291                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 292                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 293                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 294                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 295                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 296
 297         /* enable ENFC_CLK_ROOT clock */
 298         setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 299
 300         /* enable gpmi and bch clock gating */
 301         setbits_le32(&mxc_ccm->CCGR4,
 302                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 303                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 304                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 305                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 306                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 307
 308         /* enable apbh clock gating */
 309         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 310 }
 311 #endif
 312
 313 /*
 314  * Board revision is coded in 4 GPIOs
 315  */
 316 u32 get_board_rev(void)
 317 {
 318         u32 rev;
 319         int i;
 320
 321         for (i = 0, rev = 0; i < 4; i++)
 322                 rev |= (gpio_get_value(IMX_GPIO_NR(2, 12 + i)) << i);
 323
 324         return 16 - rev;
 325 }
 326
 327 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 328 {
 329         if (bus != 2 || (cs != 0))
 330                 return -EINVAL;
 331
 332         return IMX_GPIO_NR(4, 24);
 333 }
 334
 335 int board_eth_init(bd_t *bis)
 336 {
 337         setup_iomux_enet();
 338
 339         return cpu_eth_init(bis);
 340 }
 341
 342 int board_early_init_f(void)
 343 {
 344         setup_iomux_uart();
 345
 346         return 0;
 347 }
 348
 349 int board_init(void)
 350 {
 351         /* address of boot parameters */
 352         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 353
 354 #ifdef CONFIG_SYS_I2C_MXC
 355         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info);
 356 #endif
 357
 358 #ifdef CONFIG_MXC_SPI
 359         setup_spi();
 360 #endif
 361
 362         setup_gpios();
 363
 364 #ifdef CONFIG_CMD_NAND
 365         setup_gpmi_nand();
 366 #endif
 367         return 0;
 368 }
 369
 370
 371 #ifdef CONFIG_CMD_BMODE
 372 /*
 373  * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
 374  * see Table 8-11 and Table 5-9
 375  *  BOOT_CFG1[7] = 1 (boot from NAND)
 376  *  BOOT_CFG1[5] = 0 - raw NAND
 377  *  BOOT_CFG1[4] = 0 - default pad settings
 378  *  BOOT_CFG1[3:2] = 00 - devices = 1
 379  *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
 380  *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
 381  *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
 382  *  BOOT_CFG2[0] = 0 - Reset time 12ms
 383  */
 384 static const struct boot_mode board_boot_modes[] = {
 385         /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
 386         {"nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00)},
 387         {"mmc0",  MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 388         {NULL, 0},
 389 };
 390 #endif
 391
 392 int board_late_init(void)
 393 {
 394         char buf[10];
 395 #ifdef CONFIG_CMD_BMODE
 396         add_board_boot_modes(board_boot_modes);
 397 #endif
 398
 399         snprintf(buf, sizeof(buf), "%d", get_board_rev());
 400         env_set("board_rev", buf);
 401
 402         return 0;
 403 }
 404
 405 #ifdef CONFIG_SPL_BUILD
 406 #include <asm/arch/mx6-ddr.h>
 407 #include <spl.h>
 408 #include <linux/libfdt.h>
 409
 410 #define MX6_PHYFLEX_ERR006282   IMX_GPIO_NR(2, 11)
 411 static void phyflex_err006282_workaround(void)
 412 {
 413         /*
 414          * Boards beginning with 1362.2 have the SD4_DAT3 pin connected
 415          * to the CMIC. If this pin isn't toggled within 10s the boards
 416          * reset. The pin is unconnected on older boards, so we do not
 417          * need a check for older boards before applying this fixup.
 418          */
 419
 420         gpio_direction_output(MX6_PHYFLEX_ERR006282, 0);
 421         mdelay(2);
 422         gpio_direction_output(MX6_PHYFLEX_ERR006282, 1);
 423         mdelay(2);
 424         gpio_set_value(MX6_PHYFLEX_ERR006282, 0);
 425
 426         gpio_direction_input(MX6_PHYFLEX_ERR006282);
 427 }
 428
 429 static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
 430         .dram_sdclk_0 = 0x00000030,
 431         .dram_sdclk_1 = 0x00000030,
 432         .dram_cas = 0x00000030,
 433         .dram_ras = 0x00000030,
 434         .dram_reset = 0x00000030,
 435         .dram_sdcke0 = 0x00003000,
 436         .dram_sdcke1 = 0x00003000,
 437         .dram_sdba2 = 0x00000030,
 438         .dram_sdodt0 = 0x00000030,
 439         .dram_sdodt1 = 0x00000030,
 440
 441         .dram_sdqs0 = 0x00000028,
 442         .dram_sdqs1 = 0x00000028,
 443         .dram_sdqs2 = 0x00000028,
 444         .dram_sdqs3 = 0x00000028,
 445         .dram_sdqs4 = 0x00000028,
 446         .dram_sdqs5 = 0x00000028,
 447         .dram_sdqs6 = 0x00000028,
 448         .dram_sdqs7 = 0x00000028,
 449         .dram_dqm0 = 0x00000028,
 450         .dram_dqm1 = 0x00000028,
 451         .dram_dqm2 = 0x00000028,
 452         .dram_dqm3 = 0x00000028,
 453         .dram_dqm4 = 0x00000028,
 454         .dram_dqm5 = 0x00000028,
 455         .dram_dqm6 = 0x00000028,
 456         .dram_dqm7 = 0x00000028,
 457 };
 458
 459 static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
 460         .grp_ddr_type =  0x000C0000,
 461         .grp_ddrmode_ctl =  0x00020000,
 462         .grp_ddrpke =  0x00000000,
 463         .grp_addds = IMX6Q_DRIVE_STRENGTH,
 464         .grp_ctlds = IMX6Q_DRIVE_STRENGTH,
 465         .grp_ddrmode =  0x00020000,
 466         .grp_b0ds = 0x00000028,
 467         .grp_b1ds = 0x00000028,
 468         .grp_b2ds = 0x00000028,
 469         .grp_b3ds = 0x00000028,
 470         .grp_b4ds = 0x00000028,
 471         .grp_b5ds = 0x00000028,
 472         .grp_b6ds = 0x00000028,
 473         .grp_b7ds = 0x00000028,
 474 };
 475
 476 static const struct mx6_mmdc_calibration mx6_mmcd_calib = {
 477         .p0_mpwldectrl0 =  0x00110011,
 478         .p0_mpwldectrl1 =  0x00240024,
 479         .p1_mpwldectrl0 =  0x00260038,
 480         .p1_mpwldectrl1 =  0x002C0038,
 481         .p0_mpdgctrl0 =  0x03400350,
 482         .p0_mpdgctrl1 =  0x03440340,
 483         .p1_mpdgctrl0 =  0x034C0354,
 484         .p1_mpdgctrl1 =  0x035C033C,
 485         .p0_mprddlctl =  0x322A2A2A,
 486         .p1_mprddlctl =  0x302C2834,
 487         .p0_mpwrdlctl =  0x34303834,
 488         .p1_mpwrdlctl =  0x422A3E36,
 489 };
 490
 491 /* Index in RAM Chip array */
 492 enum {
 493         RAM_MT64K,
 494         RAM_MT128K,
 495         RAM_MT256K
 496 };
 497
 498 static struct mx6_ddr3_cfg mt41k_xx[] = {
 499 /* MT41K64M16JT-125 (1Gb density) */
 500         {
 501         .mem_speed = 1600,
 502         .density = 1,
 503         .width = 16,
 504         .banks = 8,
 505         .rowaddr = 13,
 506         .coladdr = 10,
 507         .pagesz = 2,
 508         .trcd = 1375,
 509         .trcmin = 4875,
 510         .trasmin = 3500,
 511         .SRT       = 1,
 512         },
 513
 514 /* MT41K256M16JT-125 (2Gb density) */
 515         {
 516         .mem_speed = 1600,
 517         .density = 2,
 518         .width = 16,
 519         .banks = 8,
 520         .rowaddr = 14,
 521         .coladdr = 10,
 522         .pagesz = 2,
 523         .trcd = 1375,
 524         .trcmin = 4875,
 525         .trasmin = 3500,
 526         .SRT       = 1,
 527         },
 528
 529 /* MT41K256M16JT-125 (4Gb density) */
 530         {
 531         .mem_speed = 1600,
 532         .density = 4,
 533         .width = 16,
 534         .banks = 8,
 535         .rowaddr = 15,
 536         .coladdr = 10,
 537         .pagesz = 2,
 538         .trcd = 1375,
 539         .trcmin = 4875,
 540         .trasmin = 3500,
 541         .SRT       = 1,
 542         }
 543 };
 544
 545 static void ccgr_init(void)
 546 {
 547         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 548
 549         writel(0x00C03F3F, &ccm->CCGR0);
 550         writel(0x0030FC03, &ccm->CCGR1);
 551         writel(0x0FFFC000, &ccm->CCGR2);
 552         writel(0x3FF00000, &ccm->CCGR3);
 553         writel(0x00FFF300, &ccm->CCGR4);
 554         writel(0x0F0000C3, &ccm->CCGR5);
 555         writel(0x000003FF, &ccm->CCGR6);
 556 }
 557
 558 static void spl_dram_init(struct mx6_ddr_sysinfo *sysinfo,
 559                                 struct mx6_ddr3_cfg *mem_ddr)
 560 {
 561         mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 562         mx6_dram_cfg(sysinfo, &mx6_mmcd_calib, mem_ddr);
 563 }
 564
 565 int board_mmc_init(bd_t *bis)
 566 {
 567         if (spl_boot_device() == BOOT_DEVICE_SPI)
 568                 printf("MMC SEtup, Boot SPI");
 569
 570         SETUP_IOMUX_PADS(usdhc3_pads);
 571         usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 572         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 573         usdhc_cfg[0].max_bus_width = 4;
 574         gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 575
 576         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 577 }
 578
 579
 580 void board_boot_order(u32 *spl_boot_list)
 581 {
 582         spl_boot_list[0] = spl_boot_device();
 583         printf("Boot device %x\n", spl_boot_list[0]);
 584         switch (spl_boot_list[0]) {
 585         case BOOT_DEVICE_SPI:
 586                 spl_boot_list[1] = BOOT_DEVICE_UART;
 587                 break;
 588         case BOOT_DEVICE_MMC1:
 589                 spl_boot_list[1] = BOOT_DEVICE_SPI;
 590                 spl_boot_list[2] = BOOT_DEVICE_UART;
 591                 break;
 592         default:
 593                 printf("Boot device %x\n", spl_boot_list[0]);
 594         }
 595 }
 596
 597 /*
 598  * This is used because get_ram_size() does not
 599  * take care of cache, resulting a wrong size
 600  * pfla02 has just 1, 2 or 4 GB option
 601  * Function checks for mirrors in the first CS
 602  */
 603 #define RAM_TEST_PATTERN        0xaa5555aa
 604 #define MIN_BANK_SIZE           (512 * 1024 * 1024)
 605
 606 static unsigned int pfla02_detect_chiptype(void)
 607 {
 608         u32 *p, *p1;
 609         unsigned int offset = MIN_BANK_SIZE;
 610         int i;
 611
 612         for (i = 0; i < 2; i++) {
 613                 p = (u32 *)PHYS_SDRAM;
 614                 p1 = (u32 *)(PHYS_SDRAM + (i + 1) * offset);
 615
 616                 *p1 = 0;
 617                 *p = RAM_TEST_PATTERN;
 618
 619                 /*
 620                  *  This is required to detect mirroring
 621                  *  else we read back values from cache
 622                  */
 623                 flush_dcache_all();
 624
 625                 if (*p == *p1)
 626                         return i;
 627         }
 628         return RAM_MT256K;
 629 }
 630
 631 void board_init_f(ulong dummy)
 632 {
 633         unsigned int ramchip;
 634
 635         struct mx6_ddr_sysinfo sysinfo = {
 636                 /* width of data bus:0=16,1=32,2=64 */
 637                 .dsize = 2,
 638                 /* config for full 4GB range so that get_mem_size() works */
 639                 .cs_density = 32, /* 512 MB */
 640                 /* single chip select */
 641 #if IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)
 642                 .ncs = 1,
 643 #else
 644                 .ncs = 2,
 645 #endif
 646                 .cs1_mirror = 1,
 647                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 648                 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/,       /* RTT_Nom = RZQ/4 */
 649                 .walat = 1,     /* Write additional latency */
 650                 .ralat = 5,     /* Read additional latency */
 651                 .mif3_mode = 3, /* Command prediction working mode */
 652                 .bi_on = 1,     /* Bank interleaving enabled */
 653                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 654                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 655                 .ddr_type = DDR_TYPE_DDR3,
 656                 .refsel = 1,    /* Refresh cycles at 32KHz */
 657                 .refr = 7,      /* 8 refresh commands per refresh cycle */
 658         };
 659
 660 #ifdef CONFIG_CMD_NAND
 661         /* Enable NAND */
 662         setup_gpmi_nand();
 663 #endif
 664
 665         /* setup clock gating */
 666         ccgr_init();
 667
 668         /* setup AIPS and disable watchdog */
 669         arch_cpu_init();
 670
 671         /* setup AXI */
 672         gpr_init();
 673
 674         board_early_init_f();
 675
 676         /* setup GP timer */
 677         timer_init();
 678
 679         /* UART clocks enabled and gd valid - init serial console */
 680         preloader_console_init();
 681
 682         setup_spi();
 683
 684         setup_gpios();
 685
 686         /* DDR initialization */
 687         spl_dram_init(&sysinfo, &mt41k_xx[RAM_MT256K]);
 688         ramchip = pfla02_detect_chiptype();
 689         debug("Detected chip %d\n", ramchip);
 690 #if !IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)
 691         switch (ramchip) {
 692                 case RAM_MT64K:
 693                         sysinfo.cs_density = 6;
 694                         break;
 695                 case RAM_MT128K:
 696                         sysinfo.cs_density = 10;
 697                         break;
 698                 case RAM_MT256K:
 699                         sysinfo.cs_density = 18;
 700                         break;
 701         }
 702 #endif
 703         spl_dram_init(&sysinfo, &mt41k_xx[ramchip]);
 704
 705         /* Clear the BSS. */
 706         memset(__bss_start, 0, __bss_end - __bss_start);
 707
 708         phyflex_err006282_workaround();
 709
 710         /* load/boot image from boot device */
 711         board_init_r(NULL, 0);
 712 }
 713 #endif