board/phytec/pfla02/pfla02.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 Stefano Babic <sbabic@denx.de>
   4  */
   5
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <init.h>
   9 #include <log.h>
  10 #include <net.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/iomux.h>
  15 #include <asm/arch/crm_regs.h>
  16 #include <asm/arch/iomux.h>
  17 #include <asm/arch/mx6-pins.h>
  18 #include <asm/mach-imx/iomux-v3.h>
  19 #include <asm/mach-imx/boot_mode.h>
  20 #include <asm/mach-imx/mxc_i2c.h>
  21 #include <asm/mach-imx/spi.h>
  22 #include <env.h>
  23 #include <linux/errno.h>
  24 #include <asm/gpio.h>
  25 #include <mmc.h>
  26 #include <i2c.h>
  27 #include <fsl_esdhc_imx.h>
  28 #include <nand.h>
  29 #include <miiphy.h>
  30 #include <netdev.h>
  31 #include <asm/arch/sys_proto.h>
  32 #include <asm/sections.h>
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  37         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  38         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  39
  40 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  41         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  42         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  43
  44 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  45         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  46
  47 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  48                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  49
  50 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  51         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  52         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  53
  54 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  55
  56 #define ASRC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP  |     \
  57                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  58
  59 #define NAND_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  60                PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  61
  62 #define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 14)
  63 #define USDHC2_CD_GPIO  IMX_GPIO_NR(1, 4)
  64 #define GREEN_LED       IMX_GPIO_NR(2, 31)
  65 #define RED_LED         IMX_GPIO_NR(1, 30)
  66 #define IMX6Q_DRIVE_STRENGTH    0x30
  67
  68 int dram_init(void)
  69 {
  70         gd->ram_size = imx_ddr_size();
  71         return 0;
  72 }
  73
  74 static iomux_v3_cfg_t const uart4_pads[] = {
  75         IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  76         IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  77 };
  78
  79 static iomux_v3_cfg_t const enet_pads[] = {
  80         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  81         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC       | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  82         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  83         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  84         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  85         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  86         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  87         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  88                         MUX_PAD_CTRL(ENET_PAD_CTRL)),
  89         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
  90                         MUX_PAD_CTRL(ENET_PAD_CTRL)),
  91         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  92         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  93         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  94         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  95         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  96         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
  97                         MUX_PAD_CTRL(ENET_PAD_CTRL)),
  98         IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14     | MUX_PAD_CTRL(NO_PAD_CTRL)),
  99 };
 100
 101 static iomux_v3_cfg_t const ecspi3_pads[] = {
 102         IOMUX_PADS(PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 103         IOMUX_PADS(PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 104         IOMUX_PADS(PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 105         IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24  | MUX_PAD_CTRL(NO_PAD_CTRL)),
 106 };
 107
 108 static iomux_v3_cfg_t const gpios_pads[] = {
 109         IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 110         IOMUX_PADS(PAD_SD4_DAT4__GPIO2_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 111         IOMUX_PADS(PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 112         IOMUX_PADS(PAD_SD4_DAT6__GPIO2_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 113         IOMUX_PADS(PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 114         IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 115         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 116         IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 117 };
 118
 119 #ifdef CONFIG_CMD_NAND
 120 /* NAND */
 121 static iomux_v3_cfg_t const nfc_pads[] = {
 122         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE      | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 123         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE      | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 124         IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 125         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B  | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 126         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 127         IOMUX_PADS(PAD_NANDF_CS1__NAND_CE1_B    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 128         IOMUX_PADS(PAD_NANDF_CS2__NAND_CE2_B    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 129         IOMUX_PADS(PAD_NANDF_CS3__NAND_CE3_B    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 130         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B       | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 131         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B       | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 132         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 133         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 134         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 135         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 136         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 137         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 138         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 139         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 140         IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS       | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 141 };
 142 #endif
 143
 144 static struct i2c_pads_info i2c_pad_info = {
 145         .scl = {
 146                 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | I2C_PAD,
 147                 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | I2C_PAD,
 148                 .gp = IMX_GPIO_NR(3, 21)
 149         },
 150         .sda = {
 151                 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | I2C_PAD,
 152                 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | I2C_PAD,
 153                 .gp = IMX_GPIO_NR(3, 28)
 154         }
 155 };
 156
 157 static struct fsl_esdhc_cfg usdhc_cfg[] = {
 158         {USDHC3_BASE_ADDR,
 159         .max_bus_width = 4},
 160         {.esdhc_base = USDHC2_BASE_ADDR,
 161         .max_bus_width = 4},
 162 };
 163
 164 #if !defined(CONFIG_SPL_BUILD)
 165 static iomux_v3_cfg_t const usdhc2_pads[] = {
 166         IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 167         IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 168         IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 169         IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 170         IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 171         IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 172         IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 173         IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04       | MUX_PAD_CTRL(NO_PAD_CTRL)),
 174 };
 175 #endif
 176
 177 static iomux_v3_cfg_t const usdhc3_pads[] = {
 178         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 179         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 180         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 181         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 182         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 183         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 184         IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 185         IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 186         IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 187         IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 188 };
 189
 190 int board_mmc_get_env_dev(int devno)
 191 {
 192         return devno - 1;
 193 }
 194
 195 int board_mmc_getcd(struct mmc *mmc)
 196 {
 197         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 198         int ret = 0;
 199
 200         switch (cfg->esdhc_base) {
 201         case USDHC2_BASE_ADDR:
 202                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 203                 ret = 1;
 204                 break;
 205         case USDHC3_BASE_ADDR:
 206                 ret = 1;
 207                 break;
 208         }
 209
 210         return ret;
 211 }
 212
 213 #ifndef CONFIG_SPL_BUILD
 214 int board_mmc_init(bd_t *bis)
 215 {
 216         int ret;
 217         int i;
 218
 219         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 220                 switch (i) {
 221                 case 0:
 222                         SETUP_IOMUX_PADS(usdhc3_pads);
 223                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 224                         break;
 225                 case 1:
 226                         SETUP_IOMUX_PADS(usdhc2_pads);
 227                         gpio_direction_input(USDHC2_CD_GPIO);
 228                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 229                         break;
 230                 default:
 231                         printf("Warning: you configured more USDHC controllers"
 232                                "(%d) then supported by the board (%d)\n",
 233                                i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 234                         return -EINVAL;
 235                 }
 236
 237                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 238                 if (ret)
 239                         return ret;
 240         }
 241
 242         return 0;
 243 }
 244 #endif
 245
 246 static void setup_iomux_uart(void)
 247 {
 248         SETUP_IOMUX_PADS(uart4_pads);
 249 }
 250
 251 static void setup_iomux_enet(void)
 252 {
 253         SETUP_IOMUX_PADS(enet_pads);
 254
 255         gpio_direction_output(ENET_PHY_RESET_GPIO, 0);
 256         mdelay(10);
 257         gpio_set_value(ENET_PHY_RESET_GPIO, 1);
 258         mdelay(30);
 259 }
 260
 261 static void setup_spi(void)
 262 {
 263         gpio_request(IMX_GPIO_NR(4, 24), "spi_cs0");
 264         gpio_direction_output(IMX_GPIO_NR(4, 24), 1);
 265
 266         SETUP_IOMUX_PADS(ecspi3_pads);
 267
 268         enable_spi_clk(true, 2);
 269 }
 270
 271 static void setup_gpios(void)
 272 {
 273         SETUP_IOMUX_PADS(gpios_pads);
 274 }
 275
 276 #ifdef CONFIG_CMD_NAND
 277 static void setup_gpmi_nand(void)
 278 {
 279         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 280
 281         /* config gpmi nand iomux */
 282         SETUP_IOMUX_PADS(nfc_pads);
 283
 284         /* gate ENFC_CLK_ROOT clock first,before clk source switch */
 285         clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 286
 287         /* config gpmi and bch clock to 100 MHz */
 288         clrsetbits_le32(&mxc_ccm->cs2cdr,
 289                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 290                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 291                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 292                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 293                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 294                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 295
 296         /* enable ENFC_CLK_ROOT clock */
 297         setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 298
 299         /* enable gpmi and bch clock gating */
 300         setbits_le32(&mxc_ccm->CCGR4,
 301                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 302                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 303                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 304                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 305                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 306
 307         /* enable apbh clock gating */
 308         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 309 }
 310 #endif
 311
 312 /*
 313  * Board revision is coded in 4 GPIOs
 314  */
 315 u32 get_board_rev(void)
 316 {
 317         u32 rev;
 318         int i;
 319
 320         for (i = 0, rev = 0; i < 4; i++)
 321                 rev |= (gpio_get_value(IMX_GPIO_NR(2, 12 + i)) << i);
 322
 323         return 16 - rev;
 324 }
 325
 326 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 327 {
 328         if (bus != 2 || (cs != 0))
 329                 return -EINVAL;
 330
 331         return IMX_GPIO_NR(4, 24);
 332 }
 333
 334 int board_eth_init(bd_t *bis)
 335 {
 336         setup_iomux_enet();
 337
 338         return cpu_eth_init(bis);
 339 }
 340
 341 int board_early_init_f(void)
 342 {
 343         setup_iomux_uart();
 344
 345         return 0;
 346 }
 347
 348 int board_init(void)
 349 {
 350         /* address of boot parameters */
 351         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 352
 353 #ifdef CONFIG_SYS_I2C_MXC
 354         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info);
 355 #endif
 356
 357 #ifdef CONFIG_MXC_SPI
 358         setup_spi();
 359 #endif
 360
 361         setup_gpios();
 362
 363 #ifdef CONFIG_CMD_NAND
 364         setup_gpmi_nand();
 365 #endif
 366         return 0;
 367 }
 368
 369
 370 #ifdef CONFIG_CMD_BMODE
 371 /*
 372  * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
 373  * see Table 8-11 and Table 5-9
 374  *  BOOT_CFG1[7] = 1 (boot from NAND)
 375  *  BOOT_CFG1[5] = 0 - raw NAND
 376  *  BOOT_CFG1[4] = 0 - default pad settings
 377  *  BOOT_CFG1[3:2] = 00 - devices = 1
 378  *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
 379  *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
 380  *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
 381  *  BOOT_CFG2[0] = 0 - Reset time 12ms
 382  */
 383 static const struct boot_mode board_boot_modes[] = {
 384         /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
 385         {"nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00)},
 386         {"mmc0",  MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 387         {NULL, 0},
 388 };
 389 #endif
 390
 391 int board_late_init(void)
 392 {
 393         char buf[10];
 394 #ifdef CONFIG_CMD_BMODE
 395         add_board_boot_modes(board_boot_modes);
 396 #endif
 397
 398         snprintf(buf, sizeof(buf), "%d", get_board_rev());
 399         env_set("board_rev", buf);
 400
 401         return 0;
 402 }
 403
 404 #ifdef CONFIG_SPL_BUILD
 405 #include <asm/arch/mx6-ddr.h>
 406 #include <spl.h>
 407 #include <linux/libfdt.h>
 408
 409 #define MX6_PHYFLEX_ERR006282   IMX_GPIO_NR(2, 11)
 410 static void phyflex_err006282_workaround(void)
 411 {
 412         /*
 413          * Boards beginning with 1362.2 have the SD4_DAT3 pin connected
 414          * to the CMIC. If this pin isn't toggled within 10s the boards
 415          * reset. The pin is unconnected on older boards, so we do not
 416          * need a check for older boards before applying this fixup.
 417          */
 418
 419         gpio_direction_output(MX6_PHYFLEX_ERR006282, 0);
 420         mdelay(2);
 421         gpio_direction_output(MX6_PHYFLEX_ERR006282, 1);
 422         mdelay(2);
 423         gpio_set_value(MX6_PHYFLEX_ERR006282, 0);
 424
 425         gpio_direction_input(MX6_PHYFLEX_ERR006282);
 426 }
 427
 428 static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
 429         .dram_sdclk_0 = 0x00000030,
 430         .dram_sdclk_1 = 0x00000030,
 431         .dram_cas = 0x00000030,
 432         .dram_ras = 0x00000030,
 433         .dram_reset = 0x00000030,
 434         .dram_sdcke0 = 0x00003000,
 435         .dram_sdcke1 = 0x00003000,
 436         .dram_sdba2 = 0x00000030,
 437         .dram_sdodt0 = 0x00000030,
 438         .dram_sdodt1 = 0x00000030,
 439
 440         .dram_sdqs0 = 0x00000028,
 441         .dram_sdqs1 = 0x00000028,
 442         .dram_sdqs2 = 0x00000028,
 443         .dram_sdqs3 = 0x00000028,
 444         .dram_sdqs4 = 0x00000028,
 445         .dram_sdqs5 = 0x00000028,
 446         .dram_sdqs6 = 0x00000028,
 447         .dram_sdqs7 = 0x00000028,
 448         .dram_dqm0 = 0x00000028,
 449         .dram_dqm1 = 0x00000028,
 450         .dram_dqm2 = 0x00000028,
 451         .dram_dqm3 = 0x00000028,
 452         .dram_dqm4 = 0x00000028,
 453         .dram_dqm5 = 0x00000028,
 454         .dram_dqm6 = 0x00000028,
 455         .dram_dqm7 = 0x00000028,
 456 };
 457
 458 static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
 459         .grp_ddr_type =  0x000C0000,
 460         .grp_ddrmode_ctl =  0x00020000,
 461         .grp_ddrpke =  0x00000000,
 462         .grp_addds = IMX6Q_DRIVE_STRENGTH,
 463         .grp_ctlds = IMX6Q_DRIVE_STRENGTH,
 464         .grp_ddrmode =  0x00020000,
 465         .grp_b0ds = 0x00000028,
 466         .grp_b1ds = 0x00000028,
 467         .grp_b2ds = 0x00000028,
 468         .grp_b3ds = 0x00000028,
 469         .grp_b4ds = 0x00000028,
 470         .grp_b5ds = 0x00000028,
 471         .grp_b6ds = 0x00000028,
 472         .grp_b7ds = 0x00000028,
 473 };
 474
 475 static const struct mx6_mmdc_calibration mx6_mmcd_calib = {
 476         .p0_mpwldectrl0 =  0x00110011,
 477         .p0_mpwldectrl1 =  0x00240024,
 478         .p1_mpwldectrl0 =  0x00260038,
 479         .p1_mpwldectrl1 =  0x002C0038,
 480         .p0_mpdgctrl0 =  0x03400350,
 481         .p0_mpdgctrl1 =  0x03440340,
 482         .p1_mpdgctrl0 =  0x034C0354,
 483         .p1_mpdgctrl1 =  0x035C033C,
 484         .p0_mprddlctl =  0x322A2A2A,
 485         .p1_mprddlctl =  0x302C2834,
 486         .p0_mpwrdlctl =  0x34303834,
 487         .p1_mpwrdlctl =  0x422A3E36,
 488 };
 489
 490 /* Index in RAM Chip array */
 491 enum {
 492         RAM_MT64K,
 493         RAM_MT128K,
 494         RAM_MT256K
 495 };
 496
 497 static struct mx6_ddr3_cfg mt41k_xx[] = {
 498 /* MT41K64M16JT-125 (1Gb density) */
 499         {
 500         .mem_speed = 1600,
 501         .density = 1,
 502         .width = 16,
 503         .banks = 8,
 504         .rowaddr = 13,
 505         .coladdr = 10,
 506         .pagesz = 2,
 507         .trcd = 1375,
 508         .trcmin = 4875,
 509         .trasmin = 3500,
 510         .SRT       = 1,
 511         },
 512
 513 /* MT41K256M16JT-125 (2Gb density) */
 514         {
 515         .mem_speed = 1600,
 516         .density = 2,
 517         .width = 16,
 518         .banks = 8,
 519         .rowaddr = 14,
 520         .coladdr = 10,
 521         .pagesz = 2,
 522         .trcd = 1375,
 523         .trcmin = 4875,
 524         .trasmin = 3500,
 525         .SRT       = 1,
 526         },
 527
 528 /* MT41K256M16JT-125 (4Gb density) */
 529         {
 530         .mem_speed = 1600,
 531         .density = 4,
 532         .width = 16,
 533         .banks = 8,
 534         .rowaddr = 15,
 535         .coladdr = 10,
 536         .pagesz = 2,
 537         .trcd = 1375,
 538         .trcmin = 4875,
 539         .trasmin = 3500,
 540         .SRT       = 1,
 541         }
 542 };
 543
 544 static void ccgr_init(void)
 545 {
 546         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 547
 548         writel(0x00C03F3F, &ccm->CCGR0);
 549         writel(0x0030FC03, &ccm->CCGR1);
 550         writel(0x0FFFC000, &ccm->CCGR2);
 551         writel(0x3FF00000, &ccm->CCGR3);
 552         writel(0x00FFF300, &ccm->CCGR4);
 553         writel(0x0F0000C3, &ccm->CCGR5);
 554         writel(0x000003FF, &ccm->CCGR6);
 555 }
 556
 557 static void spl_dram_init(struct mx6_ddr_sysinfo *sysinfo,
 558                                 struct mx6_ddr3_cfg *mem_ddr)
 559 {
 560         mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 561         mx6_dram_cfg(sysinfo, &mx6_mmcd_calib, mem_ddr);
 562 }
 563
 564 int board_mmc_init(bd_t *bis)
 565 {
 566         if (spl_boot_device() == BOOT_DEVICE_SPI)
 567                 printf("MMC SEtup, Boot SPI");
 568
 569         SETUP_IOMUX_PADS(usdhc3_pads);
 570         usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 571         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 572         usdhc_cfg[0].max_bus_width = 4;
 573         gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 574
 575         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 576 }
 577
 578
 579 void board_boot_order(u32 *spl_boot_list)
 580 {
 581         spl_boot_list[0] = spl_boot_device();
 582         printf("Boot device %x\n", spl_boot_list[0]);
 583         switch (spl_boot_list[0]) {
 584         case BOOT_DEVICE_SPI:
 585                 spl_boot_list[1] = BOOT_DEVICE_UART;
 586                 break;
 587         case BOOT_DEVICE_MMC1:
 588                 spl_boot_list[1] = BOOT_DEVICE_SPI;
 589                 spl_boot_list[2] = BOOT_DEVICE_UART;
 590                 break;
 591         default:
 592                 printf("Boot device %x\n", spl_boot_list[0]);
 593         }
 594 }
 595
 596 /*
 597  * This is used because get_ram_size() does not
 598  * take care of cache, resulting a wrong size
 599  * pfla02 has just 1, 2 or 4 GB option
 600  * Function checks for mirrors in the first CS
 601  */
 602 #define RAM_TEST_PATTERN        0xaa5555aa
 603 #define MIN_BANK_SIZE           (512 * 1024 * 1024)
 604
 605 static unsigned int pfla02_detect_chiptype(void)
 606 {
 607         u32 *p, *p1;
 608         unsigned int offset = MIN_BANK_SIZE;
 609         int i;
 610
 611         for (i = 0; i < 2; i++) {
 612                 p = (u32 *)PHYS_SDRAM;
 613                 p1 = (u32 *)(PHYS_SDRAM + (i + 1) * offset);
 614
 615                 *p1 = 0;
 616                 *p = RAM_TEST_PATTERN;
 617
 618                 /*
 619                  *  This is required to detect mirroring
 620                  *  else we read back values from cache
 621                  */
 622                 flush_dcache_all();
 623
 624                 if (*p == *p1)
 625                         return i;
 626         }
 627         return RAM_MT256K;
 628 }
 629
 630 void board_init_f(ulong dummy)
 631 {
 632         unsigned int ramchip;
 633
 634         struct mx6_ddr_sysinfo sysinfo = {
 635                 /* width of data bus:0=16,1=32,2=64 */
 636                 .dsize = 2,
 637                 /* config for full 4GB range so that get_mem_size() works */
 638                 .cs_density = 32, /* 512 MB */
 639                 /* single chip select */
 640 #if IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)
 641                 .ncs = 1,
 642 #else
 643                 .ncs = 2,
 644 #endif
 645                 .cs1_mirror = 1,
 646                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 647                 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/,       /* RTT_Nom = RZQ/4 */
 648                 .walat = 1,     /* Write additional latency */
 649                 .ralat = 5,     /* Read additional latency */
 650                 .mif3_mode = 3, /* Command prediction working mode */
 651                 .bi_on = 1,     /* Bank interleaving enabled */
 652                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 653                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 654                 .ddr_type = DDR_TYPE_DDR3,
 655                 .refsel = 1,    /* Refresh cycles at 32KHz */
 656                 .refr = 7,      /* 8 refresh commands per refresh cycle */
 657         };
 658
 659 #ifdef CONFIG_CMD_NAND
 660         /* Enable NAND */
 661         setup_gpmi_nand();
 662 #endif
 663
 664         /* setup clock gating */
 665         ccgr_init();
 666
 667         /* setup AIPS and disable watchdog */
 668         arch_cpu_init();
 669
 670         /* setup AXI */
 671         gpr_init();
 672
 673         board_early_init_f();
 674
 675         /* setup GP timer */
 676         timer_init();
 677
 678         /* UART clocks enabled and gd valid - init serial console */
 679         preloader_console_init();
 680
 681         setup_spi();
 682
 683         setup_gpios();
 684
 685         /* DDR initialization */
 686         spl_dram_init(&sysinfo, &mt41k_xx[RAM_MT256K]);
 687         ramchip = pfla02_detect_chiptype();
 688         debug("Detected chip %d\n", ramchip);
 689 #if !IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)
 690         switch (ramchip) {
 691                 case RAM_MT64K:
 692                         sysinfo.cs_density = 6;
 693                         break;
 694                 case RAM_MT128K:
 695                         sysinfo.cs_density = 10;
 696                         break;
 697                 case RAM_MT256K:
 698                         sysinfo.cs_density = 18;
 699                         break;
 700         }
 701 #endif
 702         spl_dram_init(&sysinfo, &mt41k_xx[ramchip]);
 703
 704         /* Clear the BSS. */
 705         memset(__bss_start, 0, __bss_end - __bss_start);
 706
 707         phyflex_err006282_workaround();
 708
 709         /* load/boot image from boot device */
 710         board_init_r(NULL, 0);
 711 }
 712 #endif