board/phytec/pfla02/pfla02.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 Stefano Babic <sbabic@denx.de>
   4  */
   5
   6 #include <common.h>
   7 #include <asm/io.h>
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/arch/iomux.h>
  11 #include <asm/arch/crm_regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <asm/mach-imx/iomux-v3.h>
  15 #include <asm/mach-imx/boot_mode.h>
  16 #include <asm/mach-imx/mxc_i2c.h>
  17 #include <asm/mach-imx/spi.h>
  18 #include <env.h>
  19 #include <linux/errno.h>
  20 #include <asm/gpio.h>
  21 #include <mmc.h>
  22 #include <i2c.h>
  23 #include <fsl_esdhc_imx.h>
  24 #include <nand.h>
  25 #include <miiphy.h>
  26 #include <netdev.h>
  27 #include <asm/arch/sys_proto.h>
  28 #include <asm/sections.h>
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  33         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  34         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  35
  36 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  37         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  38         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  39
  40 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  41         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  42
  43 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  44                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  45
  46 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  47         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  48         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  49
  50 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  51
  52 #define ASRC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP  |     \
  53                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  54
  55 #define NAND_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  56                PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  57
  58 #define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 14)
  59 #define USDHC2_CD_GPIO  IMX_GPIO_NR(1, 4)
  60 #define GREEN_LED       IMX_GPIO_NR(2, 31)
  61 #define RED_LED         IMX_GPIO_NR(1, 30)
  62 #define IMX6Q_DRIVE_STRENGTH    0x30
  63
  64 int dram_init(void)
  65 {
  66         gd->ram_size = imx_ddr_size();
  67         return 0;
  68 }
  69
  70 static iomux_v3_cfg_t const uart4_pads[] = {
  71         IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  72         IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  73 };
  74
  75 static iomux_v3_cfg_t const enet_pads[] = {
  76         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  77         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC       | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  78         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  79         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  80         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  81         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  82         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  83         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  84                         MUX_PAD_CTRL(ENET_PAD_CTRL)),
  85         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
  86                         MUX_PAD_CTRL(ENET_PAD_CTRL)),
  87         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  88         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  89         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  90         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  91         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3     | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  92         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
  93                         MUX_PAD_CTRL(ENET_PAD_CTRL)),
  94         IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14     | MUX_PAD_CTRL(NO_PAD_CTRL)),
  95 };
  96
  97 static iomux_v3_cfg_t const ecspi3_pads[] = {
  98         IOMUX_PADS(PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  99         IOMUX_PADS(PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 100         IOMUX_PADS(PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 101         IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24  | MUX_PAD_CTRL(NO_PAD_CTRL)),
 102 };
 103
 104 static iomux_v3_cfg_t const gpios_pads[] = {
 105         IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 106         IOMUX_PADS(PAD_SD4_DAT4__GPIO2_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 107         IOMUX_PADS(PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 108         IOMUX_PADS(PAD_SD4_DAT6__GPIO2_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 109         IOMUX_PADS(PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 110         IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 111         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 112         IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 113 };
 114
 115 #ifdef CONFIG_CMD_NAND
 116 /* NAND */
 117 static iomux_v3_cfg_t const nfc_pads[] = {
 118         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE      | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 119         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE      | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 120         IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 121         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B  | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 122         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 123         IOMUX_PADS(PAD_NANDF_CS1__NAND_CE1_B    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 124         IOMUX_PADS(PAD_NANDF_CS2__NAND_CE2_B    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 125         IOMUX_PADS(PAD_NANDF_CS3__NAND_CE3_B    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 126         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B       | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 127         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B       | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 128         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 129         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 130         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 131         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 132         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 133         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 134         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 135         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07    | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 136         IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS       | MUX_PAD_CTRL(NAND_PAD_CTRL)),
 137 };
 138 #endif
 139
 140 static struct i2c_pads_info i2c_pad_info = {
 141         .scl = {
 142                 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | I2C_PAD,
 143                 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | I2C_PAD,
 144                 .gp = IMX_GPIO_NR(3, 21)
 145         },
 146         .sda = {
 147                 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | I2C_PAD,
 148                 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | I2C_PAD,
 149                 .gp = IMX_GPIO_NR(3, 28)
 150         }
 151 };
 152
 153 static struct fsl_esdhc_cfg usdhc_cfg[] = {
 154         {USDHC3_BASE_ADDR,
 155         .max_bus_width = 4},
 156         {.esdhc_base = USDHC2_BASE_ADDR,
 157         .max_bus_width = 4},
 158 };
 159
 160 #if !defined(CONFIG_SPL_BUILD)
 161 static iomux_v3_cfg_t const usdhc2_pads[] = {
 162         IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 163         IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 164         IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 165         IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 166         IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 167         IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 168         IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 169         IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04       | MUX_PAD_CTRL(NO_PAD_CTRL)),
 170 };
 171 #endif
 172
 173 static iomux_v3_cfg_t const usdhc3_pads[] = {
 174         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 175         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 176         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 177         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 178         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 179         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 180         IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 181         IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 182         IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 183         IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 184 };
 185
 186 int board_mmc_get_env_dev(int devno)
 187 {
 188         return devno - 1;
 189 }
 190
 191 int board_mmc_getcd(struct mmc *mmc)
 192 {
 193         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 194         int ret = 0;
 195
 196         switch (cfg->esdhc_base) {
 197         case USDHC2_BASE_ADDR:
 198                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 199                 ret = 1;
 200                 break;
 201         case USDHC3_BASE_ADDR:
 202                 ret = 1;
 203                 break;
 204         }
 205
 206         return ret;
 207 }
 208
 209 #ifndef CONFIG_SPL_BUILD
 210 int board_mmc_init(bd_t *bis)
 211 {
 212         int ret;
 213         int i;
 214
 215         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 216                 switch (i) {
 217                 case 0:
 218                         SETUP_IOMUX_PADS(usdhc3_pads);
 219                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 220                         break;
 221                 case 1:
 222                         SETUP_IOMUX_PADS(usdhc2_pads);
 223                         gpio_direction_input(USDHC2_CD_GPIO);
 224                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 225                         break;
 226                 default:
 227                         printf("Warning: you configured more USDHC controllers"
 228                                "(%d) then supported by the board (%d)\n",
 229                                i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 230                         return -EINVAL;
 231                 }
 232
 233                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 234                 if (ret)
 235                         return ret;
 236         }
 237
 238         return 0;
 239 }
 240 #endif
 241
 242 static void setup_iomux_uart(void)
 243 {
 244         SETUP_IOMUX_PADS(uart4_pads);
 245 }
 246
 247 static void setup_iomux_enet(void)
 248 {
 249         SETUP_IOMUX_PADS(enet_pads);
 250
 251         gpio_direction_output(ENET_PHY_RESET_GPIO, 0);
 252         mdelay(10);
 253         gpio_set_value(ENET_PHY_RESET_GPIO, 1);
 254         mdelay(30);
 255 }
 256
 257 static void setup_spi(void)
 258 {
 259         gpio_request(IMX_GPIO_NR(4, 24), "spi_cs0");
 260         gpio_direction_output(IMX_GPIO_NR(4, 24), 1);
 261
 262         SETUP_IOMUX_PADS(ecspi3_pads);
 263
 264         enable_spi_clk(true, 2);
 265 }
 266
 267 static void setup_gpios(void)
 268 {
 269         SETUP_IOMUX_PADS(gpios_pads);
 270 }
 271
 272 #ifdef CONFIG_CMD_NAND
 273 static void setup_gpmi_nand(void)
 274 {
 275         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 276
 277         /* config gpmi nand iomux */
 278         SETUP_IOMUX_PADS(nfc_pads);
 279
 280         /* gate ENFC_CLK_ROOT clock first,before clk source switch */
 281         clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 282
 283         /* config gpmi and bch clock to 100 MHz */
 284         clrsetbits_le32(&mxc_ccm->cs2cdr,
 285                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 286                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 287                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 288                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 289                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 290                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 291
 292         /* enable ENFC_CLK_ROOT clock */
 293         setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 294
 295         /* enable gpmi and bch clock gating */
 296         setbits_le32(&mxc_ccm->CCGR4,
 297                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 298                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 299                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 300                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 301                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 302
 303         /* enable apbh clock gating */
 304         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 305 }
 306 #endif
 307
 308 /*
 309  * Board revision is coded in 4 GPIOs
 310  */
 311 u32 get_board_rev(void)
 312 {
 313         u32 rev;
 314         int i;
 315
 316         for (i = 0, rev = 0; i < 4; i++)
 317                 rev |= (gpio_get_value(IMX_GPIO_NR(2, 12 + i)) << i);
 318
 319         return 16 - rev;
 320 }
 321
 322 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 323 {
 324         if (bus != 2 || (cs != 0))
 325                 return -EINVAL;
 326
 327         return IMX_GPIO_NR(4, 24);
 328 }
 329
 330 int board_eth_init(bd_t *bis)
 331 {
 332         setup_iomux_enet();
 333
 334         return cpu_eth_init(bis);
 335 }
 336
 337 int board_early_init_f(void)
 338 {
 339         setup_iomux_uart();
 340
 341         return 0;
 342 }
 343
 344 int board_init(void)
 345 {
 346         /* address of boot parameters */
 347         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 348
 349 #ifdef CONFIG_SYS_I2C_MXC
 350         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info);
 351 #endif
 352
 353 #ifdef CONFIG_MXC_SPI
 354         setup_spi();
 355 #endif
 356
 357         setup_gpios();
 358
 359 #ifdef CONFIG_CMD_NAND
 360         setup_gpmi_nand();
 361 #endif
 362         return 0;
 363 }
 364
 365
 366 #ifdef CONFIG_CMD_BMODE
 367 /*
 368  * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
 369  * see Table 8-11 and Table 5-9
 370  *  BOOT_CFG1[7] = 1 (boot from NAND)
 371  *  BOOT_CFG1[5] = 0 - raw NAND
 372  *  BOOT_CFG1[4] = 0 - default pad settings
 373  *  BOOT_CFG1[3:2] = 00 - devices = 1
 374  *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
 375  *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
 376  *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
 377  *  BOOT_CFG2[0] = 0 - Reset time 12ms
 378  */
 379 static const struct boot_mode board_boot_modes[] = {
 380         /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
 381         {"nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00)},
 382         {"mmc0",  MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 383         {NULL, 0},
 384 };
 385 #endif
 386
 387 int board_late_init(void)
 388 {
 389         char buf[10];
 390 #ifdef CONFIG_CMD_BMODE
 391         add_board_boot_modes(board_boot_modes);
 392 #endif
 393
 394         snprintf(buf, sizeof(buf), "%d", get_board_rev());
 395         env_set("board_rev", buf);
 396
 397         return 0;
 398 }
 399
 400 #ifdef CONFIG_SPL_BUILD
 401 #include <asm/arch/mx6-ddr.h>
 402 #include <spl.h>
 403 #include <linux/libfdt.h>
 404
 405 #define MX6_PHYFLEX_ERR006282   IMX_GPIO_NR(2, 11)
 406 static void phyflex_err006282_workaround(void)
 407 {
 408         /*
 409          * Boards beginning with 1362.2 have the SD4_DAT3 pin connected
 410          * to the CMIC. If this pin isn't toggled within 10s the boards
 411          * reset. The pin is unconnected on older boards, so we do not
 412          * need a check for older boards before applying this fixup.
 413          */
 414
 415         gpio_direction_output(MX6_PHYFLEX_ERR006282, 0);
 416         mdelay(2);
 417         gpio_direction_output(MX6_PHYFLEX_ERR006282, 1);
 418         mdelay(2);
 419         gpio_set_value(MX6_PHYFLEX_ERR006282, 0);
 420
 421         gpio_direction_input(MX6_PHYFLEX_ERR006282);
 422 }
 423
 424 static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
 425         .dram_sdclk_0 = 0x00000030,
 426         .dram_sdclk_1 = 0x00000030,
 427         .dram_cas = 0x00000030,
 428         .dram_ras = 0x00000030,
 429         .dram_reset = 0x00000030,
 430         .dram_sdcke0 = 0x00003000,
 431         .dram_sdcke1 = 0x00003000,
 432         .dram_sdba2 = 0x00000030,
 433         .dram_sdodt0 = 0x00000030,
 434         .dram_sdodt1 = 0x00000030,
 435
 436         .dram_sdqs0 = 0x00000028,
 437         .dram_sdqs1 = 0x00000028,
 438         .dram_sdqs2 = 0x00000028,
 439         .dram_sdqs3 = 0x00000028,
 440         .dram_sdqs4 = 0x00000028,
 441         .dram_sdqs5 = 0x00000028,
 442         .dram_sdqs6 = 0x00000028,
 443         .dram_sdqs7 = 0x00000028,
 444         .dram_dqm0 = 0x00000028,
 445         .dram_dqm1 = 0x00000028,
 446         .dram_dqm2 = 0x00000028,
 447         .dram_dqm3 = 0x00000028,
 448         .dram_dqm4 = 0x00000028,
 449         .dram_dqm5 = 0x00000028,
 450         .dram_dqm6 = 0x00000028,
 451         .dram_dqm7 = 0x00000028,
 452 };
 453
 454 static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
 455         .grp_ddr_type =  0x000C0000,
 456         .grp_ddrmode_ctl =  0x00020000,
 457         .grp_ddrpke =  0x00000000,
 458         .grp_addds = IMX6Q_DRIVE_STRENGTH,
 459         .grp_ctlds = IMX6Q_DRIVE_STRENGTH,
 460         .grp_ddrmode =  0x00020000,
 461         .grp_b0ds = 0x00000028,
 462         .grp_b1ds = 0x00000028,
 463         .grp_b2ds = 0x00000028,
 464         .grp_b3ds = 0x00000028,
 465         .grp_b4ds = 0x00000028,
 466         .grp_b5ds = 0x00000028,
 467         .grp_b6ds = 0x00000028,
 468         .grp_b7ds = 0x00000028,
 469 };
 470
 471 static const struct mx6_mmdc_calibration mx6_mmcd_calib = {
 472         .p0_mpwldectrl0 =  0x00110011,
 473         .p0_mpwldectrl1 =  0x00240024,
 474         .p1_mpwldectrl0 =  0x00260038,
 475         .p1_mpwldectrl1 =  0x002C0038,
 476         .p0_mpdgctrl0 =  0x03400350,
 477         .p0_mpdgctrl1 =  0x03440340,
 478         .p1_mpdgctrl0 =  0x034C0354,
 479         .p1_mpdgctrl1 =  0x035C033C,
 480         .p0_mprddlctl =  0x322A2A2A,
 481         .p1_mprddlctl =  0x302C2834,
 482         .p0_mpwrdlctl =  0x34303834,
 483         .p1_mpwrdlctl =  0x422A3E36,
 484 };
 485
 486 /* Index in RAM Chip array */
 487 enum {
 488         RAM_MT64K,
 489         RAM_MT128K,
 490         RAM_MT256K
 491 };
 492
 493 static struct mx6_ddr3_cfg mt41k_xx[] = {
 494 /* MT41K64M16JT-125 (1Gb density) */
 495         {
 496         .mem_speed = 1600,
 497         .density = 1,
 498         .width = 16,
 499         .banks = 8,
 500         .rowaddr = 13,
 501         .coladdr = 10,
 502         .pagesz = 2,
 503         .trcd = 1375,
 504         .trcmin = 4875,
 505         .trasmin = 3500,
 506         .SRT       = 1,
 507         },
 508
 509 /* MT41K256M16JT-125 (2Gb density) */
 510         {
 511         .mem_speed = 1600,
 512         .density = 2,
 513         .width = 16,
 514         .banks = 8,
 515         .rowaddr = 14,
 516         .coladdr = 10,
 517         .pagesz = 2,
 518         .trcd = 1375,
 519         .trcmin = 4875,
 520         .trasmin = 3500,
 521         .SRT       = 1,
 522         },
 523
 524 /* MT41K256M16JT-125 (4Gb density) */
 525         {
 526         .mem_speed = 1600,
 527         .density = 4,
 528         .width = 16,
 529         .banks = 8,
 530         .rowaddr = 15,
 531         .coladdr = 10,
 532         .pagesz = 2,
 533         .trcd = 1375,
 534         .trcmin = 4875,
 535         .trasmin = 3500,
 536         .SRT       = 1,
 537         }
 538 };
 539
 540 static void ccgr_init(void)
 541 {
 542         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 543
 544         writel(0x00C03F3F, &ccm->CCGR0);
 545         writel(0x0030FC03, &ccm->CCGR1);
 546         writel(0x0FFFC000, &ccm->CCGR2);
 547         writel(0x3FF00000, &ccm->CCGR3);
 548         writel(0x00FFF300, &ccm->CCGR4);
 549         writel(0x0F0000C3, &ccm->CCGR5);
 550         writel(0x000003FF, &ccm->CCGR6);
 551 }
 552
 553 static void spl_dram_init(struct mx6_ddr_sysinfo *sysinfo,
 554                                 struct mx6_ddr3_cfg *mem_ddr)
 555 {
 556         mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 557         mx6_dram_cfg(sysinfo, &mx6_mmcd_calib, mem_ddr);
 558 }
 559
 560 int board_mmc_init(bd_t *bis)
 561 {
 562         if (spl_boot_device() == BOOT_DEVICE_SPI)
 563                 printf("MMC SEtup, Boot SPI");
 564
 565         SETUP_IOMUX_PADS(usdhc3_pads);
 566         usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 567         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 568         usdhc_cfg[0].max_bus_width = 4;
 569         gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 570
 571         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 572 }
 573
 574
 575 void board_boot_order(u32 *spl_boot_list)
 576 {
 577         spl_boot_list[0] = spl_boot_device();
 578         printf("Boot device %x\n", spl_boot_list[0]);
 579         switch (spl_boot_list[0]) {
 580         case BOOT_DEVICE_SPI:
 581                 spl_boot_list[1] = BOOT_DEVICE_UART;
 582                 break;
 583         case BOOT_DEVICE_MMC1:
 584                 spl_boot_list[1] = BOOT_DEVICE_SPI;
 585                 spl_boot_list[2] = BOOT_DEVICE_UART;
 586                 break;
 587         default:
 588                 printf("Boot device %x\n", spl_boot_list[0]);
 589         }
 590 }
 591
 592 /*
 593  * This is used because get_ram_size() does not
 594  * take care of cache, resulting a wrong size
 595  * pfla02 has just 1, 2 or 4 GB option
 596  * Function checks for mirrors in the first CS
 597  */
 598 #define RAM_TEST_PATTERN        0xaa5555aa
 599 #define MIN_BANK_SIZE           (512 * 1024 * 1024)
 600
 601 static unsigned int pfla02_detect_chiptype(void)
 602 {
 603         u32 *p, *p1;
 604         unsigned int offset = MIN_BANK_SIZE;
 605         int i;
 606
 607         for (i = 0; i < 2; i++) {
 608                 p = (u32 *)PHYS_SDRAM;
 609                 p1 = (u32 *)(PHYS_SDRAM + (i + 1) * offset);
 610
 611                 *p1 = 0;
 612                 *p = RAM_TEST_PATTERN;
 613
 614                 /*
 615                  *  This is required to detect mirroring
 616                  *  else we read back values from cache
 617                  */
 618                 flush_dcache_all();
 619
 620                 if (*p == *p1)
 621                         return i;
 622         }
 623         return RAM_MT256K;
 624 }
 625
 626 void board_init_f(ulong dummy)
 627 {
 628         unsigned int ramchip;
 629
 630         struct mx6_ddr_sysinfo sysinfo = {
 631                 /* width of data bus:0=16,1=32,2=64 */
 632                 .dsize = 2,
 633                 /* config for full 4GB range so that get_mem_size() works */
 634                 .cs_density = 32, /* 512 MB */
 635                 /* single chip select */
 636 #if IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)
 637                 .ncs = 1,
 638 #else
 639                 .ncs = 2,
 640 #endif
 641                 .cs1_mirror = 1,
 642                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 643                 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/,       /* RTT_Nom = RZQ/4 */
 644                 .walat = 1,     /* Write additional latency */
 645                 .ralat = 5,     /* Read additional latency */
 646                 .mif3_mode = 3, /* Command prediction working mode */
 647                 .bi_on = 1,     /* Bank interleaving enabled */
 648                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 649                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 650                 .ddr_type = DDR_TYPE_DDR3,
 651                 .refsel = 1,    /* Refresh cycles at 32KHz */
 652                 .refr = 7,      /* 8 refresh commands per refresh cycle */
 653         };
 654
 655 #ifdef CONFIG_CMD_NAND
 656         /* Enable NAND */
 657         setup_gpmi_nand();
 658 #endif
 659
 660         /* setup clock gating */
 661         ccgr_init();
 662
 663         /* setup AIPS and disable watchdog */
 664         arch_cpu_init();
 665
 666         /* setup AXI */
 667         gpr_init();
 668
 669         board_early_init_f();
 670
 671         /* setup GP timer */
 672         timer_init();
 673
 674         /* UART clocks enabled and gd valid - init serial console */
 675         preloader_console_init();
 676
 677         setup_spi();
 678
 679         setup_gpios();
 680
 681         /* DDR initialization */
 682         spl_dram_init(&sysinfo, &mt41k_xx[RAM_MT256K]);
 683         ramchip = pfla02_detect_chiptype();
 684         debug("Detected chip %d\n", ramchip);
 685 #if !IS_ENABLED(CONFIG_SPL_DRAM_1_BANK)
 686         switch (ramchip) {
 687                 case RAM_MT64K:
 688                         sysinfo.cs_density = 6;
 689                         break;
 690                 case RAM_MT128K:
 691                         sysinfo.cs_density = 10;
 692                         break;
 693                 case RAM_MT256K:
 694                         sysinfo.cs_density = 18;
 695                         break;
 696         }
 697 #endif
 698         spl_dram_init(&sysinfo, &mt41k_xx[ramchip]);
 699
 700         /* Clear the BSS. */
 701         memset(__bss_start, 0, __bss_end - __bss_start);
 702
 703         phyflex_err006282_workaround();
 704
 705         /* load/boot image from boot device */
 706         board_init_r(NULL, 0);
 707 }
 708 #endif